target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Weijie Gao <weijie.gao@mediatek.com>
   5  */
   6
   7 #ifndef _MT753X_H_
   8 #define _MT753X_H_
   9
  10 #include <linux/list.h>
  11 #include <linux/mutex.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/of_mdio.h>
  14 #include <linux/workqueue.h>
  15 #include <linux/gpio/consumer.h>
  16
  17 #ifdef CONFIG_SWCONFIG
  18 #include <linux/switch.h>
  19 #endif
  20
  21 #include "mt753x_vlan.h"
  22
  23 #define MT753X_DFL_CPU_PORT     6
  24 #define MT753X_NUM_PHYS         5
  25
  26 #define MT753X_DFL_SMI_ADDR     0x1f
  27 #define MT753X_SMI_ADDR_MASK    0x1f
  28
  29 struct gsw_mt753x;
  30
  31 enum mt753x_model {
  32         MT7530 = 0x7530,
  33         MT7531 = 0x7531
  34 };
  35
  36 struct mt753x_port_cfg {
  37         struct device_node *np;
  38         int phy_mode;
  39         u32 enabled: 1;
  40         u32 force_link: 1;
  41         u32 speed: 2;
  42         u32 duplex: 1;
  43 };
  44
  45 struct mt753x_phy {
  46         struct gsw_mt753x *gsw;
  47         struct net_device netdev;
  48         struct phy_device *phydev;
  49 };
  50
  51 struct gsw_mt753x {
  52         u32 id;
  53
  54         struct device *dev;
  55         struct mii_bus *host_bus;
  56         struct mii_bus *gphy_bus;
  57         struct mutex mii_lock;  /* MII access lock */
  58         u32 smi_addr;
  59         u32 phy_base;
  60         int direct_phy_access;
  61
  62         enum mt753x_model model;
  63         const char *name;
  64
  65         struct mt753x_port_cfg port5_cfg;
  66         struct mt753x_port_cfg port6_cfg;
  67
  68         int phy_status_poll;
  69         struct mt753x_phy phys[MT753X_NUM_PHYS];
  70
  71         int phy_link_sts;
  72
  73         int irq;
  74         int reset_pin;
  75         struct work_struct irq_worker;
  76
  77 #ifdef CONFIG_SWCONFIG
  78         struct switch_dev swdev;
  79         u32 cpu_port;
  80 #endif
  81
  82         int global_vlan_enable;
  83         struct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS];
  84         struct mt753x_port_entry port_entries[MT753X_NUM_PORTS];
  85
  86         int (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg);
  87         void (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
  88
  89         int (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
  90         void (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
  91                           u16 val);
  92
  93         struct list_head list;
  94 };
  95
  96 struct chip_rev {
  97         const char *name;
  98         u32 rev;
  99 };
 100
 101 struct mt753x_sw_id {
 102         enum mt753x_model model;
 103         int (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev);
 104         int (*init)(struct gsw_mt753x *gsw);
 105         int (*post_init)(struct gsw_mt753x *gsw);
 106 };
 107
 108 extern struct list_head mt753x_devs;
 109
 110 struct gsw_mt753x *mt753x_get_gsw(u32 id);
 111 struct gsw_mt753x *mt753x_get_first_gsw(void);
 112 void mt753x_put_gsw(void);
 113 void mt753x_lock_gsw(void);
 114
 115 u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg);
 116 void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val);
 117
 118 int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg);
 119 void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
 120
 121 int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
 122 void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
 123                       u16 val);
 124
 125 int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
 126 void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
 127                           u16 val);
 128
 129 void mt753x_irq_worker(struct work_struct *work);
 130 void mt753x_irq_enable(struct gsw_mt753x *gsw);
 131
 132 /* MDIO Indirect Access Registers */
 133 #define MII_MMD_ACC_CTL_REG             0x0d
 134 #define MMD_CMD_S                       14
 135 #define MMD_CMD_M                       0xc000
 136 #define MMD_DEVAD_S                     0
 137 #define MMD_DEVAD_M                     0x1f
 138
 139 /* MMD_CMD: MMD commands */
 140 #define MMD_ADDR                        0
 141 #define MMD_DATA                        1
 142
 143 #define MII_MMD_ADDR_DATA_REG           0x0e
 144
 145 /* Procedure of MT753x Internal Register Access
 146  *
 147  * 1. Internal Register Address
 148  *
 149  *    The MT753x has a 16-bit register address and each register is 32-bit.
 150  *    This means the lowest two bits are not used as the register address is
 151  *    4-byte aligned.
 152  *
 153  *    Rest of the valid bits are divided into two parts:
 154  *      Bit 15..6 is the Page address
 155  *      Bit 5..2 is the low address
 156  *
 157  *    -------------------------------------------------------------------
 158  *    | 15  14  13  12  11  10   9   8   7   6 | 5   4   3   2 | 1   0  |
 159  *    |----------------------------------------|---------------|--------|
 160  *    |              Page Address              |    Address    | Unused |
 161  *    -------------------------------------------------------------------
 162  *
 163  * 2. MDIO access timing
 164  *
 165  *    The MT753x uses the following MDIO timing for a single register read
 166  *
 167  *      Phase 1: Write Page Address
 168  *    -------------------------------------------------------------------
 169  *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |  RSVD |    PAGE_ADDR    |
 170  *    -------------------------------------------------------------------
 171  *    | 01 | 01 |   11111  |   1  | 1111 | xx | 00000 | REG_ADDR[15..6] |
 172  *    -------------------------------------------------------------------
 173  *
 174  *      Phase 2: Write low Address & Read low word
 175  *    -------------------------------------------------------------------
 176  *    | ST | OP | PHY_ADDR | TYPE |    LOW_ADDR    | TA |      DATA     |
 177  *    -------------------------------------------------------------------
 178  *    | 01 | 10 |   11111  |   0  | REG_ADDR[5..2] | xx |  DATA[15..0]  |
 179  *    -------------------------------------------------------------------
 180  *
 181  *      Phase 3: Read high word
 182  *    -------------------------------------------------------------------
 183  *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |           DATA          |
 184  *    -------------------------------------------------------------------
 185  *    | 01 | 10 |   11111  |   1  | 0000 | xx |       DATA[31..16]      |
 186  *    -------------------------------------------------------------------
 187  *
 188  *    The MT753x uses the following MDIO timing for a single register write
 189  *
 190  *      Phase 1: Write Page Address (The same as read)
 191  *
 192  *      Phase 2: Write low Address and low word
 193  *    -------------------------------------------------------------------
 194  *    | ST | OP | PHY_ADDR | TYPE |    LOW_ADDR    | TA |      DATA     |
 195  *    -------------------------------------------------------------------
 196  *    | 01 | 01 |   11111  |   0  | REG_ADDR[5..2] | xx |  DATA[15..0]  |
 197  *    -------------------------------------------------------------------
 198  *
 199  *      Phase 3: write high word
 200  *    -------------------------------------------------------------------
 201  *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |           DATA          |
 202  *    -------------------------------------------------------------------
 203  *    | 01 | 01 |   11111  |   1  | 0000 | xx |       DATA[31..16]      |
 204  *    -------------------------------------------------------------------
 205  *
 206  */
 207
 208 /* Internal Register Address fields */
 209 #define MT753X_REG_PAGE_ADDR_S          6
 210 #define MT753X_REG_PAGE_ADDR_M          0xffc0
 211 #define MT753X_REG_ADDR_S               2
 212 #define MT753X_REG_ADDR_M               0x3c
 213 #endif /* _MT753X_H_ */