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mediatek: add v5.4 support
[openwrt/openwrt.git] / target / linux / mediatek / files-5.4 / drivers / net / phy / mtk / mt753x / mt753x_mdio.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Weijie Gao <weijie.gao@mediatek.com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/device.h>
11 #include <linux/delay.h>
12 #include <linux/reset.h>
13 #include <linux/hrtimer.h>
14 #include <linux/mii.h>
15 #include <linux/of_mdio.h>
16 #include <linux/of_platform.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_net.h>
19 #include <linux/of_irq.h>
20 #include <linux/phy.h>
21
22 #include "mt753x.h"
23 #include "mt753x_swconfig.h"
24 #include "mt753x_regs.h"
25 #include "mt753x_nl.h"
26 #include "mt7530.h"
27 #include "mt7531.h"
28
29 static u32 mt753x_id;
30 struct list_head mt753x_devs;
31 static DEFINE_MUTEX(mt753x_devs_lock);
32
33 static struct mt753x_sw_id *mt753x_sw_ids[] = {
34 &mt7530_id,
35 &mt7531_id,
36 };
37
38 u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg)
39 {
40 u32 high, low;
41
42 mutex_lock(&gsw->host_bus->mdio_lock);
43
44 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
45 (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
46
47 low = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr,
48 (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S);
49
50 high = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10);
51
52 mutex_unlock(&gsw->host_bus->mdio_lock);
53
54 return (high << 16) | (low & 0xffff);
55 }
56
57 void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)
58 {
59 mutex_lock(&gsw->host_bus->mdio_lock);
60
61 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
62 (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
63
64 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr,
65 (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff);
66
67 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16);
68
69 mutex_unlock(&gsw->host_bus->mdio_lock);
70 }
71
72 /* Indirect MDIO clause 22/45 access */
73 static int mt753x_mii_rw(struct gsw_mt753x *gsw, int phy, int reg, u16 data,
74 u32 cmd, u32 st)
75 {
76 ktime_t timeout;
77 u32 val, timeout_us;
78 int ret = 0;
79
80 timeout_us = 100000;
81 timeout = ktime_add_us(ktime_get(), timeout_us);
82 while (1) {
83 val = mt753x_reg_read(gsw, PHY_IAC);
84
85 if ((val & PHY_ACS_ST) == 0)
86 break;
87
88 if (ktime_compare(ktime_get(), timeout) > 0)
89 return -ETIMEDOUT;
90 }
91
92 val = (st << MDIO_ST_S) |
93 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
94 ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
95 ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
96
97 if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
98 val |= data & MDIO_RW_DATA_M;
99
100 mt753x_reg_write(gsw, PHY_IAC, val | PHY_ACS_ST);
101
102 timeout_us = 100000;
103 timeout = ktime_add_us(ktime_get(), timeout_us);
104 while (1) {
105 val = mt753x_reg_read(gsw, PHY_IAC);
106
107 if ((val & PHY_ACS_ST) == 0)
108 break;
109
110 if (ktime_compare(ktime_get(), timeout) > 0)
111 return -ETIMEDOUT;
112 }
113
114 if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
115 val = mt753x_reg_read(gsw, PHY_IAC);
116 ret = val & MDIO_RW_DATA_M;
117 }
118
119 return ret;
120 }
121
122 int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg)
123 {
124 int val;
125
126 if (phy < MT753X_NUM_PHYS)
127 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
128
129 mutex_lock(&gsw->mii_lock);
130 val = mt753x_mii_rw(gsw, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
131 mutex_unlock(&gsw->mii_lock);
132
133 return val;
134 }
135
136 void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)
137 {
138 if (phy < MT753X_NUM_PHYS)
139 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
140
141 mutex_lock(&gsw->mii_lock);
142 mt753x_mii_rw(gsw, phy, reg, val, MDIO_CMD_WRITE, MDIO_ST_C22);
143 mutex_unlock(&gsw->mii_lock);
144 }
145
146 int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
147 {
148 int val;
149
150 if (addr < MT753X_NUM_PHYS)
151 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
152
153 mutex_lock(&gsw->mii_lock);
154 mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
155 val = mt753x_mii_rw(gsw, addr, devad, 0, MDIO_CMD_READ_C45,
156 MDIO_ST_C45);
157 mutex_unlock(&gsw->mii_lock);
158
159 return val;
160 }
161
162 void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
163 u16 val)
164 {
165 if (addr < MT753X_NUM_PHYS)
166 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
167
168 mutex_lock(&gsw->mii_lock);
169 mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
170 mt753x_mii_rw(gsw, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45);
171 mutex_unlock(&gsw->mii_lock);
172 }
173
174 int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
175 {
176 u16 val;
177
178 if (addr < MT753X_NUM_PHYS)
179 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
180
181 mutex_lock(&gsw->mii_lock);
182
183 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
184 (MMD_ADDR << MMD_CMD_S) |
185 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
186 MDIO_CMD_WRITE, MDIO_ST_C22);
187
188 mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
189 MDIO_CMD_WRITE, MDIO_ST_C22);
190
191 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
192 (MMD_DATA << MMD_CMD_S) |
193 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
194 MDIO_CMD_WRITE, MDIO_ST_C22);
195
196 val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0,
197 MDIO_CMD_READ, MDIO_ST_C22);
198
199 mutex_unlock(&gsw->mii_lock);
200
201 return val;
202 }
203
204 void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
205 u16 val)
206 {
207 if (addr < MT753X_NUM_PHYS)
208 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
209
210 mutex_lock(&gsw->mii_lock);
211
212 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
213 (MMD_ADDR << MMD_CMD_S) |
214 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
215 MDIO_CMD_WRITE, MDIO_ST_C22);
216
217 mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
218 MDIO_CMD_WRITE, MDIO_ST_C22);
219
220 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
221 (MMD_DATA << MMD_CMD_S) |
222 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
223 MDIO_CMD_WRITE, MDIO_ST_C22);
224
225 mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val,
226 MDIO_CMD_WRITE, MDIO_ST_C22);
227
228 mutex_unlock(&gsw->mii_lock);
229 }
230
231 static inline int mt753x_get_duplex(const struct device_node *np)
232 {
233 return of_property_read_bool(np, "full-duplex");
234 }
235
236 static void mt753x_load_port_cfg(struct gsw_mt753x *gsw)
237 {
238 struct device_node *port_np;
239 struct device_node *fixed_link_node;
240 struct mt753x_port_cfg *port_cfg;
241 u32 port;
242
243 for_each_child_of_node(gsw->dev->of_node, port_np) {
244 if (!of_device_is_compatible(port_np, "mediatek,mt753x-port"))
245 continue;
246
247 if (!of_device_is_available(port_np))
248 continue;
249
250 if (of_property_read_u32(port_np, "reg", &port))
251 continue;
252
253 switch (port) {
254 case 5:
255 port_cfg = &gsw->port5_cfg;
256 break;
257 case 6:
258 port_cfg = &gsw->port6_cfg;
259 break;
260 default:
261 continue;
262 }
263
264 if (port_cfg->enabled) {
265 dev_info(gsw->dev, "duplicated node for port%d\n",
266 port_cfg->phy_mode);
267 continue;
268 }
269
270 port_cfg->np = port_np;
271
272 port_cfg->phy_mode = of_get_phy_mode(port_np);
273 if (port_cfg->phy_mode < 0) {
274 dev_info(gsw->dev, "incorrect phy-mode %d\n", port);
275 continue;
276 }
277
278 fixed_link_node = of_get_child_by_name(port_np, "fixed-link");
279 if (fixed_link_node) {
280 u32 speed;
281
282 port_cfg->force_link = 1;
283 port_cfg->duplex = mt753x_get_duplex(fixed_link_node);
284
285 if (of_property_read_u32(fixed_link_node, "speed",
286 &speed)) {
287 speed = 0;
288 continue;
289 }
290
291 of_node_put(fixed_link_node);
292
293 switch (speed) {
294 case 10:
295 port_cfg->speed = MAC_SPD_10;
296 break;
297 case 100:
298 port_cfg->speed = MAC_SPD_100;
299 break;
300 case 1000:
301 port_cfg->speed = MAC_SPD_1000;
302 break;
303 case 2500:
304 port_cfg->speed = MAC_SPD_2500;
305 break;
306 default:
307 dev_info(gsw->dev, "incorrect speed %d\n",
308 speed);
309 continue;
310 }
311 }
312
313 port_cfg->enabled = 1;
314 }
315 }
316
317 static void mt753x_add_gsw(struct gsw_mt753x *gsw)
318 {
319 mutex_lock(&mt753x_devs_lock);
320 gsw->id = mt753x_id++;
321 INIT_LIST_HEAD(&gsw->list);
322 list_add_tail(&gsw->list, &mt753x_devs);
323 mutex_unlock(&mt753x_devs_lock);
324 }
325
326 static void mt753x_remove_gsw(struct gsw_mt753x *gsw)
327 {
328 mutex_lock(&mt753x_devs_lock);
329 list_del(&gsw->list);
330 mutex_unlock(&mt753x_devs_lock);
331 }
332
333
334 struct gsw_mt753x *mt753x_get_gsw(u32 id)
335 {
336 struct gsw_mt753x *dev;
337
338 mutex_lock(&mt753x_devs_lock);
339
340 list_for_each_entry(dev, &mt753x_devs, list) {
341 if (dev->id == id)
342 return dev;
343 }
344
345 mutex_unlock(&mt753x_devs_lock);
346
347 return NULL;
348 }
349
350 struct gsw_mt753x *mt753x_get_first_gsw(void)
351 {
352 struct gsw_mt753x *dev;
353
354 mutex_lock(&mt753x_devs_lock);
355
356 list_for_each_entry(dev, &mt753x_devs, list)
357 return dev;
358
359 mutex_unlock(&mt753x_devs_lock);
360
361 return NULL;
362 }
363
364 void mt753x_put_gsw(void)
365 {
366 mutex_unlock(&mt753x_devs_lock);
367 }
368
369 void mt753x_lock_gsw(void)
370 {
371 mutex_lock(&mt753x_devs_lock);
372 }
373
374 static int mt753x_hw_reset(struct gsw_mt753x *gsw)
375 {
376 struct device_node *np = gsw->dev->of_node;
377 struct reset_control *rstc;
378 int mcm;
379 int ret = -EINVAL;
380
381 mcm = of_property_read_bool(np, "mediatek,mcm");
382 if (mcm) {
383 rstc = devm_reset_control_get(gsw->dev, "mcm");
384 ret = IS_ERR(rstc);
385 if (IS_ERR(rstc)) {
386 dev_err(gsw->dev, "Missing reset ctrl of switch\n");
387 return ret;
388 }
389
390 reset_control_assert(rstc);
391 msleep(30);
392 reset_control_deassert(rstc);
393
394 gsw->reset_pin = -1;
395 return 0;
396 }
397
398 gsw->reset_pin = of_get_named_gpio(np, "reset-gpios", 0);
399 if (gsw->reset_pin < 0) {
400 dev_err(gsw->dev, "Missing reset pin of switch\n");
401 return ret;
402 }
403
404 ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mt753x-reset");
405 if (ret) {
406 dev_info(gsw->dev, "Failed to request gpio %d\n",
407 gsw->reset_pin);
408 return ret;
409 }
410
411 gpio_direction_output(gsw->reset_pin, 0);
412 msleep(30);
413 gpio_set_value(gsw->reset_pin, 1);
414 msleep(500);
415
416 return 0;
417 }
418
419 static irqreturn_t mt753x_irq_handler(int irq, void *dev)
420 {
421 struct gsw_mt753x *gsw = dev;
422
423 disable_irq_nosync(gsw->irq);
424
425 schedule_work(&gsw->irq_worker);
426
427 return IRQ_HANDLED;
428 }
429
430 static int mt753x_probe(struct platform_device *pdev)
431 {
432 struct gsw_mt753x *gsw;
433 struct mt753x_sw_id *sw;
434 struct device_node *np = pdev->dev.of_node;
435 struct device_node *mdio;
436 struct mii_bus *mdio_bus;
437 int ret = -EINVAL;
438 struct chip_rev rev;
439 struct mt753x_mapping *map;
440 int i;
441
442 mdio = of_parse_phandle(np, "mediatek,mdio", 0);
443 if (!mdio)
444 return -EINVAL;
445
446 mdio_bus = of_mdio_find_bus(mdio);
447 if (!mdio_bus)
448 return -EPROBE_DEFER;
449
450 gsw = devm_kzalloc(&pdev->dev, sizeof(struct gsw_mt753x), GFP_KERNEL);
451 if (!gsw)
452 return -ENOMEM;
453
454 gsw->host_bus = mdio_bus;
455 gsw->dev = &pdev->dev;
456 mutex_init(&gsw->mii_lock);
457
458 /* Switch hard reset */
459 if (mt753x_hw_reset(gsw))
460 goto fail;
461
462 /* Fetch the SMI address dirst */
463 if (of_property_read_u32(np, "mediatek,smi-addr", &gsw->smi_addr))
464 gsw->smi_addr = MT753X_DFL_SMI_ADDR;
465
466 /* Get LAN/WAN port mapping */
467 map = mt753x_find_mapping(np);
468 if (map) {
469 mt753x_apply_mapping(gsw, map);
470 gsw->global_vlan_enable = 1;
471 dev_info(gsw->dev, "LAN/WAN VLAN setting=%s\n", map->name);
472 }
473
474 /* Load MAC port configurations */
475 mt753x_load_port_cfg(gsw);
476
477 /* Check for valid switch and then initialize */
478 for (i = 0; i < ARRAY_SIZE(mt753x_sw_ids); i++) {
479 if (!mt753x_sw_ids[i]->detect(gsw, &rev)) {
480 sw = mt753x_sw_ids[i];
481
482 gsw->name = rev.name;
483 gsw->model = sw->model;
484
485 dev_info(gsw->dev, "Switch is MediaTek %s rev %d",
486 gsw->name, rev.rev);
487
488 /* Initialize the switch */
489 ret = sw->init(gsw);
490 if (ret)
491 goto fail;
492
493 break;
494 }
495 }
496
497 if (i >= ARRAY_SIZE(mt753x_sw_ids)) {
498 dev_err(gsw->dev, "No mt753x switch found\n");
499 goto fail;
500 }
501
502 gsw->irq = platform_get_irq(pdev, 0);
503 if (gsw->irq >= 0) {
504 ret = devm_request_irq(gsw->dev, gsw->irq, mt753x_irq_handler,
505 0, dev_name(gsw->dev), gsw);
506 if (ret) {
507 dev_err(gsw->dev, "Failed to request irq %d\n",
508 gsw->irq);
509 goto fail;
510 }
511
512 INIT_WORK(&gsw->irq_worker, mt753x_irq_worker);
513 }
514
515 platform_set_drvdata(pdev, gsw);
516
517 gsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node,
518 "mediatek,phy-poll");
519
520 mt753x_add_gsw(gsw);
521
522 mt753x_swconfig_init(gsw);
523
524 if (sw->post_init)
525 sw->post_init(gsw);
526
527 if (gsw->irq >= 0)
528 mt753x_irq_enable(gsw);
529
530 return 0;
531
532 fail:
533 devm_kfree(&pdev->dev, gsw);
534
535 return ret;
536 }
537
538 static int mt753x_remove(struct platform_device *pdev)
539 {
540 struct gsw_mt753x *gsw = platform_get_drvdata(pdev);
541
542 if (gsw->irq >= 0)
543 cancel_work_sync(&gsw->irq_worker);
544
545 if (gsw->reset_pin >= 0)
546 devm_gpio_free(&pdev->dev, gsw->reset_pin);
547
548 #ifdef CONFIG_SWCONFIG
549 mt753x_swconfig_destroy(gsw);
550 #endif
551
552 mt753x_remove_gsw(gsw);
553
554 platform_set_drvdata(pdev, NULL);
555
556 return 0;
557 }
558
559 static const struct of_device_id mt753x_ids[] = {
560 { .compatible = "mediatek,mt753x" },
561 { },
562 };
563
564 MODULE_DEVICE_TABLE(of, mt753x_ids);
565
566 static struct platform_driver mt753x_driver = {
567 .probe = mt753x_probe,
568 .remove = mt753x_remove,
569 .driver = {
570 .name = "mt753x",
571 .of_match_table = mt753x_ids,
572 },
573 };
574
575 static int __init mt753x_init(void)
576 {
577 int ret;
578
579 INIT_LIST_HEAD(&mt753x_devs);
580 ret = platform_driver_register(&mt753x_driver);
581
582 mt753x_nl_init();
583
584 return ret;
585 }
586 module_init(mt753x_init);
587
588 static void __exit mt753x_exit(void)
589 {
590 mt753x_nl_exit();
591
592 platform_driver_unregister(&mt753x_driver);
593 }
594 module_exit(mt753x_exit);
595
596 MODULE_LICENSE("GPL");
597 MODULE_AUTHOR("Weijie Gao <weijie.gao@mediatek.com>");
598 MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch");
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