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[openwrt/openwrt.git] / target / linux / mediatek / files / arch / arm / boot / dts / _mt7623.dtsi
1 /*
2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: John Crispin <blogic@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/clock/mt2701-clk.h>
18 #include <dt-bindings/power/mt2701-power.h>
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/reset-controller/mt2701-resets.h>
21 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
22 #include "skeleton64.dtsi"
23
24
25 / {
26 compatible = "mediatek,mt7623";
27 interrupt-parent = <&sysirq>;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "mediatek,mt6589-smp";
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a7";
37 reg = <0x0>;
38 clocks = <&infracfg CLK_INFRA_CPUSEL>,
39 <&apmixedsys CLK_APMIXED_MAINPLL>;
40 clock-names = "cpu", "intermediate";
41 operating-points = <
42 598000 1150000
43 747500 1150000
44 1040000 1150000
45 1196000 1200000
46 1300000 1300000
47 >;
48 };
49 cpu1: cpu@1 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0x1>;
53 clocks = <&infracfg CLK_INFRA_CPUSEL>,
54 <&apmixedsys CLK_APMIXED_MAINPLL>;
55 clock-names = "cpu", "intermediate";
56 operating-points = <
57 598000 1150000
58 747500 1150000
59 1040000 1150000
60 1196000 1200000
61 1300000 1300000
62 >;
63 };
64 cpu2: cpu@2 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 reg = <0x2>;
68 clocks = <&infracfg CLK_INFRA_CPUSEL>,
69 <&apmixedsys CLK_APMIXED_MAINPLL>;
70 clock-names = "cpu", "intermediate";
71 operating-points = <
72 598000 1150000
73 747500 1150000
74 1040000 1150000
75 1196000 1200000
76 1300000 1300000
77 >;
78 };
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a7";
82 reg = <0x3>;
83 clocks = <&infracfg CLK_INFRA_CPUSEL>,
84 <&apmixedsys CLK_APMIXED_MAINPLL>;
85 clock-names = "cpu", "intermediate";
86 operating-points = <
87 598000 1150000
88 747500 1150000
89 1040000 1150000
90 1196000 1200000
91 1300000 1300000
92 >;
93 };
94 };
95
96 system_clk: dummy13m {
97 compatible = "fixed-clock";
98 clock-frequency = <13000000>;
99 #clock-cells = <0>;
100 };
101
102 rtc_clk: dummy32k {
103 compatible = "fixed-clock";
104 clock-frequency = <32000>;
105 #clock-cells = <0>;
106 clock-output-names = "clk32k";
107 };
108
109 clk26m: dummy26m {
110 compatible = "fixed-clock";
111 clock-frequency = <26000000>;
112 #clock-cells = <0>;
113 clock-output-names = "clk26m";
114 };
115
116 timer {
117 compatible = "arm,armv7-timer";
118 interrupt-parent = <&gic>;
119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
123 clock-frequency = <13000000>;
124 arm,cpu-registers-not-fw-configured;
125 };
126
127 topckgen: power-controller@10000000 {
128 compatible = "mediatek,mt7623-topckgen",
129 "mediatek,mt2701-topckgen",
130 "syscon";
131 reg = <0 0x10000000 0 0x1000>;
132 #clock-cells = <1>;
133 };
134
135 infracfg: power-controller@10001000 {
136 compatible = "mediatek,mt7623-infracfg",
137 "mediatek,mt2701-infracfg",
138 "syscon";
139 reg = <0 0x10001000 0 0x1000>;
140 #clock-cells = <1>;
141 #reset-cells = <1>;
142 };
143
144 pericfg: pericfg@10003000 {
145 compatible = "mediatek,mt7623-pericfg",
146 "mediatek,mt2701-pericfg",
147 "syscon";
148 reg = <0 0x10003000 0 0x1000>;
149 #clock-cells = <1>;
150 #reset-cells = <1>;
151 };
152
153 pio: pinctrl@10005000 {
154 compatible = "mediatek,mt7623-pinctrl";
155 reg = <0 0x1000b000 0 0x1000>;
156 mediatek,pctl-regmap = <&syscfg_pctl_a>;
157 pins-are-numbered;
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 interrupt-parent = <&gic>;
162 #interrupt-cells = <2>;
163 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
165 };
166
167 syscfg_pctl_a: syscfg@10005000 {
168 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
169 reg = <0 0x10005000 0 0x1000>;
170 };
171
172 scpsys: scpsys@10006000 {
173 #power-domain-cells = <1>;
174 compatible = "mediatek,mt7623-scpsys",
175 "mediatek,mt2701-scpsys";
176 reg = <0 0x10006000 0 0x1000>;
177 infracfg = <&infracfg>;
178 clocks = <&clk26m>,
179 <&topckgen CLK_TOP_MM_SEL>;
180 clock-names = "mfg", "mm";
181 };
182
183 watchdog: watchdog@10007000 {
184 compatible = "mediatek,mt7623-wdt",
185 "mediatek,mt6589-wdt";
186 reg = <0 0x10007000 0 0x100>;
187 };
188
189 timer: timer@10008000 {
190 compatible = "mediatek,mt7623-timer",
191 "mediatek,mt6577-timer";
192 reg = <0 0x10008000 0 0x80>;
193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
194 clocks = <&system_clk>, <&rtc_clk>;
195 clock-names = "system-clk", "rtc-clk";
196 };
197
198 pwrap: pwrap@1000d000 {
199 compatible = "mediatek,mt7623-pwrap",
200 "mediatek,mt2701-pwrap";
201 reg = <0 0x1000d000 0 0x1000>;
202 reg-names = "pwrap";
203 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
204 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
205 reset-names = "pwrap";
206 clocks = <&infracfg CLK_INFRA_PMICSPI>,
207 <&infracfg CLK_INFRA_PMICWRAP>;
208 clock-names = "spi", "wrap";
209 };
210
211 sysirq: interrupt-controller@10200100 {
212 compatible = "mediatek,mt7623-sysirq",
213 "mediatek,mt6577-sysirq";
214 interrupt-controller;
215 #interrupt-cells = <3>;
216 interrupt-parent = <&gic>;
217 reg = <0 0x10200100 0 0x1c>;
218 };
219
220 apmixedsys: apmixedsys@10209000 {
221 compatible = "mediatek,mt7623-apmixedsys",
222 "mediatek,mt2701-apmixedsys";
223 reg = <0 0x10209000 0 0x1000>;
224 #clock-cells = <1>;
225 };
226
227 gic: interrupt-controller@10211000 {
228 compatible = "arm,cortex-a7-gic";
229 interrupt-controller;
230 #interrupt-cells = <3>;
231 interrupt-parent = <&gic>;
232 reg = <0 0x10211000 0 0x1000>,
233 <0 0x10212000 0 0x1000>,
234 <0 0x10214000 0 0x2000>,
235 <0 0x10216000 0 0x2000>;
236 };
237
238 i2c0: i2c@11007000 {
239 compatible = "mediatek,mt7623-i2c",
240 "mediatek,mt6577-i2c";
241 reg = <0 0x11007000 0 0x70>,
242 <0 0x11000200 0 0x80>;
243 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
244 clock-div = <16>;
245 clocks = <&pericfg CLK_PERI_I2C0>,
246 <&pericfg CLK_PERI_AP_DMA>;
247 clock-names = "main", "dma";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 status = "disabled";
251 };
252
253 i2c1: i2c@11008000 {
254 compatible = "mediatek,mt7623-i2c",
255 "mediatek,mt6577-i2c";
256 reg = <0 0x11008000 0 0x70>,
257 <0 0x11000280 0 0x80>;
258 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
259 clock-div = <16>;
260 clocks = <&pericfg CLK_PERI_I2C1>,
261 <&pericfg CLK_PERI_AP_DMA>;
262 clock-names = "main", "dma";
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
268 i2c2: i2c@11009000 {
269 compatible = "mediatek,mt7623-i2c",
270 "mediatek,mt6577-i2c";
271 reg = <0 0x11009000 0 0x70>,
272 <0 0x11000300 0 0x80>;
273 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
274 clock-div = <16>;
275 clocks = <&pericfg CLK_PERI_I2C2>,
276 <&pericfg CLK_PERI_AP_DMA>;
277 clock-names = "main", "dma";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 status = "disabled";
281 };
282
283 uart0: serial@11002000 {
284 compatible = "mediatek,mt7623-uart",
285 "mediatek,mt6577-uart";
286 reg = <0 0x11002000 0 0x400>;
287 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
288 clocks = <&pericfg CLK_PERI_UART0_SEL>,
289 <&pericfg CLK_PERI_UART0>;
290 clock-names = "baud", "bus";
291 status = "disabled";
292 };
293
294 uart1: serial@11003000 {
295 compatible = "mediatek,mt7623-uart",
296 "mediatek,mt6577-uart";
297 reg = <0 0x11003000 0 0x400>;
298 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
299 clocks = <&pericfg CLK_PERI_UART1_SEL>,
300 <&pericfg CLK_PERI_UART1>;
301 clock-names = "baud", "bus";
302 status = "disabled";
303 };
304
305 uart2: serial@11004000 {
306 compatible = "mediatek,mt7623-uart",
307 "mediatek,mt6577-uart";
308 reg = <0 0x11004000 0 0x400>;
309 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
310 clocks = <&pericfg CLK_PERI_UART2_SEL>,
311 <&pericfg CLK_PERI_UART2>;
312 clock-names = "baud", "bus";
313 status = "disabled";
314 };
315
316 uart3: serial@11005000 {
317 compatible = "mediatek,mt7623-uart",
318 "mediatek,mt6577-uart";
319 reg = <0 0x11005000 0 0x400>;
320 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
321 clocks = <&pericfg CLK_PERI_UART3_SEL>,
322 <&pericfg CLK_PERI_UART3>;
323 clock-names = "baud", "bus";
324 status = "disabled";
325 };
326
327 pwm: pwm@11006000 {
328 compatible = "mediatek,mt7623-pwm";
329
330 reg = <0 0x11006000 0 0x1000>;
331
332 resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
333 reset-names = "pwm";
334
335 #pwm-cells = <2>;
336 clocks = <&topckgen CLK_TOP_PWM_SEL>,
337 <&pericfg CLK_PERI_PWM>,
338 <&pericfg CLK_PERI_PWM1>,
339 <&pericfg CLK_PERI_PWM2>,
340 <&pericfg CLK_PERI_PWM3>,
341 <&pericfg CLK_PERI_PWM4>,
342 <&pericfg CLK_PERI_PWM5>;
343 clock-names = "top", "main", "pwm1", "pwm2",
344 "pwm3", "pwm4", "pwm5";
345
346 status = "disabled";
347 };
348
349 spi: spi@1100a000 {
350 compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
351 reg = <0 0x1100a000 0 0x1000>;
352 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
353 clocks = <&pericfg CLK_PERI_SPI0>;
354 clock-names = "main";
355
356 status = "disabled";
357 };
358
359 nandc: nfi@1100d000 {
360 compatible = "mediatek,mt2701-nfc";
361 reg = <0 0x1100d000 0 0x1000>;
362 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
363 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
364 clocks = <&pericfg CLK_PERI_NFI>,
365 <&pericfg CLK_PERI_NFI_PAD>;
366 clock-names = "nfi_clk", "pad_clk";
367 status = "disabled";
368 ecc-engine = <&bch>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 };
372
373 bch: ecc@1100e000 {
374 compatible = "mediatek,mt2701-ecc";
375 reg = <0 0x1100e000 0 0x1000>;
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
377 clocks = <&pericfg CLK_PERI_NFI_ECC>;
378 clock-names = "nfiecc_clk";
379 status = "disabled";
380 };
381
382 mmc0: mmc@11230000 {
383 compatible = "mediatek,mt7623-mmc",
384 "mediatek,mt8135-mmc";
385 reg = <0 0x11230000 0 0x1000>;
386 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
387 clocks = <&pericfg CLK_PERI_MSDC30_0>,
388 <&topckgen CLK_TOP_MSDC30_0_SEL>;
389 clock-names = "source", "hclk";
390 status = "disabled";
391 };
392
393 mmc1: mmc@11240000 {
394 compatible = "mediatek,mt7623-mmc",
395 "mediatek,mt8135-mmc";
396 reg = <0 0x11240000 0 0x1000>;
397 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
398 clocks = <&pericfg CLK_PERI_MSDC30_1>,
399 <&topckgen CLK_TOP_MSDC30_1_SEL>;
400 clock-names = "source", "hclk";
401 status = "disabled";
402 };
403
404 usb1: usb@1a1c0000 {
405 compatible = "mediatek,mt2701-xhci",
406 "mediatek,mt8173-xhci";
407 reg = <0 0x1a1c0000 0 0x1000>,
408 <0 0x1a1c4700 0 0x0100>;
409 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
410 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
411 <&topckgen CLK_TOP_ETHIF_SEL>;
412 clock-names = "sys_ck", "ethif";
413 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
414 phys = <&phy_port0 PHY_TYPE_USB3>;
415 status = "disabled";
416 };
417
418 u3phy1: usb-phy@1a1c4000 {
419 compatible = "mediatek,mt2701-u3phy",
420 "mediatek,mt8173-u3phy";
421 reg = <0 0x1a1c4000 0 0x0700>;
422 clocks = <&clk26m>;
423 clock-names = "u3phya_ref";
424 #phy-cells = <1>;
425 #address-cells = <2>;
426 #size-cells = <2>;
427 ranges;
428 status = "disabled";
429
430 phy_port0: phy_port0: port@1a1c4800 {
431 reg = <0 0x1a1c4800 0 0x800>;
432 #phy-cells = <1>;
433 status = "okay";
434 };
435 };
436
437 usb2: usb@1a240000 {
438 compatible = "mediatek,mt2701-xhci",
439 "mediatek,mt8173-xhci";
440 reg = <0 0x1a240000 0 0x1000>,
441 <0 0x1a244700 0 0x0100>;
442 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
444 <&topckgen CLK_TOP_ETHIF_SEL>;
445 clock-names = "sys_ck", "ethif";
446 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
447 phys = <&u3phy2 0>;
448 status = "disabled";
449 };
450
451 u3phy2: usb-phy@1a244000 {
452 compatible = "mediatek,mt2701-u3phy",
453 "mediatek,mt8173-u3phy";
454 reg = <0 0x1a244000 0 0x0700>,
455 <0 0x1a244800 0 0x0800>;
456 clocks = <&clk26m>;
457 clock-names = "u3phya_ref";
458 #phy-cells = <1>;
459 status = "disabled";
460 };
461
462 hifsys: clock-controller@1a000000 {
463 compatible = "mediatek,mt7623-hifsys",
464 "mediatek,mt2701-hifsys",
465 "syscon";
466 reg = <0 0x1a000000 0 0x1000>;
467 #clock-cells = <1>;
468 #reset-cells = <1>;
469 };
470
471 pcie: pcie@1a140000 {
472 compatible = "mediatek,mt7623-pcie";
473 device_type = "pci";
474 reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
475 <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
476 <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
477 <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
478 reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
479 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
480 <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
481 <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
482 interrupt-names = "pcie0", "pcie1", "pcie2";
483 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
484 clock-names = "pcie";
485 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
486 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
487 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
488 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
489 reset-names = "pcie0", "pcie1", "pcie2";
490
491 mediatek,hifsys = <&hifsys>;
492
493 bus-range = <0x00 0xff>;
494 #address-cells = <3>;
495 #size-cells = <2>;
496
497 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
498 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
499
500 status = "disabled";
501
502 pcie@1,0 {
503 device_type = "pci";
504 reg = <0x0800 0 0 0 0>;
505
506 #address-cells = <3>;
507 #size-cells = <2>;
508 ranges;
509 };
510
511 pcie@2,0{
512 device_type = "pci";
513 reg = <0x1000 0 0 0 0>;
514
515 #address-cells = <3>;
516 #size-cells = <2>;
517 ranges;
518 };
519
520 pcie@3,0{
521 device_type = "pci";
522 reg = <0x1800 0 0 0 0>;
523
524 #address-cells = <3>;
525 #size-cells = <2>;
526 ranges;
527 };
528 };
529
530 ethsys: syscon@1b000000 {
531 compatible = "mediatek,mt2701-ethsys", "syscon";
532 reg = <0 0x1b000000 0 0x1000>;
533 #reset-cells = <1>;
534 #clock-cells = <1>;
535 };
536
537 eth: ethernet@1b100000 {
538 compatible = "mediatek,mt7623-eth";
539 reg = <0 0x1b100000 0 0x20000>;
540
541 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
542 <&ethsys CLK_ETHSYS_ESW>,
543 <&ethsys CLK_ETHSYS_GP2>,
544 <&ethsys CLK_ETHSYS_GP1>;
545 clock-names = "ethif", "esw", "gp2", "gp1";
546 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
547 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
548 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
549 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
550
551 resets = <&ethsys 6>;
552 reset-names = "eth";
553
554 mediatek,ethsys = <&ethsys>;
555 mediatek,pctl = <&syscfg_pctl_a>;
556
557 mediatek,switch = <&gsw>;
558
559 #address-cells = <1>;
560 #size-cells = <0>;
561
562 status = "disabled";
563
564 gmac1: mac@0 {
565 compatible = "mediatek,eth-mac";
566 reg = <0>;
567
568 status = "disabled";
569
570 phy-mode = "rgmii";
571
572 fixed-link {
573 speed = <1000>;
574 full-duplex;
575 pause;
576 };
577 };
578
579 gmac2: mac@1 {
580 compatible = "mediatek,eth-mac";
581 reg = <1>;
582
583 status = "disabled";
584 };
585
586 mdio-bus {
587 #address-cells = <1>;
588 #size-cells = <0>;
589
590 phy5: ethernet-phy@5 {
591 reg = <5>;
592 phy-mode = "rgmii-rxid";
593 };
594
595 phy1f: ethernet-phy@1f {
596 reg = <0x1f>;
597 phy-mode = "rgmii";
598 };
599 };
600 };
601
602 gsw: switch@1b100000 {
603 compatible = "mediatek,mt7623-gsw";
604 interrupt-parent = <&pio>;
605 interrupts = <168 IRQ_TYPE_EDGE_RISING>;
606 resets = <&ethsys 2>;
607 reset-names = "eth";
608 clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
609 clock-names = "trgpll";
610 mt7530-supply = <&mt6323_vpa_reg>;
611 mediatek,pctl-regmap = <&syscfg_pctl_a>;
612 mediatek,ethsys = <&ethsys>;
613 status = "disabled";
614 };
615 };
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