target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch

   1 From 4422c4efeed2a8b9fa745c6e529623d89c0be75e Mon Sep 17 00:00:00 2001
   2 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
   3 Date: Fri, 13 Oct 2017 16:26:35 +0800
   4 Subject: [PATCH 128/224] usb: xhci-mtk: check clock stability of U3_MAC
   5
   6 This is useful to find out the root cause when the Super Speed doesn't
   7 work. Such as when the T-PHY is switched to PCIe or SATA, and affects
   8 Super Speed function, the check will fail.
   9
  10 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  11 Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
  12 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  13 ---
  14  drivers/usb/host/xhci-mtk.c | 4 ++++
  15  1 file changed, 4 insertions(+)
  16
  17 --- a/drivers/usb/host/xhci-mtk.c
  18 +++ b/drivers/usb/host/xhci-mtk.c
  19 @@ -43,6 +43,7 @@
  20
  21  /* ip_pw_sts1 register */
  22  #define STS1_IP_SLEEP_STS      BIT(30)
  23 +#define STS1_U3_MAC_RST        BIT(16)
  24  #define STS1_XHCI_RST          BIT(11)
  25  #define STS1_SYS125_RST        BIT(10)
  26  #define STS1_REF_RST           BIT(8)
  27 @@ -125,6 +126,9 @@ static int xhci_mtk_host_enable(struct x
  28         check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
  29                         STS1_SYS125_RST | STS1_XHCI_RST;
  30
  31 +       if (mtk->num_u3_ports)
  32 +               check_val |= STS1_U3_MAC_RST;
  33 +
  34         ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
  35                           (check_val == (value & check_val)), 100, 20000);
  36         if (ret) {