target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch

   1 From 8119f3e147deaf97a66e953fecf3d2b0edbb07fd Mon Sep 17 00:00:00 2001
   2 From: Chaotian Jing <chaotian.jing@mediatek.com>
   3 Date: Mon, 16 Oct 2017 09:46:29 +0800
   4 Subject: [PATCH 143/224] mmc: mediatek: add support of mt2701/mt2712
   5
   6 mt2701/mt2712 has 12bit clock div, which is not compatible with
   7 mt8135/mt8173. and, some additional features will be added in
   8 mt2701/mt2712, so that need distinguish it by comatibale name.
   9
  10 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
  11 Tested-by: Sean Wang <sean.wang@mediatek.com>
  12 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  13 ---
  14  drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++--------
  15  1 file changed, 69 insertions(+), 13 deletions(-)
  16
  17 --- a/drivers/mmc/host/mtk-sd.c
  18 +++ b/drivers/mmc/host/mtk-sd.c
  19 @@ -95,6 +95,9 @@
  20  #define MSDC_CFG_CKDIV          (0xff << 8)    /* RW */
  21  #define MSDC_CFG_CKMOD          (0x3 << 16)    /* RW */
  22  #define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)    /* RW */
  23 +#define MSDC_CFG_HS400_CK_MODE_EXTRA  (0x1 << 22)      /* RW */
  24 +#define MSDC_CFG_CKDIV_EXTRA    (0xfff << 8)   /* RW */
  25 +#define MSDC_CFG_CKMOD_EXTRA    (0x3 << 20)    /* RW */
  26
  27  /* MSDC_IOCON mask */
  28  #define MSDC_IOCON_SDR104CKS    (0x1 << 0)     /* RW */
  29 @@ -295,6 +298,10 @@ struct msdc_save_para {
  30         u32 emmc50_cfg0;
  31  };
  32
  33 +struct mtk_mmc_compatible {
  34 +       u8 clk_div_bits;
  35 +};
  36 +
  37  struct msdc_tune_para {
  38         u32 iocon;
  39         u32 pad_tune;
  40 @@ -309,6 +316,7 @@ struct msdc_delay_phase {
  41
  42  struct msdc_host {
  43         struct device *dev;
  44 +       const struct mtk_mmc_compatible *dev_comp;
  45         struct mmc_host *mmc;   /* mmc structure */
  46         int cmd_rsp;
  47
  48 @@ -350,6 +358,31 @@ struct msdc_host {
  49         struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
  50  };
  51
  52 +static const struct mtk_mmc_compatible mt8135_compat = {
  53 +       .clk_div_bits = 8,
  54 +};
  55 +
  56 +static const struct mtk_mmc_compatible mt8173_compat = {
  57 +       .clk_div_bits = 8,
  58 +};
  59 +
  60 +static const struct mtk_mmc_compatible mt2701_compat = {
  61 +       .clk_div_bits = 12,
  62 +};
  63 +
  64 +static const struct mtk_mmc_compatible mt2712_compat = {
  65 +       .clk_div_bits = 12,
  66 +};
  67 +
  68 +static const struct of_device_id msdc_of_ids[] = {
  69 +       { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
  70 +       { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
  71 +       { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
  72 +       { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
  73 +       {}
  74 +};
  75 +MODULE_DEVICE_TABLE(of, msdc_of_ids);
  76 +
  77  static void sdr_set_bits(void __iomem *reg, u32 bs)
  78  {
  79         u32 val = readl(reg);
  80 @@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc
  81                 timeout = (ns + clk_ns - 1) / clk_ns + clks;
  82                 /* in 1048576 sclk cycle unit */
  83                 timeout = (timeout + (0x1 << 20) - 1) >> 20;
  84 -               sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
  85 +               if (host->dev_comp->clk_div_bits == 8)
  86 +                       sdr_get_field(host->base + MSDC_CFG,
  87 +                                     MSDC_CFG_CKMOD, &mode);
  88 +               else
  89 +                       sdr_get_field(host->base + MSDC_CFG,
  90 +                                     MSDC_CFG_CKMOD_EXTRA, &mode);
  91                 /*DDR mode will double the clk cycles for data timeout */
  92                 timeout = mode >= 2 ? timeout * 2 : timeout;
  93                 timeout = timeout > 1 ? timeout - 1 : 0;
  94 @@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_ho
  95
  96         flags = readl(host->base + MSDC_INTEN);
  97         sdr_clr_bits(host->base + MSDC_INTEN, flags);
  98 -       sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
  99 +       if (host->dev_comp->clk_div_bits == 8)
 100 +               sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
 101 +       else
 102 +               sdr_clr_bits(host->base + MSDC_CFG,
 103 +                            MSDC_CFG_HS400_CK_MODE_EXTRA);
 104         if (timing == MMC_TIMING_UHS_DDR50 ||
 105             timing == MMC_TIMING_MMC_DDR52 ||
 106             timing == MMC_TIMING_MMC_HS400) {
 107 @@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_ho
 108
 109                 if (timing == MMC_TIMING_MMC_HS400 &&
 110                     hz >= (host->src_clk_freq >> 1)) {
 111 -                       sdr_set_bits(host->base + MSDC_CFG,
 112 -                                    MSDC_CFG_HS400_CK_MODE);
 113 +                       if (host->dev_comp->clk_div_bits == 8)
 114 +                               sdr_set_bits(host->base + MSDC_CFG,
 115 +                                            MSDC_CFG_HS400_CK_MODE);
 116 +                       else
 117 +                               sdr_set_bits(host->base + MSDC_CFG,
 118 +                                            MSDC_CFG_HS400_CK_MODE_EXTRA);
 119                         sclk = host->src_clk_freq >> 1;
 120                         div = 0; /* div is ignore when bit18 is set */
 121                 }
 122 @@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_ho
 123                         sclk = (host->src_clk_freq >> 2) / div;
 124                 }
 125         }
 126 -       sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
 127 -                     (mode << 8) | div);
 128 +       if (host->dev_comp->clk_div_bits == 8)
 129 +               sdr_set_field(host->base + MSDC_CFG,
 130 +                             MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
 131 +                             (mode << 8) | div);
 132 +       else
 133 +               sdr_set_field(host->base + MSDC_CFG,
 134 +                             MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
 135 +                             (mode << 12) | div);
 136 +
 137         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 138         while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 139                 cpu_relax();
 140 @@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platfor
 141         struct mmc_host *mmc;
 142         struct msdc_host *host;
 143         struct resource *res;
 144 +       const struct of_device_id *of_id;
 145         int ret;
 146
 147         if (!pdev->dev.of_node) {
 148                 dev_err(&pdev->dev, "No DT found\n");
 149                 return -EINVAL;
 150         }
 151 +
 152 +       of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
 153 +       if (!of_id)
 154 +               return -EINVAL;
 155         /* Allocate MMC host for this device */
 156         mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
 157         if (!mmc)
 158 @@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platfor
 159         msdc_of_property_parse(pdev, host);
 160
 161         host->dev = &pdev->dev;
 162 +       host->dev_comp = of_id->data;
 163         host->mmc = mmc;
 164         host->src_clk_freq = clk_get_rate(host->src_clk);
 165         /* Set host parameters to mmc */
 166         mmc->ops = &mt_msdc_ops;
 167 -       mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
 168 +       if (host->dev_comp->clk_div_bits == 8)
 169 +               mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
 170 +       else
 171 +               mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
 172
 173         mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
 174         /* MMC core transfer sizes tunable parameters */
 175 @@ -1839,12 +1901,6 @@ static const struct dev_pm_ops msdc_dev_
 176         SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
 177  };
 178
 179 -static const struct of_device_id msdc_of_ids[] = {
 180 -       {   .compatible = "mediatek,mt8135-mmc", },
 181 -       {}
 182 -};
 183 -MODULE_DEVICE_TABLE(of, msdc_of_ids);
 184 -
 185  static struct platform_driver mt_msdc_driver = {
 186         .probe = msdc_drv_probe,
 187         .remove = msdc_drv_remove,