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[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0166-mtd-nand-mtk-Support-different-MTK-NAND-flash-contro.patch
1 From fd1a1eabf2473e769b5cafc704e0336d11f61961 Mon Sep 17 00:00:00 2001
2 From: RogerCC Lin <rogercc.lin@mediatek.com>
3 Date: Thu, 30 Nov 2017 22:10:44 +0800
4 Subject: [PATCH 166/224] mtd: nand: mtk: Support different MTK NAND flash
5 controller IP
6
7 MT7622 uses an MTK's earlier NAND flash controller IP which support
8 different sector size, max spare size per sector and paraity bits...,
9 some register's offset and definition also been changed in the NAND
10 flash controller, this patch is the preparation to support MT7622
11 NAND flash controller.
12
13 MT7622 NFC and ECC engine are similar to MT2701's, except below
14 differences:
15 (1)MT7622 NFC's max sector size(ECC data size) is 512 bytes, and
16 MT2701's is 1024, and MT7622's max sector number is 8.
17 (2)The parity bit of MT7622 is 13, MT2701 is 14.
18 (3)MT7622 ECC supports less ECC strength, max to 16 bit ecc strength.
19 (4)MT7622 supports less spare size per sector, max spare size per
20 sector is 28 bytes.
21 (5)Some register's offset are different, include ECC_ENCIRQ_EN,
22 ECC_ENCIRQ_STA, ECC_DECDONE, ECC_DECIRQ_EN and ECC_DECIRQ_STA.
23 (6)ENC_MODE of ECC_ENCCNFG register is moved from bit 5-6 to bit 4-5.
24
25 Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com>
26 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
27 ---
28 drivers/mtd/nand/mtk_ecc.c | 100 ++++++++++++++++++++++++++++++--------------
29 drivers/mtd/nand/mtk_ecc.h | 3 +-
30 drivers/mtd/nand/mtk_nand.c | 27 ++++++++----
31 3 files changed, 89 insertions(+), 41 deletions(-)
32
33 diff --git a/drivers/mtd/nand/mtk_ecc.c b/drivers/mtd/nand/mtk_ecc.c
34 index c51d214d169e..6610eefaa92b 100644
35 --- a/drivers/mtd/nand/mtk_ecc.c
36 +++ b/drivers/mtd/nand/mtk_ecc.c
37 @@ -34,34 +34,28 @@
38
39 #define ECC_ENCCON (0x00)
40 #define ECC_ENCCNFG (0x04)
41 -#define ECC_MODE_SHIFT (5)
42 #define ECC_MS_SHIFT (16)
43 #define ECC_ENCDIADDR (0x08)
44 #define ECC_ENCIDLE (0x0C)
45 -#define ECC_ENCIRQ_EN (0x80)
46 -#define ECC_ENCIRQ_STA (0x84)
47 #define ECC_DECCON (0x100)
48 #define ECC_DECCNFG (0x104)
49 #define DEC_EMPTY_EN BIT(31)
50 #define DEC_CNFG_CORRECT (0x3 << 12)
51 #define ECC_DECIDLE (0x10C)
52 #define ECC_DECENUM0 (0x114)
53 -#define ECC_DECDONE (0x124)
54 -#define ECC_DECIRQ_EN (0x200)
55 -#define ECC_DECIRQ_STA (0x204)
56
57 #define ECC_TIMEOUT (500000)
58
59 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
60 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
61 -#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
62 - ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
63
64 struct mtk_ecc_caps {
65 u32 err_mask;
66 const u8 *ecc_strength;
67 + const u32 *ecc_regs;
68 u8 num_ecc_strength;
69 - u32 encode_parity_reg0;
70 + u8 ecc_mode_shift;
71 + u32 parity_bits;
72 int pg_irq_sel;
73 };
74
75 @@ -89,6 +83,33 @@ static const u8 ecc_strength_mt2712[] = {
76 40, 44, 48, 52, 56, 60, 68, 72, 80
77 };
78
79 +enum mtk_ecc_regs {
80 + ECC_ENCPAR00,
81 + ECC_ENCIRQ_EN,
82 + ECC_ENCIRQ_STA,
83 + ECC_DECDONE,
84 + ECC_DECIRQ_EN,
85 + ECC_DECIRQ_STA,
86 +};
87 +
88 +static int mt2701_ecc_regs[] = {
89 + [ECC_ENCPAR00] = 0x10,
90 + [ECC_ENCIRQ_EN] = 0x80,
91 + [ECC_ENCIRQ_STA] = 0x84,
92 + [ECC_DECDONE] = 0x124,
93 + [ECC_DECIRQ_EN] = 0x200,
94 + [ECC_DECIRQ_STA] = 0x204,
95 +};
96 +
97 +static int mt2712_ecc_regs[] = {
98 + [ECC_ENCPAR00] = 0x300,
99 + [ECC_ENCIRQ_EN] = 0x80,
100 + [ECC_ENCIRQ_STA] = 0x84,
101 + [ECC_DECDONE] = 0x124,
102 + [ECC_DECIRQ_EN] = 0x200,
103 + [ECC_DECIRQ_STA] = 0x204,
104 +};
105 +
106 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
107 enum mtk_ecc_operation op)
108 {
109 @@ -107,32 +128,30 @@ static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
110 static irqreturn_t mtk_ecc_irq(int irq, void *id)
111 {
112 struct mtk_ecc *ecc = id;
113 - enum mtk_ecc_operation op;
114 u32 dec, enc;
115
116 - dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
117 + dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
118 + & ECC_IRQ_EN;
119 if (dec) {
120 - op = ECC_DECODE;
121 - dec = readw(ecc->regs + ECC_DECDONE);
122 + dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
123 if (dec & ecc->sectors) {
124 /*
125 * Clear decode IRQ status once again to ensure that
126 * there will be no extra IRQ.
127 */
128 - readw(ecc->regs + ECC_DECIRQ_STA);
129 + readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
130 ecc->sectors = 0;
131 complete(&ecc->done);
132 } else {
133 return IRQ_HANDLED;
134 }
135 } else {
136 - enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
137 - if (enc) {
138 - op = ECC_ENCODE;
139 + enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
140 + & ECC_IRQ_EN;
141 + if (enc)
142 complete(&ecc->done);
143 - } else {
144 + else
145 return IRQ_NONE;
146 - }
147 }
148
149 return IRQ_HANDLED;
150 @@ -160,7 +179,7 @@ static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
151 /* configure ECC encoder (in bits) */
152 enc_sz = config->len << 3;
153
154 - reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
155 + reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
156 reg |= (enc_sz << ECC_MS_SHIFT);
157 writel(reg, ecc->regs + ECC_ENCCNFG);
158
159 @@ -171,9 +190,9 @@ static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
160 } else {
161 /* configure ECC decoder (in bits) */
162 dec_sz = (config->len << 3) +
163 - config->strength * ECC_PARITY_BITS;
164 + config->strength * ecc->caps->parity_bits;
165
166 - reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
167 + reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
168 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
169 reg |= DEC_EMPTY_EN;
170 writel(reg, ecc->regs + ECC_DECCNFG);
171 @@ -291,7 +310,12 @@ int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
172 */
173 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
174 reg_val |= ECC_PG_IRQ_SEL;
175 - writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
176 + if (op == ECC_ENCODE)
177 + writew(reg_val, ecc->regs +
178 + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
179 + else
180 + writew(reg_val, ecc->regs +
181 + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
182 }
183
184 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
185 @@ -310,13 +334,17 @@ void mtk_ecc_disable(struct mtk_ecc *ecc)
186
187 /* disable it */
188 mtk_ecc_wait_idle(ecc, op);
189 - if (op == ECC_DECODE)
190 + if (op == ECC_DECODE) {
191 /*
192 * Clear decode IRQ status in case there is a timeout to wait
193 * decode IRQ.
194 */
195 - readw(ecc->regs + ECC_DECIRQ_STA);
196 - writew(0, ecc->regs + ECC_IRQ_REG(op));
197 + readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
198 + writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
199 + } else {
200 + writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
201 + }
202 +
203 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
204
205 mutex_unlock(&ecc->lock);
206 @@ -367,11 +395,11 @@ int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
207 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
208
209 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
210 - len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
211 + len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
212
213 /* write the parity bytes generated by the ECC back to temp buffer */
214 __ioread32_copy(ecc->eccdata,
215 - ecc->regs + ecc->caps->encode_parity_reg0,
216 + ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
217 round_up(len, 4));
218
219 /* copy into possibly unaligned OOB region with actual length */
220 @@ -404,19 +432,29 @@ void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
221 }
222 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
223
224 +unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
225 +{
226 + return ecc->caps->parity_bits;
227 +}
228 +EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
229 +
230 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
231 .err_mask = 0x3f,
232 .ecc_strength = ecc_strength_mt2701,
233 + .ecc_regs = mt2701_ecc_regs,
234 .num_ecc_strength = 20,
235 - .encode_parity_reg0 = 0x10,
236 + .ecc_mode_shift = 5,
237 + .parity_bits = 14,
238 .pg_irq_sel = 0,
239 };
240
241 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
242 .err_mask = 0x7f,
243 .ecc_strength = ecc_strength_mt2712,
244 + .ecc_regs = mt2712_ecc_regs,
245 .num_ecc_strength = 23,
246 - .encode_parity_reg0 = 0x300,
247 + .ecc_mode_shift = 5,
248 + .parity_bits = 14,
249 .pg_irq_sel = 1,
250 };
251
252 @@ -452,7 +490,7 @@ static int mtk_ecc_probe(struct platform_device *pdev)
253
254 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
255 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
256 - max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3;
257 + max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
258 max_eccdata_size = round_up(max_eccdata_size, 4);
259 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
260 if (!ecc->eccdata)
261 diff --git a/drivers/mtd/nand/mtk_ecc.h b/drivers/mtd/nand/mtk_ecc.h
262 index d245c14f1b80..a455df080952 100644
263 --- a/drivers/mtd/nand/mtk_ecc.h
264 +++ b/drivers/mtd/nand/mtk_ecc.h
265 @@ -14,8 +14,6 @@
266
267 #include <linux/types.h>
268
269 -#define ECC_PARITY_BITS (14)
270 -
271 enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
272 enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
273
274 @@ -43,6 +41,7 @@ int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
275 int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
276 void mtk_ecc_disable(struct mtk_ecc *);
277 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
278 +unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
279
280 struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
281 void mtk_ecc_release(struct mtk_ecc *);
282 diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c
283 index 6d0101e13ef6..7349aa846f9a 100644
284 --- a/drivers/mtd/nand/mtk_nand.c
285 +++ b/drivers/mtd/nand/mtk_nand.c
286 @@ -97,7 +97,6 @@
287
288 #define MTK_TIMEOUT (500000)
289 #define MTK_RESET_TIMEOUT (1000000)
290 -#define MTK_MAX_SECTOR (16)
291 #define MTK_NAND_MAX_NSELS (2)
292 #define MTK_NFC_MIN_SPARE (16)
293 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
294 @@ -109,6 +108,8 @@ struct mtk_nfc_caps {
295 u8 num_spare_size;
296 u8 pageformat_spare_shift;
297 u8 nfi_clk_div;
298 + u8 max_sector;
299 + u32 max_sector_size;
300 };
301
302 struct mtk_nfc_bad_mark_ctl {
303 @@ -450,7 +451,7 @@ static inline u8 mtk_nfc_read_byte(struct mtd_info *mtd)
304 * set to max sector to allow the HW to continue reading over
305 * unaligned accesses
306 */
307 - reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
308 + reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
309 nfi_writel(nfc, reg, NFI_CON);
310
311 /* trigger to fetch data */
312 @@ -481,7 +482,7 @@ static void mtk_nfc_write_byte(struct mtd_info *mtd, u8 byte)
313 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
314 nfi_writew(nfc, reg, NFI_CNFG);
315
316 - reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
317 + reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
318 nfi_writel(nfc, reg, NFI_CON);
319
320 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
321 @@ -1126,9 +1127,11 @@ static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
322 {
323 struct nand_chip *nand = mtd_to_nand(mtd);
324 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
325 + struct mtk_nfc *nfc = nand_get_controller_data(nand);
326 u32 ecc_bytes;
327
328 - ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
329 + ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
330 + mtk_ecc_get_parity_bits(nfc->ecc), 8);
331
332 fdm->reg_size = chip->spare_per_sector - ecc_bytes;
333 if (fdm->reg_size > NFI_FDM_MAX_SIZE)
334 @@ -1208,7 +1211,8 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
335 * this controller only supports 512 and 1024 sizes
336 */
337 if (nand->ecc.size < 1024) {
338 - if (mtd->writesize > 512) {
339 + if (mtd->writesize > 512 &&
340 + nfc->caps->max_sector_size > 512) {
341 nand->ecc.size = 1024;
342 nand->ecc.strength <<= 1;
343 } else {
344 @@ -1223,7 +1227,8 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
345 return ret;
346
347 /* calculate oob bytes except ecc parity data */
348 - free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3;
349 + free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
350 + + 7) >> 3;
351 free = spare - free;
352
353 /*
354 @@ -1233,10 +1238,12 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
355 */
356 if (free > NFI_FDM_MAX_SIZE) {
357 spare -= NFI_FDM_MAX_SIZE;
358 - nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
359 + nand->ecc.strength = (spare << 3) /
360 + mtk_ecc_get_parity_bits(nfc->ecc);
361 } else if (free < 0) {
362 spare -= NFI_FDM_MIN_SIZE;
363 - nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
364 + nand->ecc.strength = (spare << 3) /
365 + mtk_ecc_get_parity_bits(nfc->ecc);
366 }
367 }
368
369 @@ -1389,6 +1396,8 @@ static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
370 .num_spare_size = 16,
371 .pageformat_spare_shift = 4,
372 .nfi_clk_div = 1,
373 + .max_sector = 16,
374 + .max_sector_size = 1024,
375 };
376
377 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
378 @@ -1396,6 +1405,8 @@ static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
379 .num_spare_size = 19,
380 .pageformat_spare_shift = 16,
381 .nfi_clk_div = 2,
382 + .max_sector = 16,
383 + .max_sector_size = 1024,
384 };
385
386 static const struct of_device_id mtk_nfc_id_table[] = {
387 --
388 2.11.0
389
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