target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch

   1 From 927c736a1a169713cd59140db5e82f8ed11dad60 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Fri, 29 Dec 2017 11:06:52 +0800
   4 Subject: [PATCH 212/224] arm64: dts: mt7622: add pinctrl related device nodes
   5
   6 add pinctrl device nodes and rfb1 board, additionally include all pin
   7 groups possible being used on rfb1 board and available gpio keys.
   8
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Cc: Matthias Brugger <matthias.bgg@gmail.com>
  11 ---
  12  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 200 +++++++++++++++++++++++++++
  13  arch/arm64/boot/dts/mediatek/mt7622.dtsi     |   7 +
  14  2 files changed, 207 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  17 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  18 @@ -7,6 +7,8 @@
  19   */
  20
  21  /dts-v1/;
  22 +#include <dt-bindings/input/input.h>
  23 +
  24  #include "mt7622.dtsi"
  25
  26  / {
  27 @@ -17,11 +19,209 @@
  28                 bootargs = "console=ttyS0,115200n1";
  29         };
  30
  31 +       gpio-keys {
  32 +               compatible = "gpio-keys-polled";
  33 +               poll-interval = <100>;
  34 +
  35 +               factory {
  36 +                       label = "factory";
  37 +                       linux,code = <BTN_0>;
  38 +                       gpios = <&pio 0 0>;
  39 +               };
  40 +
  41 +               wps {
  42 +                       label = "wps";
  43 +                       linux,code = <KEY_WPS_BUTTON>;
  44 +                       gpios = <&pio 102 0>;
  45 +               };
  46 +       };
  47 +
  48         memory {
  49                 reg = <0 0x40000000 0 0x3F000000>;
  50         };
  51  };
  52
  53 +&pio {
  54 +       /* eMMC is shared pin with parallel NAND */
  55 +       emmc_pins_default: emmc-pins-default {
  56 +               mux {
  57 +                       function = "emmc", "emmc_rst";
  58 +                       groups = "emmc";
  59 +               };
  60 +       };
  61 +
  62 +       emmc_pins_uhs: emmc-pins-uhs {
  63 +               mux {
  64 +                       function = "emmc";
  65 +                       groups = "emmc";
  66 +               };
  67 +       };
  68 +
  69 +       eth_pins: eth-pins {
  70 +               mux {
  71 +                       function = "eth";
  72 +                       groups = "mdc_mdio", "rgmii_via_gmac2";
  73 +               };
  74 +       };
  75 +
  76 +       i2c1_pins: i2c1-pins {
  77 +               mux {
  78 +                       function = "i2c";
  79 +                       groups =  "i2c1_0";
  80 +               };
  81 +       };
  82 +
  83 +       i2c2_pins: i2c2-pins {
  84 +               mux {
  85 +                       function = "i2c";
  86 +                       groups =  "i2c2_0";
  87 +               };
  88 +       };
  89 +
  90 +       i2s1_pins: i2s1-pins {
  91 +               mux {
  92 +                       function = "i2s";
  93 +                       groups =  "i2s_out_bclk_ws_mclk",
  94 +                                 "i2s1_in_data",
  95 +                                 "i2s1_out_data";
  96 +               };
  97 +       };
  98 +
  99 +       irrx_pins: irrx-pins {
 100 +               mux {
 101 +                       function = "ir";
 102 +                       groups =  "ir_1_rx";
 103 +               };
 104 +       };
 105 +
 106 +       irtx_pins: irtx-pins {
 107 +               mux {
 108 +                       function = "ir";
 109 +                       groups =  "ir_1_tx";
 110 +               };
 111 +       };
 112 +
 113 +       /* Parallel nand is shared pin with eMMC */
 114 +       parallel_nand_pins: parallel-nand-pins {
 115 +               mux {
 116 +                       function = "flash";
 117 +                       groups = "par_nand";
 118 +               };
 119 +       };
 120 +
 121 +       pcie0_pins: pcie0-pins {
 122 +               mux {
 123 +                       function = "pcie";
 124 +                       groups = "pcie0_pad_perst",
 125 +                                "pcie0_1_waken",
 126 +                                "pcie0_1_clkreq";
 127 +               };
 128 +       };
 129 +
 130 +       pcie1_pins: pcie1-pins {
 131 +               mux {
 132 +                       function = "pcie";
 133 +                       groups = "pcie1_pad_perst",
 134 +                                "pcie1_0_waken",
 135 +                                "pcie1_0_clkreq";
 136 +               };
 137 +       };
 138 +
 139 +       pmic_bus_pins: pmic-bus-pins {
 140 +               mux {
 141 +                       function = "pmic";
 142 +                       groups = "pmic_bus";
 143 +               };
 144 +       };
 145 +
 146 +       pwm7_pins: pwm1-2-pins {
 147 +               mux {
 148 +                       function = "pwm";
 149 +                       groups = "pwm_ch7_2";
 150 +               };
 151 +       };
 152 +
 153 +       wled_pins: wled-pins {
 154 +               mux {
 155 +                       function = "led";
 156 +                       groups = "wled";
 157 +               };
 158 +       };
 159 +
 160 +       sd0_pins_default: sd0-pins-default {
 161 +               mux {
 162 +                       function = "sd";
 163 +                       groups = "sd_0";
 164 +               };
 165 +       };
 166 +
 167 +       sd0_pins_uhs: sd0-pins-uhs {
 168 +               mux {
 169 +                       function = "sd";
 170 +                       groups = "sd_0";
 171 +               };
 172 +       };
 173 +
 174 +       /* Serial NAND is shared pin with SPI-NOR */
 175 +       serial_nand_pins: serial-nand-pins {
 176 +               mux {
 177 +                       function = "flash";
 178 +                       groups = "snfi";
 179 +               };
 180 +       };
 181 +
 182 +       spic0_pins: spic0-pins {
 183 +               mux {
 184 +                       function = "spi";
 185 +                       groups = "spic0_0";
 186 +               };
 187 +       };
 188 +
 189 +       spic1_pins: spic1-pins {
 190 +               mux {
 191 +                       function = "spi";
 192 +                       groups = "spic1_0";
 193 +               };
 194 +       };
 195 +
 196 +       /* SPI-NOR is shared pin with serial NAND */
 197 +       spi_nor_pins: spi-nor-pins {
 198 +               mux {
 199 +                       function = "flash";
 200 +                       groups = "spi_nor";
 201 +               };
 202 +       };
 203 +
 204 +       /* serial NAND is shared pin with SPI-NOR */
 205 +       serial_nand_pins: serial-nand-pins {
 206 +               mux {
 207 +                       function = "flash";
 208 +                       groups = "snfi";
 209 +               };
 210 +       };
 211 +
 212 +       uart0_pins: uart0-pins {
 213 +               mux {
 214 +                       function = "uart";
 215 +                       groups = "uart0_0_tx_rx" ;
 216 +               };
 217 +       };
 218 +
 219 +       uart2_pins: uart2-pins {
 220 +               mux {
 221 +                       function = "uart";
 222 +                       groups = "uart2_1_tx_rx" ;
 223 +               };
 224 +       };
 225 +
 226 +       watchdog_pins: watchdog-pins {
 227 +               mux {
 228 +                       function = "watchdog";
 229 +                       groups = "watchdog";
 230 +               };
 231 +       };
 232 +};
 233 +
 234  &uart0 {
 235         status = "okay";
 236  };
 237 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 238 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 239 @@ -147,6 +147,13 @@
 240                 #clock-cells = <1>;
 241         };
 242
 243 +       pio: pinctrl@10211000 {
 244 +               compatible = "mediatek,mt7622-pinctrl";
 245 +               reg = <0 0x10211000 0 0x1000>;
 246 +               gpio-controller;
 247 +               #gpio-cells = <2>;
 248 +       };
 249 +
 250         gic: interrupt-controller@10300000 {
 251                 compatible = "arm,gic-400";
 252                 interrupt-controller;