target/linux/mediatek/patches-4.19/0101-pci-mediatek-backport-fix-pcie.patch

   1 diff -urN a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
   2 --- a/drivers/clk/clk-devres.c  2019-08-29 16:59:26.540010395 +0800
   3 +++ b/drivers/clk/clk-devres.c  2019-08-29 17:02:09.215924786 +0800
   4 @@ -34,6 +34,17 @@
   5  }
   6  EXPORT_SYMBOL(devm_clk_get);
   7
   8 +struct clk *devm_clk_get_optional(struct device *dev, const char *id)
   9 +{
  10 +        struct clk *clk = devm_clk_get(dev, id);
  11 +
  12 +        if (clk == ERR_PTR(-ENOENT))
  13 +                return NULL;
  14 +
  15 +        return clk;
  16 +}
  17 +EXPORT_SYMBOL(devm_clk_get_optional);
  18 +
  19  struct clk_bulk_devres {
  20         struct clk_bulk_data *clks;
  21         int num_clks;
  22 diff -urN a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
  23 --- a/drivers/pci/controller/pcie-mediatek.c    2019-08-29 16:59:10.520410188 +0800
  24 +++ b/drivers/pci/controller/pcie-mediatek.c    2019-08-29 17:01:58.340199243 +0800
  25 @@ -15,6 +15,7 @@
  26  #include <linux/irqdomain.h>
  27  #include <linux/kernel.h>
  28  #include <linux/msi.h>
  29 +#include <linux/module.h>
  30  #include <linux/of_address.h>
  31  #include <linux/of_pci.h>
  32  #include <linux/of_platform.h>
  33 @@ -162,6 +163,7 @@
  34   * @phy: pointer to PHY control block
  35   * @lane: lane count
  36   * @slot: port slot
  37 + * @irq: GIC irq
  38   * @irq_domain: legacy INTx IRQ domain
  39   * @inner_domain: inner IRQ domain
  40   * @msi_domain: MSI IRQ domain
  41 @@ -182,6 +184,7 @@
  42         struct phy *phy;
  43         u32 lane;
  44         u32 slot;
  45 +       int irq;
  46         struct irq_domain *irq_domain;
  47         struct irq_domain *inner_domain;
  48         struct irq_domain *msi_domain;
  49 @@ -225,10 +228,8 @@
  50
  51         clk_disable_unprepare(pcie->free_ck);
  52
  53 -       if (dev->pm_domain) {
  54 -               pm_runtime_put_sync(dev);
  55 -               pm_runtime_disable(dev);
  56 -       }
  57 +       pm_runtime_put_sync(dev);
  58 +       pm_runtime_disable(dev);
  59  }
  60
  61  static void mtk_pcie_port_free(struct mtk_pcie_port *port)
  62 @@ -394,75 +395,6 @@
  63         .write = mtk_pcie_config_write,
  64  };
  65
  66 -static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
  67 -{
  68 -       struct mtk_pcie *pcie = port->pcie;
  69 -       struct resource *mem = &pcie->mem;
  70 -       const struct mtk_pcie_soc *soc = port->pcie->soc;
  71 -       u32 val;
  72 -       size_t size;
  73 -       int err;
  74 -
  75 -       /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
  76 -       if (pcie->base) {
  77 -               val = readl(pcie->base + PCIE_SYS_CFG_V2);
  78 -               val |= PCIE_CSR_LTSSM_EN(port->slot) |
  79 -                      PCIE_CSR_ASPM_L1_EN(port->slot);
  80 -               writel(val, pcie->base + PCIE_SYS_CFG_V2);
  81 -       }
  82 -
  83 -       /* Assert all reset signals */
  84 -       writel(0, port->base + PCIE_RST_CTRL);
  85 -
  86 -       /*
  87 -        * Enable PCIe link down reset, if link status changed from link up to
  88 -        * link down, this will reset MAC control registers and configuration
  89 -        * space.
  90 -        */
  91 -       writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
  92 -
  93 -       /* De-assert PHY, PE, PIPE, MAC and configuration reset */
  94 -       val = readl(port->base + PCIE_RST_CTRL);
  95 -       val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
  96 -              PCIE_MAC_SRSTB | PCIE_CRSTB;
  97 -       writel(val, port->base + PCIE_RST_CTRL);
  98 -
  99 -       /* Set up vendor ID and class code */
 100 -       if (soc->need_fix_class_id) {
 101 -               val = PCI_VENDOR_ID_MEDIATEK;
 102 -               writew(val, port->base + PCIE_CONF_VEND_ID);
 103 -
 104 -               val = PCI_CLASS_BRIDGE_HOST;
 105 -               writew(val, port->base + PCIE_CONF_CLASS_ID);
 106 -       }
 107 -
 108 -       /* 100ms timeout value should be enough for Gen1/2 training */
 109 -       err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
 110 -                                !!(val & PCIE_PORT_LINKUP_V2), 20,
 111 -                                100 * USEC_PER_MSEC);
 112 -       if (err)
 113 -               return -ETIMEDOUT;
 114 -
 115 -       /* Set INTx mask */
 116 -       val = readl(port->base + PCIE_INT_MASK);
 117 -       val &= ~INTX_MASK;
 118 -       writel(val, port->base + PCIE_INT_MASK);
 119 -
 120 -       /* Set AHB to PCIe translation windows */
 121 -       size = mem->end - mem->start;
 122 -       val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
 123 -       writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
 124 -
 125 -       val = upper_32_bits(mem->start);
 126 -       writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
 127 -
 128 -       /* Set PCIe to AXI translation memory space.*/
 129 -       val = fls(0xffffffff) | WIN_ENABLE;
 130 -       writel(val, port->base + PCIE_AXI_WINDOW0);
 131 -
 132 -       return 0;
 133 -}
 134 -
 135  static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 136  {
 137         struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
 138 @@ -601,6 +533,27 @@
 139         writel(val, port->base + PCIE_INT_MASK);
 140  }
 141
 142 +static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
 143 +{
 144 +       struct mtk_pcie_port *port, *tmp;
 145 +
 146 +       list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 147 +               irq_set_chained_handler_and_data(port->irq, NULL, NULL);
 148 +
 149 +               if (port->irq_domain)
 150 +                       irq_domain_remove(port->irq_domain);
 151 +
 152 +               if (IS_ENABLED(CONFIG_PCI_MSI)) {
 153 +                       if (port->msi_domain)
 154 +                               irq_domain_remove(port->msi_domain);
 155 +                       if (port->inner_domain)
 156 +                               irq_domain_remove(port->inner_domain);
 157 +               }
 158 +
 159 +               irq_dispose_mapping(port->irq);
 160 +       }
 161 +}
 162 +
 163  static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 164                              irq_hw_number_t hwirq)
 165  {
 166 @@ -630,6 +583,7 @@
 167
 168         port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
 169                                                  &intx_domain_ops, port);
 170 +       of_node_put(pcie_intc_node);
 171         if (!port->irq_domain) {
 172                 dev_err(dev, "failed to get INTx IRQ domain\n");
 173                 return -ENODEV;
 174 @@ -639,8 +593,6 @@
 175                 ret = mtk_pcie_allocate_msi_domains(port);
 176                 if (ret)
 177                         return ret;
 178 -
 179 -               mtk_pcie_enable_msi(port);
 180         }
 181
 182         return 0;
 183 @@ -693,7 +645,7 @@
 184         struct mtk_pcie *pcie = port->pcie;
 185         struct device *dev = pcie->dev;
 186         struct platform_device *pdev = to_platform_device(dev);
 187 -       int err, irq;
 188 +       int err;
 189
 190         err = mtk_pcie_init_irq_domain(port, node);
 191         if (err) {
 192 @@ -701,8 +653,81 @@
 193                 return err;
 194         }
 195
 196 -       irq = platform_get_irq(pdev, port->slot);
 197 -       irq_set_chained_handler_and_data(irq, mtk_pcie_intr_handler, port);
 198 +       port->irq = platform_get_irq(pdev, port->slot);
 199 +       irq_set_chained_handler_and_data(port->irq,
 200 +                                        mtk_pcie_intr_handler, port);
 201 +
 202 +       return 0;
 203 +}
 204 +
 205 +static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
 206 +{
 207 +       struct mtk_pcie *pcie = port->pcie;
 208 +       struct resource *mem = &pcie->mem;
 209 +       const struct mtk_pcie_soc *soc = port->pcie->soc;
 210 +       u32 val;
 211 +       size_t size;
 212 +       int err;
 213 +
 214 +       /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
 215 +       if (pcie->base) {
 216 +               val = readl(pcie->base + PCIE_SYS_CFG_V2);
 217 +               val |= PCIE_CSR_LTSSM_EN(port->slot) |
 218 +                      PCIE_CSR_ASPM_L1_EN(port->slot);
 219 +               writel(val, pcie->base + PCIE_SYS_CFG_V2);
 220 +       }
 221 +
 222 +       /* Assert all reset signals */
 223 +       writel(0, port->base + PCIE_RST_CTRL);
 224 +
 225 +       /*
 226 +        * Enable PCIe link down reset, if link status changed from link up to
 227 +        * link down, this will reset MAC control registers and configuration
 228 +        * space.
 229 +        */
 230 +       writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
 231 +
 232 +       /* De-assert PHY, PE, PIPE, MAC and configuration reset */
 233 +       val = readl(port->base + PCIE_RST_CTRL);
 234 +       val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
 235 +              PCIE_MAC_SRSTB | PCIE_CRSTB;
 236 +       writel(val, port->base + PCIE_RST_CTRL);
 237 +
 238 +       /* Set up vendor ID and class code */
 239 +       if (soc->need_fix_class_id) {
 240 +               val = PCI_VENDOR_ID_MEDIATEK;
 241 +               writew(val, port->base + PCIE_CONF_VEND_ID);
 242 +
 243 +               val = PCI_CLASS_BRIDGE_PCI;
 244 +               writew(val, port->base + PCIE_CONF_CLASS_ID);
 245 +       }
 246 +
 247 +       /* 100ms timeout value should be enough for Gen1/2 training */
 248 +       err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
 249 +                                !!(val & PCIE_PORT_LINKUP_V2), 20,
 250 +                                100 * USEC_PER_MSEC);
 251 +       if (err)
 252 +               return -ETIMEDOUT;
 253 +
 254 +       /* Set INTx mask */
 255 +       val = readl(port->base + PCIE_INT_MASK);
 256 +       val &= ~INTX_MASK;
 257 +       writel(val, port->base + PCIE_INT_MASK);
 258 +
 259 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 260 +               mtk_pcie_enable_msi(port);
 261 +
 262 +       /* Set AHB to PCIe translation windows */
 263 +       size = mem->end - mem->start;
 264 +       val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
 265 +       writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
 266 +
 267 +       val = upper_32_bits(mem->start);
 268 +       writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
 269 +
 270 +       /* Set PCIe to AXI translation memory space.*/
 271 +       val = fls(0xffffffff) | WIN_ENABLE;
 272 +       writel(val, port->base + PCIE_AXI_WINDOW0);
 273
 274         return 0;
 275  }
 276 @@ -903,49 +928,29 @@
 277
 278         /* sys_ck might be divided into the following parts in some chips */
 279         snprintf(name, sizeof(name), "ahb_ck%d", slot);
 280 -       port->ahb_ck = devm_clk_get(dev, name);
 281 -       if (IS_ERR(port->ahb_ck)) {
 282 -               if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
 283 -                       return -EPROBE_DEFER;
 284 -
 285 -               port->ahb_ck = NULL;
 286 -       }
 287 +       port->ahb_ck = devm_clk_get_optional(dev, name);
 288 +       if (IS_ERR(port->ahb_ck))
 289 +               return PTR_ERR(port->ahb_ck);
 290
 291         snprintf(name, sizeof(name), "axi_ck%d", slot);
 292 -       port->axi_ck = devm_clk_get(dev, name);
 293 -       if (IS_ERR(port->axi_ck)) {
 294 -               if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
 295 -                       return -EPROBE_DEFER;
 296 -
 297 -               port->axi_ck = NULL;
 298 -       }
 299 +       port->axi_ck = devm_clk_get_optional(dev, name);
 300 +       if (IS_ERR(port->axi_ck))
 301 +               return PTR_ERR(port->axi_ck);
 302
 303         snprintf(name, sizeof(name), "aux_ck%d", slot);
 304 -       port->aux_ck = devm_clk_get(dev, name);
 305 -       if (IS_ERR(port->aux_ck)) {
 306 -               if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
 307 -                       return -EPROBE_DEFER;
 308 -
 309 -               port->aux_ck = NULL;
 310 -       }
 311 +       port->aux_ck = devm_clk_get_optional(dev, name);
 312 +       if (IS_ERR(port->aux_ck))
 313 +               return PTR_ERR(port->aux_ck);
 314
 315         snprintf(name, sizeof(name), "obff_ck%d", slot);
 316 -       port->obff_ck = devm_clk_get(dev, name);
 317 -       if (IS_ERR(port->obff_ck)) {
 318 -               if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
 319 -                       return -EPROBE_DEFER;
 320 -
 321 -               port->obff_ck = NULL;
 322 -       }
 323 +       port->obff_ck = devm_clk_get_optional(dev, name);
 324 +       if (IS_ERR(port->obff_ck))
 325 +               return PTR_ERR(port->obff_ck);
 326
 327         snprintf(name, sizeof(name), "pipe_ck%d", slot);
 328 -       port->pipe_ck = devm_clk_get(dev, name);
 329 -       if (IS_ERR(port->pipe_ck)) {
 330 -               if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
 331 -                       return -EPROBE_DEFER;
 332 -
 333 -               port->pipe_ck = NULL;
 334 -       }
 335 +       port->pipe_ck = devm_clk_get_optional(dev, name);
 336 +       if (IS_ERR(port->pipe_ck))
 337 +               return PTR_ERR(port->pipe_ck);
 338
 339         snprintf(name, sizeof(name), "pcie-rst%d", slot);
 340         port->reset = devm_reset_control_get_optional_exclusive(dev, name);
 341 @@ -998,10 +1003,8 @@
 342                 pcie->free_ck = NULL;
 343         }
 344
 345 -       if (dev->pm_domain) {
 346 -               pm_runtime_enable(dev);
 347 -               pm_runtime_get_sync(dev);
 348 -       }
 349 +       pm_runtime_enable(dev);
 350 +       pm_runtime_get_sync(dev);
 351
 352         /* enable top level clock */
 353         err = clk_prepare_enable(pcie->free_ck);
 354 @@ -1013,10 +1016,8 @@
 355         return 0;
 356
 357  err_free_ck:
 358 -       if (dev->pm_domain) {
 359 -               pm_runtime_put_sync(dev);
 360 -               pm_runtime_disable(dev);
 361 -       }
 362 +       pm_runtime_put_sync(dev);
 363 +       pm_runtime_disable(dev);
 364
 365         return err;
 366  }
 367 @@ -1125,34 +1126,6 @@
 368         return 0;
 369  }
 370
 371 -static int mtk_pcie_register_host(struct pci_host_bridge *host)
 372 -{
 373 -       struct mtk_pcie *pcie = pci_host_bridge_priv(host);
 374 -       struct pci_bus *child;
 375 -       int err;
 376 -
 377 -       host->busnr = pcie->busn.start;
 378 -       host->dev.parent = pcie->dev;
 379 -       host->ops = pcie->soc->ops;
 380 -       host->map_irq = of_irq_parse_and_map_pci;
 381 -       host->swizzle_irq = pci_common_swizzle;
 382 -       host->sysdata = pcie;
 383 -
 384 -       err = pci_scan_root_bus_bridge(host);
 385 -       if (err < 0)
 386 -               return err;
 387 -
 388 -       pci_bus_size_bridges(host->bus);
 389 -       pci_bus_assign_resources(host->bus);
 390 -
 391 -       list_for_each_entry(child, &host->bus->children, node)
 392 -               pcie_bus_configure_settings(child);
 393 -
 394 -       pci_bus_add_devices(host->bus);
 395 -
 396 -       return 0;
 397 -}
 398 -
 399  static int mtk_pcie_probe(struct platform_device *pdev)
 400  {
 401         struct device *dev = &pdev->dev;
 402 @@ -1179,7 +1152,14 @@
 403         if (err)
 404                 goto put_resources;
 405
 406 -       err = mtk_pcie_register_host(host);
 407 +       host->busnr = pcie->busn.start;
 408 +       host->dev.parent = pcie->dev;
 409 +       host->ops = pcie->soc->ops;
 410 +       host->map_irq = of_irq_parse_and_map_pci;
 411 +       host->swizzle_irq = pci_common_swizzle;
 412 +       host->sysdata = pcie;
 413 +
 414 +       err = pci_host_probe(host);
 415         if (err)
 416                 goto put_resources;
 417
 418 @@ -1192,6 +1172,80 @@
 419         return err;
 420  }
 421
 422 +
 423 +static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
 424 +{
 425 +       struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
 426 +       struct list_head *windows = &host->windows;
 427 +
 428 +       pci_free_resource_list(windows);
 429 +}
 430 +
 431 +static int mtk_pcie_remove(struct platform_device *pdev)
 432 +{
 433 +       struct mtk_pcie *pcie = platform_get_drvdata(pdev);
 434 +       struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
 435 +
 436 +       pci_stop_root_bus(host->bus);
 437 +       pci_remove_root_bus(host->bus);
 438 +       mtk_pcie_free_resources(pcie);
 439 +
 440 +       mtk_pcie_irq_teardown(pcie);
 441 +
 442 +       mtk_pcie_put_resources(pcie);
 443 +
 444 +       return 0;
 445 +}
 446 +
 447 +static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
 448 +{
 449 +       struct mtk_pcie *pcie = dev_get_drvdata(dev);
 450 +       struct mtk_pcie_port *port;
 451 +
 452 +       if (list_empty(&pcie->ports))
 453 +               return 0;
 454 +
 455 +       list_for_each_entry(port, &pcie->ports, list) {
 456 +               clk_disable_unprepare(port->pipe_ck);
 457 +               clk_disable_unprepare(port->obff_ck);
 458 +               clk_disable_unprepare(port->axi_ck);
 459 +               clk_disable_unprepare(port->aux_ck);
 460 +               clk_disable_unprepare(port->ahb_ck);
 461 +               clk_disable_unprepare(port->sys_ck);
 462 +               phy_power_off(port->phy);
 463 +               phy_exit(port->phy);
 464 +       }
 465 +
 466 +       clk_disable_unprepare(pcie->free_ck);
 467 +
 468 +       return 0;
 469 +}
 470 +
 471 +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
 472 +{
 473 +       struct mtk_pcie *pcie = dev_get_drvdata(dev);
 474 +       struct mtk_pcie_port *port, *tmp;
 475 +
 476 +       if (list_empty(&pcie->ports))
 477 +               return 0;
 478 +
 479 +       clk_prepare_enable(pcie->free_ck);
 480 +
 481 +       list_for_each_entry_safe(port, tmp, &pcie->ports, list)
 482 +               mtk_pcie_enable_port(port);
 483 +
 484 +       /* In case of EP was removed while system suspend. */
 485 +       if (list_empty(&pcie->ports))
 486 +               clk_disable_unprepare(pcie->free_ck);
 487 +
 488 +       return 0;
 489 +}
 490 +
 491 +static const struct dev_pm_ops mtk_pcie_pm_ops = {
 492 +       SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
 493 +                                     mtk_pcie_resume_noirq)
 494 +};
 495 +
 496  static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
 497         .ops = &mtk_pcie_ops,
 498         .startup = mtk_pcie_startup_port,
 499 @@ -1220,10 +1274,13 @@
 500
 501  static struct platform_driver mtk_pcie_driver = {
 502         .probe = mtk_pcie_probe,
 503 +       .remove = mtk_pcie_remove,
 504         .driver = {
 505                 .name = "mtk-pcie",
 506                 .of_match_table = mtk_pcie_ids,
 507                 .suppress_bind_attrs = true,
 508 +               .pm = &mtk_pcie_pm_ops,
 509         },
 510  };
 511 -builtin_platform_driver(mtk_pcie_driver);
 512 +module_platform_driver(mtk_pcie_driver);
 513 +MODULE_LICENSE("GPL v2");
 514 diff -urN a/include/linux/clk.h b/include/linux/clk.h
 515 --- a/include/linux/clk.h       2019-08-29 16:59:52.335365591 +0800
 516 +++ b/include/linux/clk.h       2019-08-29 17:02:17.107725525 +0800
 517 @@ -349,6 +349,17 @@
 518  struct clk *devm_clk_get(struct device *dev, const char *id);
 519
 520  /**
 521 + * devm_clk_get_optional - lookup and obtain a managed reference to an optional
 522 + *                         clock producer.
 523 + * @dev: device for clock "consumer"
 524 + * @id: clock consumer ID
 525 + *
 526 + * Behaves the same as devm_clk_get() except where there is no clock producer.
 527 + * In this case, instead of returning -ENOENT, the function returns NULL.
 528 + */
 529 +struct clk *devm_clk_get_optional(struct device *dev, const char *id);
 530 +
 531 +/**
 532   * devm_get_clk_from_child - lookup and obtain a managed reference to a
 533   *                          clock producer from child node.
 534   * @dev: device for clock "consumer"