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[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
1 From 83ef9fb21a896ac03c3a78bc3ae0b21f3b0a43a3 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 12:16:17 +0100
4 Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
5
6 This adds basic chip support for Mediatek MT7623.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 arch/arm/boot/dts/Makefile | 1 +
11 arch/arm/boot/dts/mt7623-evb.dts | 474 +++++++++++++++++++++++++++++
12 arch/arm/boot/dts/mt7623.dtsi | 593 +++++++++++++++++++++++++++++++++++++
13 arch/arm/mach-mediatek/Kconfig | 4 +
14 arch/arm/mach-mediatek/mediatek.c | 1 +
15 5 files changed, 1073 insertions(+)
16 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
17 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
18
19 --- a/arch/arm/boot/dts/Makefile
20 +++ b/arch/arm/boot/dts/Makefile
21 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
22 mt6580-evbp1.dtb \
23 mt6589-aquaris5.dtb \
24 mt6592-evb.dtb \
25 + mt7623-evb.dtb \
26 mt8127-moose.dtb \
27 mt8135-evbp1.dtb
28 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
29 --- /dev/null
30 +++ b/arch/arm/boot/dts/mt7623-evb.dts
31 @@ -0,0 +1,474 @@
32 +/*
33 + * Copyright (c) 2016 MediaTek Inc.
34 + * Author: John Crispin <blogic@openwrt.org>
35 + *
36 + * This program is free software; you can redistribute it and/or modify
37 + * it under the terms of the GNU General Public License version 2 as
38 + * published by the Free Software Foundation.
39 + *
40 + * This program is distributed in the hope that it will be useful,
41 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 + * GNU General Public License for more details.
44 + */
45 +
46 +/dts-v1/;
47 +
48 +#include "mt7623.dtsi"
49 +#include <dt-bindings/gpio/gpio.h>
50 +
51 +/ {
52 + model = "MediaTek MT7623 evaluation board";
53 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
54 +
55 + chosen {
56 + stdout-path = &uart2;
57 + };
58 +
59 + memory {
60 + reg = <0 0x80000000 0 0x20000000>;
61 + };
62 +
63 + usb_p1_vbus: regulator@0 {
64 + compatible = "regulator-fixed";
65 + regulator-name = "usb_vbus";
66 + regulator-min-microvolt = <5000000>;
67 + regulator-max-microvolt = <5000000>;
68 + gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
69 + enable-active-high;
70 + };
71 +};
72 +
73 +&cpu0 {
74 + proc-supply = <&mt6323_vproc_reg>;
75 +};
76 +
77 +&cpu1 {
78 + proc-supply = <&mt6323_vproc_reg>;
79 +};
80 +
81 +&cpu2 {
82 + proc-supply = <&mt6323_vproc_reg>;
83 +};
84 +
85 +&cpu3 {
86 + proc-supply = <&mt6323_vproc_reg>;
87 +};
88 +
89 +&pwrap {
90 + pmic: mt6323 {
91 + compatible = "mediatek,mt6323";
92 + interrupt-parent = <&pio>;
93 + interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
94 + interrupt-controller;
95 + #interrupt-cells = <2>;
96 +
97 + mt6323regulator: mt6323regulator{
98 + compatible = "mediatek,mt6323-regulator";
99 +
100 + mt6323_vproc_reg: buck_vproc{
101 + regulator-name = "vproc";
102 + regulator-min-microvolt = < 700000>;
103 + regulator-max-microvolt = <1350000>;
104 + regulator-ramp-delay = <12500>;
105 + regulator-always-on;
106 + regulator-boot-on;
107 + };
108 +
109 + mt6323_vsys_reg: buck_vsys{
110 + regulator-name = "vsys";
111 + regulator-min-microvolt = <1400000>;
112 + regulator-max-microvolt = <2987500>;
113 + regulator-ramp-delay = <25000>;
114 + regulator-always-on;
115 + regulator-boot-on;
116 + };
117 +
118 + mt6323_vpa_reg: buck_vpa{
119 + regulator-name = "vpa";
120 + regulator-min-microvolt = < 500000>;
121 + regulator-max-microvolt = <3650000>;
122 + };
123 +
124 + mt6323_vtcxo_reg: ldo_vtcxo{
125 + regulator-name = "vtcxo";
126 + regulator-min-microvolt = <2800000>;
127 + regulator-max-microvolt = <2800000>;
128 + regulator-enable-ramp-delay = <90>;
129 + regulator-always-on;
130 + regulator-boot-on;
131 + };
132 +
133 + mt6323_vcn28_reg: ldo_vcn28{
134 + regulator-name = "vcn28";
135 + regulator-min-microvolt = <2800000>;
136 + regulator-max-microvolt = <2800000>;
137 + regulator-enable-ramp-delay = <185>;
138 + };
139 +
140 + mt6323_vcn33_bt_reg: ldo_vcn33_bt{
141 + regulator-name = "vcn33_bt";
142 + regulator-min-microvolt = <3300000>;
143 + regulator-max-microvolt = <3600000>;
144 + regulator-enable-ramp-delay = <185>;
145 + };
146 +
147 + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
148 + regulator-name = "vcn33_wifi";
149 + regulator-min-microvolt = <3300000>;
150 + regulator-max-microvolt = <3600000>;
151 + regulator-enable-ramp-delay = <185>;
152 + };
153 +
154 + mt6323_va_reg: ldo_va{
155 + regulator-name = "va";
156 + regulator-min-microvolt = <2800000>;
157 + regulator-max-microvolt = <2800000>;
158 + regulator-enable-ramp-delay = <216>;
159 + regulator-always-on;
160 + regulator-boot-on;
161 + };
162 +
163 + mt6323_vcama_reg: ldo_vcama{
164 + regulator-name = "vcama";
165 + regulator-min-microvolt = <1500000>;
166 + regulator-max-microvolt = <2800000>;
167 + regulator-enable-ramp-delay = <216>;
168 + };
169 +
170 + mt6323_vio28_reg: ldo_vio28{
171 + regulator-name = "vio28";
172 + regulator-min-microvolt = <2800000>;
173 + regulator-max-microvolt = <2800000>;
174 + regulator-enable-ramp-delay = <216>;
175 + regulator-always-on;
176 + regulator-boot-on;
177 + };
178 +
179 + mt6323_vusb_reg: ldo_vusb{
180 + regulator-name = "vusb";
181 + regulator-min-microvolt = <3300000>;
182 + regulator-max-microvolt = <3300000>;
183 + regulator-enable-ramp-delay = <216>;
184 + regulator-boot-on;
185 + };
186 +
187 + mt6323_vmc_reg: ldo_vmc{
188 + regulator-name = "vmc";
189 + regulator-min-microvolt = <1800000>;
190 + regulator-max-microvolt = <3300000>;
191 + regulator-enable-ramp-delay = <36>;
192 + regulator-boot-on;
193 + };
194 +
195 + mt6323_vmch_reg: ldo_vmch{
196 + regulator-name = "vmch";
197 + regulator-min-microvolt = <3000000>;
198 + regulator-max-microvolt = <3300000>;
199 + regulator-enable-ramp-delay = <36>;
200 + regulator-boot-on;
201 + };
202 +
203 + mt6323_vemc3v3_reg: ldo_vemc3v3{
204 + regulator-name = "vemc3v3";
205 + regulator-min-microvolt = <3000000>;
206 + regulator-max-microvolt = <3300000>;
207 + regulator-enable-ramp-delay = <36>;
208 + regulator-boot-on;
209 + };
210 +
211 + mt6323_vgp1_reg: ldo_vgp1{
212 + regulator-name = "vgp1";
213 + regulator-min-microvolt = <1200000>;
214 + regulator-max-microvolt = <3300000>;
215 + regulator-enable-ramp-delay = <216>;
216 + };
217 +
218 + mt6323_vgp2_reg: ldo_vgp2{
219 + regulator-name = "vgp2";
220 + regulator-min-microvolt = <1200000>;
221 + regulator-max-microvolt = <3000000>;
222 + regulator-enable-ramp-delay = <216>;
223 + };
224 +
225 + mt6323_vgp3_reg: ldo_vgp3{
226 + regulator-name = "vgp3";
227 + regulator-min-microvolt = <1200000>;
228 + regulator-max-microvolt = <1800000>;
229 + regulator-enable-ramp-delay = <216>;
230 + };
231 +
232 + mt6323_vcn18_reg: ldo_vcn18{
233 + regulator-name = "vcn18";
234 + regulator-min-microvolt = <1800000>;
235 + regulator-max-microvolt = <1800000>;
236 + regulator-enable-ramp-delay = <216>;
237 + };
238 +
239 + mt6323_vsim1_reg: ldo_vsim1{
240 + regulator-name = "vsim1";
241 + regulator-min-microvolt = <1800000>;
242 + regulator-max-microvolt = <3000000>;
243 + regulator-enable-ramp-delay = <216>;
244 + };
245 +
246 + mt6323_vsim2_reg: ldo_vsim2{
247 + regulator-name = "vsim2";
248 + regulator-min-microvolt = <1800000>;
249 + regulator-max-microvolt = <3000000>;
250 + regulator-enable-ramp-delay = <216>;
251 + };
252 +
253 + mt6323_vrtc_reg: ldo_vrtc{
254 + regulator-name = "vrtc";
255 + regulator-min-microvolt = <2800000>;
256 + regulator-max-microvolt = <2800000>;
257 + regulator-always-on;
258 + regulator-boot-on;
259 + };
260 +
261 + mt6323_vcamaf_reg: ldo_vcamaf{
262 + regulator-name = "vcamaf";
263 + regulator-min-microvolt = <1200000>;
264 + regulator-max-microvolt = <3300000>;
265 + regulator-enable-ramp-delay = <216>;
266 + };
267 +
268 + mt6323_vibr_reg: ldo_vibr{
269 + regulator-name = "vibr";
270 + regulator-min-microvolt = <1200000>;
271 + regulator-max-microvolt = <3300000>;
272 + regulator-enable-ramp-delay = <36>;
273 + };
274 +
275 + mt6323_vrf18_reg: ldo_vrf18{
276 + regulator-name = "vrf18";
277 + regulator-min-microvolt = <1825000>;
278 + regulator-max-microvolt = <1825000>;
279 + regulator-enable-ramp-delay = <187>;
280 + };
281 +
282 + mt6323_vm_reg: ldo_vm{
283 + regulator-name = "vm";
284 + regulator-min-microvolt = <1200000>;
285 + regulator-max-microvolt = <1800000>;
286 + regulator-enable-ramp-delay = <216>;
287 + regulator-always-on;
288 + regulator-boot-on;
289 + };
290 +
291 + mt6323_vio18_reg: ldo_vio18{
292 + regulator-name = "vio18";
293 + regulator-min-microvolt = <1800000>;
294 + regulator-max-microvolt = <1800000>;
295 + regulator-enable-ramp-delay = <216>;
296 + regulator-always-on;
297 + regulator-boot-on;
298 + };
299 +
300 + mt6323_vcamd_reg: ldo_vcamd{
301 + regulator-name = "vcamd";
302 + regulator-min-microvolt = <1200000>;
303 + regulator-max-microvolt = <1800000>;
304 + regulator-enable-ramp-delay = <216>;
305 + };
306 +
307 + mt6323_vcamio_reg: ldo_vcamio{
308 + regulator-name = "vcamio";
309 + regulator-min-microvolt = <1800000>;
310 + regulator-max-microvolt = <1800000>;
311 + regulator-enable-ramp-delay = <216>;
312 + };
313 + };
314 + };
315 +};
316 +
317 +&uart2 {
318 + status = "okay";
319 +};
320 +
321 +&mmc0 {
322 + status = "okay";
323 + pinctrl-names = "default", "state_uhs";
324 + pinctrl-0 = <&mmc0_pins_default>;
325 + pinctrl-1 = <&mmc0_pins_uhs>;
326 + bus-width = <8>;
327 + max-frequency = <50000000>;
328 + cap-mmc-highspeed;
329 + vmmc-supply = <&mt6323_vemc3v3_reg>;
330 + vqmmc-supply = <&mt6323_vio18_reg>;
331 + non-removable;
332 +};
333 +
334 +&mmc1 {
335 + status = "okay";
336 + pinctrl-names = "default", "state_uhs";
337 + pinctrl-0 = <&mmc1_pins_default>;
338 + pinctrl-1 = <&mmc1_pins_uhs>;
339 + bus-width = <4>;
340 + max-frequency = <50000000>;
341 + cap-sd-highspeed;
342 + sd-uhs-sdr25;
343 +// cd-gpios = <&pio 132 0>;
344 + vmmc-supply = <&mt6323_vmch_reg>;
345 + vqmmc-supply = <&mt6323_vmc_reg>;
346 +};
347 +
348 +&pio {
349 + mmc0_pins_default: mmc0default {
350 + pins_cmd_dat {
351 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
352 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
353 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
354 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
355 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
356 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
357 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
358 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
359 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
360 + input-enable;
361 + bias-pull-up;
362 + };
363 +
364 + pins_clk {
365 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
366 + bias-pull-down;
367 + };
368 +
369 + pins_rst {
370 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
371 + bias-pull-up;
372 + };
373 + };
374 +
375 + mmc0_pins_uhs: mmc0 {
376 + pins_cmd_dat {
377 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
378 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
379 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
380 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
381 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
382 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
383 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
384 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
385 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
386 + input-enable;
387 + drive-strength = <MTK_DRIVE_2mA>;
388 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
389 + };
390 +
391 + pins_clk {
392 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
393 + drive-strength = <MTK_DRIVE_2mA>;
394 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
395 + };
396 +
397 + pins_rst {
398 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
399 + bias-pull-up;
400 + };
401 + };
402 +
403 + mmc1_pins_default: mmc1default {
404 + pins_cmd_dat {
405 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
406 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
407 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
408 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
409 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
410 + input-enable;
411 + drive-strength = <MTK_DRIVE_4mA>;
412 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
413 + };
414 +
415 + pins_clk {
416 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
417 + bias-pull-down;
418 + drive-strength = <MTK_DRIVE_4mA>;
419 + };
420 +
421 +// pins_insert {
422 +// pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
423 +// bias-pull-up;
424 +// };
425 + };
426 +
427 + mmc1_pins_uhs: mmc1 {
428 + pins_cmd_dat {
429 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
430 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
431 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
432 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
433 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
434 + input-enable;
435 + drive-strength = <MTK_DRIVE_4mA>;
436 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
437 + };
438 +
439 + pins_clk {
440 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
441 + drive-strength = <MTK_DRIVE_4mA>;
442 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
443 + };
444 + };
445 +
446 + eth_default: eth {
447 + pins_eth {
448 + pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
449 + <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
450 + <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
451 + <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
452 + <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
453 + <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
454 + <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
455 + <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
456 + <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
457 + <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
458 + <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
459 + <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
460 + <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
461 + <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
462 + <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
463 + };
464 +
465 + pins_eth_rst {
466 + pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
467 + output-low;
468 + };
469 + };
470 +};
471 +
472 +&usb1 {
473 + vusb33-supply = <&mt6323_vusb_reg>;
474 + vbus-supply = <&usb_p1_vbus>;
475 + status = "okay";
476 +};
477 +
478 +&u3phy1 {
479 + status = "okay";
480 +};
481 +
482 +&pcie {
483 + status = "okay";
484 +};
485 +
486 +&eth {
487 + status = "okay";
488 +};
489 +
490 +&gmac1 {
491 + mac-address = [00 11 22 33 44 56];
492 + status = "okay";
493 +};
494 +
495 +&gmac2 {
496 + mac-address = [00 11 22 33 44 55];
497 + status = "okay";
498 +};
499 +
500 +&gsw {
501 + pinctrl-names = "default";
502 + pinctrl-0 = <&eth_default>;
503 + mediatek,reset-pin = <&pio 15 0>;
504 + status = "okay";
505 +};
506 --- /dev/null
507 +++ b/arch/arm/boot/dts/mt7623.dtsi
508 @@ -0,0 +1,593 @@
509 +/*
510 + * Copyright (c) 2016 MediaTek Inc.
511 + * Author: John Crispin <blogic@openwrt.org>
512 + *
513 + * This program is free software; you can redistribute it and/or modify
514 + * it under the terms of the GNU General Public License version 2 as
515 + * published by the Free Software Foundation.
516 + *
517 + * This program is distributed in the hope that it will be useful,
518 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
519 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
520 + * GNU General Public License for more details.
521 + */
522 +
523 +#include <dt-bindings/interrupt-controller/irq.h>
524 +#include <dt-bindings/interrupt-controller/arm-gic.h>
525 +#include <dt-bindings/clock/mt2701-clk.h>
526 +#include <dt-bindings/power/mt2701-power.h>
527 +#include <dt-bindings/phy/phy.h>
528 +#include <dt-bindings/reset-controller/mt2701-resets.h>
529 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
530 +#include "skeleton64.dtsi"
531 +
532 +
533 +/ {
534 + compatible = "mediatek,mt7623";
535 + interrupt-parent = <&sysirq>;
536 +
537 + cpus {
538 + #address-cells = <1>;
539 + #size-cells = <0>;
540 + enable-method = "mediatek,mt6589-smp";
541 +
542 + cpu0: cpu@0 {
543 + device_type = "cpu";
544 + compatible = "arm,cortex-a7";
545 + reg = <0x0>;
546 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
547 + <&apmixedsys CLK_APMIXED_MAINPLL>;
548 + clock-names = "cpu", "intermediate";
549 + operating-points = <
550 + 598000 1150000
551 + 747500 1150000
552 + 1040000 1150000
553 + 1196000 1200000
554 + 1300000 1300000
555 + >;
556 + };
557 + cpu1: cpu@1 {
558 + device_type = "cpu";
559 + compatible = "arm,cortex-a7";
560 + reg = <0x1>;
561 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
562 + <&apmixedsys CLK_APMIXED_MAINPLL>;
563 + clock-names = "cpu", "intermediate";
564 + operating-points = <
565 + 598000 1150000
566 + 747500 1150000
567 + 1040000 1150000
568 + 1196000 1200000
569 + 1300000 1300000
570 + >;
571 + };
572 + cpu2: cpu@2 {
573 + device_type = "cpu";
574 + compatible = "arm,cortex-a7";
575 + reg = <0x2>;
576 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
577 + <&apmixedsys CLK_APMIXED_MAINPLL>;
578 + clock-names = "cpu", "intermediate";
579 + operating-points = <
580 + 598000 1150000
581 + 747500 1150000
582 + 1040000 1150000
583 + 1196000 1200000
584 + 1300000 1300000
585 + >;
586 + };
587 + cpu3: cpu@3 {
588 + device_type = "cpu";
589 + compatible = "arm,cortex-a7";
590 + reg = <0x3>;
591 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
592 + <&apmixedsys CLK_APMIXED_MAINPLL>;
593 + clock-names = "cpu", "intermediate";
594 + operating-points = <
595 + 598000 1150000
596 + 747500 1150000
597 + 1040000 1150000
598 + 1196000 1200000
599 + 1300000 1300000
600 + >;
601 + };
602 + };
603 +
604 + system_clk: dummy13m {
605 + compatible = "fixed-clock";
606 + clock-frequency = <13000000>;
607 + #clock-cells = <0>;
608 + };
609 +
610 + rtc_clk: dummy32k {
611 + compatible = "fixed-clock";
612 + clock-frequency = <32000>;
613 + #clock-cells = <0>;
614 + clock-output-names = "clk32k";
615 + };
616 +
617 + clk26m: dummy26m {
618 + compatible = "fixed-clock";
619 + clock-frequency = <26000000>;
620 + #clock-cells = <0>;
621 + clock-output-names = "clk26m";
622 + };
623 +
624 + timer {
625 + compatible = "arm,armv7-timer";
626 + interrupt-parent = <&gic>;
627 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
628 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
629 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
630 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
631 + clock-frequency = <13000000>;
632 + arm,cpu-registers-not-fw-configured;
633 + };
634 +
635 + topckgen: power-controller@10000000 {
636 + compatible = "mediatek,mt7623-topckgen",
637 + "mediatek,mt2701-topckgen",
638 + "syscon";
639 + reg = <0 0x10000000 0 0x1000>;
640 + #clock-cells = <1>;
641 + };
642 +
643 + infracfg: power-controller@10001000 {
644 + compatible = "mediatek,mt7623-infracfg",
645 + "mediatek,mt2701-infracfg",
646 + "syscon";
647 + reg = <0 0x10001000 0 0x1000>;
648 + #clock-cells = <1>;
649 + #reset-cells = <1>;
650 + };
651 +
652 + pericfg: pericfg@10003000 {
653 + compatible = "mediatek,mt7623-pericfg",
654 + "mediatek,mt2701-pericfg",
655 + "syscon";
656 + reg = <0 0x10003000 0 0x1000>;
657 + #clock-cells = <1>;
658 + #reset-cells = <1>;
659 + };
660 +
661 + pio: pinctrl@10005000 {
662 + compatible = "mediatek,mt7623-pinctrl";
663 + reg = <0 0x1000b000 0 0x1000>;
664 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
665 + pins-are-numbered;
666 + gpio-controller;
667 + #gpio-cells = <2>;
668 + interrupt-controller;
669 + interrupt-parent = <&gic>;
670 + #interrupt-cells = <2>;
671 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
672 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
673 + };
674 +
675 + syscfg_pctl_a: syscfg@10005000 {
676 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
677 + reg = <0 0x10005000 0 0x1000>;
678 + };
679 +
680 + scpsys: scpsys@10006000 {
681 + #power-domain-cells = <1>;
682 + compatible = "mediatek,mt7623-scpsys",
683 + "mediatek,mt2701-scpsys";
684 + reg = <0 0x10006000 0 0x1000>;
685 + infracfg = <&infracfg>;
686 + clocks = <&clk26m>,
687 + <&topckgen CLK_TOP_MM_SEL>;
688 + clock-names = "mfg", "mm";
689 + };
690 +
691 + watchdog: watchdog@10007000 {
692 + compatible = "mediatek,mt7623-wdt",
693 + "mediatek,mt6589-wdt";
694 + reg = <0 0x10007000 0 0x100>;
695 + };
696 +
697 + timer: timer@10008000 {
698 + compatible = "mediatek,mt7623-timer",
699 + "mediatek,mt6577-timer";
700 + reg = <0 0x10008000 0 0x80>;
701 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
702 + clocks = <&system_clk>, <&rtc_clk>;
703 + clock-names = "system-clk", "rtc-clk";
704 + };
705 +
706 + pwrap: pwrap@1000d000 {
707 + compatible = "mediatek,mt7623-pwrap",
708 + "mediatek,mt2701-pwrap";
709 + reg = <0 0x1000d000 0 0x1000>;
710 + reg-names = "pwrap";
711 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
712 + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
713 + reset-names = "pwrap";
714 + clocks = <&infracfg CLK_INFRA_PMICSPI>,
715 + <&infracfg CLK_INFRA_PMICWRAP>;
716 + clock-names = "spi", "wrap";
717 + };
718 +
719 + sysirq: interrupt-controller@10200100 {
720 + compatible = "mediatek,mt7623-sysirq",
721 + "mediatek,mt6577-sysirq";
722 + interrupt-controller;
723 + #interrupt-cells = <3>;
724 + interrupt-parent = <&gic>;
725 + reg = <0 0x10200100 0 0x1c>;
726 + };
727 +
728 + apmixedsys: apmixedsys@10209000 {
729 + compatible = "mediatek,mt7623-apmixedsys",
730 + "mediatek,mt2701-apmixedsys";
731 + reg = <0 0x10209000 0 0x1000>;
732 + #clock-cells = <1>;
733 + };
734 +
735 + gic: interrupt-controller@10211000 {
736 + compatible = "arm,cortex-a7-gic";
737 + interrupt-controller;
738 + #interrupt-cells = <3>;
739 + interrupt-parent = <&gic>;
740 + reg = <0 0x10211000 0 0x1000>,
741 + <0 0x10212000 0 0x1000>,
742 + <0 0x10214000 0 0x2000>,
743 + <0 0x10216000 0 0x2000>;
744 + };
745 +
746 + i2c0: i2c@11007000 {
747 + compatible = "mediatek,mt7623-i2c",
748 + "mediatek,mt6577-i2c";
749 + reg = <0 0x11007000 0 0x70>,
750 + <0 0x11000200 0 0x80>;
751 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
752 + clock-div = <16>;
753 + clocks = <&pericfg CLK_PERI_I2C0>,
754 + <&pericfg CLK_PERI_AP_DMA>;
755 + clock-names = "main", "dma";
756 + #address-cells = <1>;
757 + #size-cells = <0>;
758 + status = "disabled";
759 + };
760 +
761 + i2c1: i2c@11008000 {
762 + compatible = "mediatek,mt7623-i2c",
763 + "mediatek,mt6577-i2c";
764 + reg = <0 0x11008000 0 0x70>,
765 + <0 0x11000280 0 0x80>;
766 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
767 + clock-div = <16>;
768 + clocks = <&pericfg CLK_PERI_I2C1>,
769 + <&pericfg CLK_PERI_AP_DMA>;
770 + clock-names = "main", "dma";
771 + #address-cells = <1>;
772 + #size-cells = <0>;
773 + status = "disabled";
774 + };
775 +
776 + i2c2: i2c@11009000 {
777 + compatible = "mediatek,mt7623-i2c",
778 + "mediatek,mt6577-i2c";
779 + reg = <0 0x11009000 0 0x70>,
780 + <0 0x11000300 0 0x80>;
781 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
782 + clock-div = <16>;
783 + clocks = <&pericfg CLK_PERI_I2C2>,
784 + <&pericfg CLK_PERI_AP_DMA>;
785 + clock-names = "main", "dma";
786 + #address-cells = <1>;
787 + #size-cells = <0>;
788 + status = "disabled";
789 + };
790 +
791 + uart0: serial@11002000 {
792 + compatible = "mediatek,mt7623-uart",
793 + "mediatek,mt6577-uart";
794 + reg = <0 0x11002000 0 0x400>;
795 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
796 + clocks = <&pericfg CLK_PERI_UART0_SEL>,
797 + <&pericfg CLK_PERI_UART0>;
798 + clock-names = "baud", "bus";
799 + status = "disabled";
800 + };
801 +
802 + uart1: serial@11003000 {
803 + compatible = "mediatek,mt7623-uart",
804 + "mediatek,mt6577-uart";
805 + reg = <0 0x11003000 0 0x400>;
806 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
807 + clocks = <&pericfg CLK_PERI_UART1_SEL>,
808 + <&pericfg CLK_PERI_UART1>;
809 + clock-names = "baud", "bus";
810 + status = "disabled";
811 + };
812 +
813 + uart2: serial@11004000 {
814 + compatible = "mediatek,mt7623-uart",
815 + "mediatek,mt6577-uart";
816 + reg = <0 0x11004000 0 0x400>;
817 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
818 + clocks = <&pericfg CLK_PERI_UART2_SEL>,
819 + <&pericfg CLK_PERI_UART2>;
820 + clock-names = "baud", "bus";
821 + status = "disabled";
822 + };
823 +
824 + uart3: serial@11005000 {
825 + compatible = "mediatek,mt7623-uart",
826 + "mediatek,mt6577-uart";
827 + reg = <0 0x11005000 0 0x400>;
828 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
829 + clocks = <&pericfg CLK_PERI_UART3_SEL>,
830 + <&pericfg CLK_PERI_UART3>;
831 + clock-names = "baud", "bus";
832 + status = "disabled";
833 + };
834 +
835 + spi: spi@1100a000 {
836 + compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
837 + reg = <0 0x1100a000 0 0x1000>;
838 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
839 + clocks = <&pericfg CLK_PERI_SPI0>;
840 + clock-names = "main";
841 +
842 + status = "disabled";
843 + };
844 +
845 + nandc: nfi@1100d000 {
846 + compatible = "mediatek,mt2701-nfc";
847 + reg = <0 0x1100d000 0 0x1000>;
848 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
849 + clocks = <&pericfg CLK_PERI_NFI>,
850 + <&pericfg CLK_PERI_NFI_PAD>;
851 + clock-names = "nfi_clk", "pad_clk";
852 + status = "disabled";
853 + ecc-engine = <&bch>;
854 + #address-cells = <1>;
855 + #size-cells = <0>;
856 + };
857 +
858 + bch: ecc@1100e000 {
859 + compatible = "mediatek,mt2701-ecc";
860 + reg = <0 0x1100e000 0 0x1000>;
861 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
862 + clocks = <&pericfg CLK_PERI_NFI_ECC>;
863 + clock-names = "nfiecc_clk";
864 + status = "disabled";
865 + };
866 +
867 + mmc0: mmc@11230000 {
868 + compatible = "mediatek,mt7623-mmc",
869 + "mediatek,mt8135-mmc";
870 + reg = <0 0x11230000 0 0x1000>;
871 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
872 + clocks = <&pericfg CLK_PERI_MSDC30_0>,
873 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
874 + clock-names = "source", "hclk";
875 + status = "disabled";
876 + };
877 +
878 + mmc1: mmc@11240000 {
879 + compatible = "mediatek,mt7623-mmc",
880 + "mediatek,mt8135-mmc";
881 + reg = <0 0x11240000 0 0x1000>;
882 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
883 + clocks = <&pericfg CLK_PERI_MSDC30_1>,
884 + <&topckgen CLK_TOP_MSDC30_1_SEL>;
885 + clock-names = "source", "hclk";
886 + status = "disabled";
887 + };
888 +
889 + usb1: usb@1a1c0000 {
890 + compatible = "mediatek,mt2701-xhci",
891 + "mediatek,mt8173-xhci";
892 + reg = <0 0x1a1c0000 0 0x1000>,
893 + <0 0x1a1c4700 0 0x0100>;
894 + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
895 + clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
896 + <&topckgen CLK_TOP_ETHIF_SEL>;
897 + clock-names = "sys_ck", "ethif";
898 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
899 + phys = <&phy_port0 PHY_TYPE_USB3>;
900 + status = "disabled";
901 + };
902 +
903 + u3phy1: usb-phy@1a1c4000 {
904 + compatible = "mediatek,mt2701-u3phy",
905 + "mediatek,mt8173-u3phy";
906 + reg = <0 0x1a1c4000 0 0x0700>;
907 + clocks = <&clk26m>;
908 + clock-names = "u3phya_ref";
909 + #phy-cells = <1>;
910 + #address-cells = <2>;
911 + #size-cells = <2>;
912 + ranges;
913 + status = "disabled";
914 +
915 + phy_port0: phy_port0: port@1a1c4800 {
916 + reg = <0 0x1a1c4800 0 0x800>;
917 + #phy-cells = <1>;
918 + status = "okay";
919 + };
920 + };
921 +
922 + usb2: usb@1a240000 {
923 + compatible = "mediatek,mt2701-xhci",
924 + "mediatek,mt8173-xhci";
925 + reg = <0 0x1a240000 0 0x1000>,
926 + <0 0x1a244700 0 0x0100>;
927 + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
928 + clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
929 + <&topckgen CLK_TOP_ETHIF_SEL>;
930 + clock-names = "sys_ck", "ethif";
931 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
932 + phys = <&u3phy2 0>;
933 + status = "disabled";
934 + };
935 +
936 + u3phy2: usb-phy@1a244000 {
937 + compatible = "mediatek,mt2701-u3phy",
938 + "mediatek,mt8173-u3phy";
939 + reg = <0 0x1a244000 0 0x0700>,
940 + <0 0x1a244800 0 0x0800>;
941 + clocks = <&clk26m>;
942 + clock-names = "u3phya_ref";
943 + #phy-cells = <1>;
944 + status = "disabled";
945 + };
946 +
947 + hifsys: clock-controller@1a000000 {
948 + compatible = "mediatek,mt7623-hifsys",
949 + "mediatek,mt2701-hifsys",
950 + "syscon";
951 + reg = <0 0x1a000000 0 0x1000>;
952 + #clock-cells = <1>;
953 + #reset-cells = <1>;
954 + };
955 +
956 + pcie: pcie@1a140000 {
957 + compatible = "mediatek,mt7623-pcie";
958 + device_type = "pci";
959 + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
960 + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
961 + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
962 + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
963 + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
964 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
965 + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
966 + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
967 + interrupt-names = "pcie0", "pcie1", "pcie2";
968 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
969 + clock-names = "pcie";
970 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
971 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
972 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
973 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
974 + reset-names = "pcie0", "pcie1", "pcie2";
975 +
976 + mediatek,hifsys = <&hifsys>;
977 +
978 + bus-range = <0x00 0xff>;
979 + #address-cells = <3>;
980 + #size-cells = <2>;
981 +
982 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
983 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
984 +
985 + status = "disabled";
986 +
987 + pcie@1,0 {
988 + device_type = "pci";
989 + reg = <0x0800 0 0 0 0>;
990 +
991 + #address-cells = <3>;
992 + #size-cells = <2>;
993 + ranges;
994 + };
995 +
996 + pcie@2,0{
997 + device_type = "pci";
998 + reg = <0x1000 0 0 0 0>;
999 +
1000 + #address-cells = <3>;
1001 + #size-cells = <2>;
1002 + ranges;
1003 + };
1004 +
1005 + pcie@3,0{
1006 + device_type = "pci";
1007 + reg = <0x1800 0 0 0 0>;
1008 +
1009 + #address-cells = <3>;
1010 + #size-cells = <2>;
1011 + ranges;
1012 + };
1013 + };
1014 +
1015 + ethsys: syscon@1b000000 {
1016 + compatible = "mediatek,mt2701-ethsys", "syscon";
1017 + reg = <0 0x1b000000 0 0x1000>;
1018 + #reset-cells = <1>;
1019 + #clock-cells = <1>;
1020 + };
1021 +
1022 + eth: ethernet@1b100000 {
1023 + compatible = "mediatek,mt7623-eth";
1024 + reg = <0 0x1b100000 0 0x20000>;
1025 +
1026 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1027 + <&ethsys CLK_ETHSYS_ESW>,
1028 + <&ethsys CLK_ETHSYS_GP2>,
1029 + <&ethsys CLK_ETHSYS_GP1>;
1030 + clock-names = "ethif", "esw", "gp2", "gp1";
1031 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
1032 + GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
1033 + GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1034 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1035 +
1036 + resets = <&ethsys 6>;
1037 + reset-names = "eth";
1038 +
1039 + mediatek,ethsys = <&ethsys>;
1040 + mediatek,pctl = <&syscfg_pctl_a>;
1041 +
1042 + mediatek,switch = <&gsw>;
1043 +
1044 + #address-cells = <1>;
1045 + #size-cells = <0>;
1046 +
1047 + status = "disabled";
1048 +
1049 + gmac1: mac@0 {
1050 + compatible = "mediatek,eth-mac";
1051 + reg = <0>;
1052 +
1053 + status = "disabled";
1054 +
1055 + phy-mode = "rgmii";
1056 +
1057 + fixed-link {
1058 + speed = <1000>;
1059 + full-duplex;
1060 + pause;
1061 + };
1062 + };
1063 +
1064 + gmac2: mac@1 {
1065 + compatible = "mediatek,eth-mac";
1066 + reg = <1>;
1067 +
1068 + phy-handle = <&phy5>;
1069 + status = "disabled";
1070 + };
1071 +
1072 + mdio-bus {
1073 + #address-cells = <1>;
1074 + #size-cells = <0>;
1075 +
1076 + phy5: ethernet-phy@5 {
1077 + reg = <5>;
1078 + phy-mode = "rgmii-rxid";
1079 + };
1080 +
1081 + phy1f: ethernet-phy@1f {
1082 + reg = <0x1f>;
1083 + phy-mode = "rgmii";
1084 + };
1085 + };
1086 + };
1087 +
1088 + gsw: switch@1b100000 {
1089 + compatible = "mediatek,mt7623-gsw";
1090 + interrupt-parent = <&pio>;
1091 + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
1092 + resets = <&ethsys 2>;
1093 + reset-names = "eth";
1094 + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
1095 + clock-names = "trgpll";
1096 + mt7530-supply = <&mt6323_vpa_reg>;
1097 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
1098 + mediatek,ethsys = <&ethsys>;
1099 + status = "disabled";
1100 + };
1101 +};
1102 --- a/arch/arm/mach-mediatek/Kconfig
1103 +++ b/arch/arm/mach-mediatek/Kconfig
1104 @@ -21,6 +21,10 @@ config MACH_MT6592
1105 bool "MediaTek MT6592 SoCs support"
1106 default ARCH_MEDIATEK
1107
1108 +config MACH_MT7623
1109 + bool "MediaTek MT7623 SoCs support"
1110 + default ARCH_MEDIATEK
1111 +
1112 config MACH_MT8127
1113 bool "MediaTek MT8127 SoCs support"
1114 default ARCH_MEDIATEK
1115 --- a/arch/arm/mach-mediatek/mediatek.c
1116 +++ b/arch/arm/mach-mediatek/mediatek.c
1117 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
1118 static const char * const mediatek_board_dt_compat[] = {
1119 "mediatek,mt6589",
1120 "mediatek,mt6592",
1121 + "mediatek,mt7623",
1122 "mediatek,mt8127",
1123 "mediatek,mt8135",
1124 NULL,
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