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[openwrt/openwrt.git] / target / linux / mediatek / patches-5.15 / 730-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
1 From a6f143af419bfc3f52d82e88ac033d9833e720af Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Mon, 13 Feb 2023 02:33:14 +0000
4 Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
5
6 Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
7 PHYs which require calibration data from the SoC's efuse.
8 Add support for these PHYs to the mediatek-ge driver if built for
9 MediaTek's ARM64 SoCs.
10
11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
12 ---
13 MAINTAINERS | 8 +
14 drivers/net/phy/Kconfig | 12 +
15 drivers/net/phy/mediatek-ge.c | 1351 +++++++++++++++++++++++++++++++++
16 3 files changed, 1371 insertions(+)
17
18 --- a/MAINTAINERS
19 +++ b/MAINTAINERS
20 @@ -11797,6 +11797,14 @@ S: Maintained
21 F: drivers/net/pcs/pcs-mtk-lynxi.c
22 F: include/linux/pcs/pcs-mtk-lynxi.h
23
24 +MEDIATEK ETHERNET PHY DRIVERS
25 +M: Daniel Golle <daniel@makrotopia.org>
26 +M: Qingfang Deng <dqfext@gmail.com>
27 +M: SkyLake Huang <SkyLake.Huang@mediatek.com>
28 +L: netdev@vger.kernel.org
29 +S: Maintained
30 +F: drivers/net/phy/mediatek-ge.c
31 +
32 MEDIATEK I2C CONTROLLER DRIVER
33 M: Qii Wang <qii.wang@mediatek.com>
34 L: linux-i2c@vger.kernel.org
35 --- a/drivers/net/phy/Kconfig
36 +++ b/drivers/net/phy/Kconfig
37 @@ -292,6 +292,18 @@ config MEDIATEK_GE_PHY
38 help
39 Supports the MediaTek Gigabit Ethernet PHYs.
40
41 +config MEDIATEK_GE_PHY_SOC
42 + bool "MediaTek SoC Ethernet PHYs"
43 + depends on (ARM64 && ARCH_MEDIATEK && MEDIATEK_GE_PHY) || COMPILE_TEST
44 + select NVMEM_MTK_EFUSE
45 + help
46 + Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
47 +
48 + Include support for built-in Ethernet PHYs which are present in
49 + the MT7981 and MT7988 SoCs. These PHYs need calibration data
50 + present in the SoCs efuse and will dynamically calibrate VCM
51 + (common-mode voltage) during startup.
52 +
53 config MICREL_PHY
54 tristate "Micrel PHYs"
55 help
56 --- a/drivers/net/phy/mediatek-ge.c
57 +++ b/drivers/net/phy/mediatek-ge.c
58 @@ -1,6 +1,9 @@
59 // SPDX-License-Identifier: GPL-2.0+
60 #include <linux/bitfield.h>
61 #include <linux/module.h>
62 +#include <linux/nvmem-consumer.h>
63 +#include <linux/of_address.h>
64 +#include <linux/of_platform.h>
65 #include <linux/phy.h>
66
67 #define MTK_EXT_PAGE_ACCESS 0x1f
68 @@ -11,6 +14,275 @@
69 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
70 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
71
72 +#define ANALOG_INTERNAL_OPERATION_MAX_US (20)
73 +#define ZCAL_CTRL_MIN (0)
74 +#define ZCAL_CTRL_MAX (63)
75 +#define TXRESERVE_MIN (0)
76 +#define TXRESERVE_MAX (7)
77 +
78 +#define MTK_PHY_ANARG_RG (0x10)
79 +#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
80 +
81 +/* Registers on MDIO_MMD_VEND1 */
82 +enum {
83 + MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TO1 = 0,
84 + MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1,
85 + MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1,
86 + MTK_PHY_MIDDLE_LEVEL_SHAPPER_1TO0,
87 + MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0,
88 + MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0,
89 + MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TON1, /* N means negative */
90 + MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1,
91 + MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1,
92 + MTK_PHY_MIDDLE_LEVEL_SHAPPER_N1TO0,
93 + MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0,
94 + MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0,
95 + MTK_PHY_TX_MLT3_END,
96 +};
97 +
98 +#define MTK_PHY_TXVLD_DA_RG (0x12)
99 +#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
100 +#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
101 +
102 +#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16)
103 +#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
104 +#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
105 +
106 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17)
107 +#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
108 +#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
109 +
110 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18)
111 +#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
112 +#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
113 +
114 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19)
115 +#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
116 +#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
117 +
118 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20)
119 +#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
120 +#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
121 +
122 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21)
123 +#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
124 +#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
125 +
126 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22)
127 +#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
128 +#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
129 +
130 +#define MTK_PHY_TANA_CAL_MODE (0xc1)
131 +#define MTK_PHY_TANA_CAL_MODE_SHIFT (8)
132 +
133 +#define MTK_PHY_RXADC_CTRL_RG7 (0xc6)
134 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
135 +
136 +#define MTK_PHY_RXADC_CTRL_RG9 (0xc8)
137 +#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
138 +#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
139 +#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
140 +#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
141 +
142 +#define MTK_PHY_LDO_OUTPUT_V (0xd7)
143 +
144 +#define MTK_PHY_RG_ANA_CAL_RG0 (0xdb)
145 +#define MTK_PHY_RG_CAL_CKINV BIT(12)
146 +#define MTK_PHY_RG_ANA_CALEN BIT(8)
147 +#define MTK_PHY_RG_REXT_CALEN BIT(4)
148 +#define MTK_PHY_RG_ZCALEN_A BIT(0)
149 +
150 +#define MTK_PHY_RG_ANA_CAL_RG1 (0xdc)
151 +#define MTK_PHY_RG_ZCALEN_B BIT(12)
152 +#define MTK_PHY_RG_ZCALEN_C BIT(8)
153 +#define MTK_PHY_RG_ZCALEN_D BIT(4)
154 +#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
155 +
156 +#define MTK_PHY_RG_ANA_CAL_RG2 (0xdd)
157 +#define MTK_PHY_RG_TXG_CALEN_A BIT(12)
158 +#define MTK_PHY_RG_TXG_CALEN_B BIT(8)
159 +#define MTK_PHY_RG_TXG_CALEN_C BIT(4)
160 +#define MTK_PHY_RG_TXG_CALEN_D BIT(0)
161 +
162 +#define MTK_PHY_RG_ANA_CAL_RG5 (0xe0)
163 +#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
164 +#define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0)
165 +
166 +#define MTK_PHY_RG_TX_FILTER (0xfe)
167 +
168 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B (0x172)
169 +#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
170 +#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
171 +
172 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D (0x173)
173 +#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
174 +#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
175 +
176 +#define MTK_PHY_RG_AD_CAL_COMP (0x17a)
177 +#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
178 +
179 +#define MTK_PHY_RG_AD_CAL_CLK (0x17b)
180 +#define MTK_PHY_DA_CAL_CLK BIT(0)
181 +
182 +#define MTK_PHY_RG_AD_CALIN (0x17c)
183 +#define MTK_PHY_DA_CALIN_FLAG BIT(0)
184 +
185 +#define MTK_PHY_RG_DASN_DAC_IN0_A (0x17d)
186 +#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
187 +
188 +#define MTK_PHY_RG_DASN_DAC_IN0_B (0x17e)
189 +#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
190 +
191 +#define MTK_PHY_RG_DASN_DAC_IN0_C (0x17f)
192 +#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
193 +
194 +#define MTK_PHY_RG_DASN_DAC_IN0_D (0x180)
195 +#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
196 +
197 +#define MTK_PHY_RG_DASN_DAC_IN1_A (0x181)
198 +#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
199 +
200 +#define MTK_PHY_RG_DASN_DAC_IN1_B (0x182)
201 +#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
202 +
203 +#define MTK_PHY_RG_DASN_DAC_IN1_C (0x183)
204 +#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
205 +
206 +#define MTK_PHY_RG_DASN_DAC_IN1_D (0x180)
207 +#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
208 +
209 +#define MTK_PHY_RG_LP_IIR2_K1_L (0x22a)
210 +#define MTK_PHY_RG_LP_IIR2_K1_U (0x22b)
211 +#define MTK_PHY_RG_LP_IIR2_K2_L (0x22c)
212 +#define MTK_PHY_RG_LP_IIR2_K2_U (0x22d)
213 +#define MTK_PHY_RG_LP_IIR2_K3_L (0x22e)
214 +#define MTK_PHY_RG_LP_IIR2_K3_U (0x22f)
215 +#define MTK_PHY_RG_LP_IIR2_K4_L (0x230)
216 +#define MTK_PHY_RG_LP_IIR2_K4_U (0x231)
217 +#define MTK_PHY_RG_LP_IIR2_K5_L (0x232)
218 +#define MTK_PHY_RG_LP_IIR2_K5_U (0x233)
219 +
220 +#define MTK_PHY_RG_DEV1E_REG234 (0x234)
221 +#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
222 +#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
223 +
224 +#define MTK_PHY_RG_LPF_CNT_VAL (0x235)
225 +
226 +#define MTK_PHY_RG_DEV1E_REG27C (0x27c)
227 +#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
228 +#define MTK_PHY_RG_DEV1E_REG27D (0x27d)
229 +#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
230 +
231 +#define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502)
232 +#define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503)
233 +
234 +#define MTK_PHY_DA_TX_R50_PAIR_A (0x53d)
235 +#define MTK_PHY_DA_TX_R50_PAIR_B (0x53e)
236 +#define MTK_PHY_DA_TX_R50_PAIR_C (0x53f)
237 +#define MTK_PHY_DA_TX_R50_PAIR_D (0x540)
238 +
239 +/* Registers on MDIO_MMD_VEND2 */
240 +#define MTK_PHY_LED0_ON_CTRL (0x24)
241 +#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0)
242 +#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
243 +#define MTK_PHY_LED0_ON_LINK100 BIT(1)
244 +#define MTK_PHY_LED0_ON_LINK10 BIT(2)
245 +#define MTK_PHY_LED0_ON_LINKDOWN BIT(3)
246 +#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */
247 +#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */
248 +#define MTK_PHY_LED0_FORCE_ON BIT(6)
249 +#define MTK_PHY_LED0_POLARITY BIT(14)
250 +#define MTK_PHY_LED0_ENABLE BIT(15)
251 +
252 +#define MTK_PHY_LED0_BLINK_CTRL (0x25)
253 +#define MTK_PHY_LED0_1000TX BIT(0)
254 +#define MTK_PHY_LED0_1000RX BIT(1)
255 +#define MTK_PHY_LED0_100TX BIT(2)
256 +#define MTK_PHY_LED0_100RX BIT(3)
257 +#define MTK_PHY_LED0_10TX BIT(4)
258 +#define MTK_PHY_LED0_10RX BIT(5)
259 +#define MTK_PHY_LED0_COLLISION BIT(6)
260 +#define MTK_PHY_LED0_RX_CRC_ERR BIT(7)
261 +#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8)
262 +#define MTK_PHY_LED0_FORCE_BLINK BIT(9)
263 +
264 +#define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100)
265 +#define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8)
266 +
267 +#define MTK_PHY_RG_DASN_TXT_DMY2 (0x110)
268 +#define MTK_PHY_TST_DMY2_MASK GENMASK(5, 0)
269 +
270 +#define MTK_PHY_RG_BG_RASEL (0x115)
271 +#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
272 +
273 +/* These macro privides efuse parsing for internal phy. */
274 +#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
275 +#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
276 +#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
277 +#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
278 +#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
279 +
280 +#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
281 +#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
282 +#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
283 +#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
284 +#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
285 +
286 +#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
287 +#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
288 +#define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0))
289 +#define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0))
290 +
291 +#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
292 +#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
293 +
294 +enum {
295 + NO_PAIR,
296 + PAIR_A,
297 + PAIR_B,
298 + PAIR_C,
299 + PAIR_D,
300 +};
301 +
302 +enum {
303 + GPHY_PORT0,
304 + GPHY_PORT1,
305 + GPHY_PORT2,
306 + GPHY_PORT3,
307 +};
308 +
309 +enum calibration_mode {
310 + EFUSE_K,
311 + SW_K
312 +};
313 +
314 +enum CAL_ITEM {
315 + REXT,
316 + TX_OFFSET,
317 + TX_AMP,
318 + TX_R50,
319 + TX_VCM
320 +};
321 +
322 +enum CAL_MODE {
323 + SW_EFUSE_M,
324 + EFUSE_M,
325 + SW_M
326 +};
327 +
328 +const u8 mt798x_zcal_to_r50[64] = {
329 + 7, 8, 9, 9, 10, 10, 11, 11,
330 + 12, 13, 13, 14, 14, 15, 16, 16,
331 + 17, 18, 18, 19, 20, 21, 21, 22,
332 + 23, 24, 24, 25, 26, 27, 28, 29,
333 + 30, 31, 32, 33, 34, 35, 36, 37,
334 + 38, 40, 41, 42, 43, 45, 46, 48,
335 + 49, 51, 52, 54, 55, 57, 59, 61,
336 + 62, 63, 63, 63, 63, 63, 63, 63
337 +};
338 +
339 +const char pair[4] = {'A', 'B', 'C', 'D'};
340 +
341 static int mtk_gephy_read_page(struct phy_device *phydev)
342 {
343 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
344 @@ -68,6 +340,1059 @@ static int mt7531_phy_config_init(struct
345 return 0;
346 }
347
348 +#ifdef CONFIG_MEDIATEK_GE_PHY_SOC
349 +/* One calibration cycle consists of:
350 + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
351 + * until AD_CAL_COMP is ready to output calibration result.
352 + * 2.Wait until DA_CAL_CLK is available.
353 + * 3.Fetch AD_CAL_COMP_OUT.
354 + */
355 +static int cal_cycle(struct phy_device *phydev, int devad,
356 + u32 regnum, u16 mask, u16 cal_val)
357 +{
358 + unsigned long timeout;
359 + int reg_val;
360 + int ret;
361 +
362 + phy_modify_mmd(phydev, devad, regnum,
363 + mask, cal_val);
364 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
365 + MTK_PHY_DA_CALIN_FLAG);
366 +
367 + timeout = jiffies + usecs_to_jiffies(ANALOG_INTERNAL_OPERATION_MAX_US);
368 + do {
369 + reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
370 + MTK_PHY_RG_AD_CAL_CLK);
371 + } while (time_before(jiffies, timeout) && !(reg_val & BIT(0)));
372 +
373 + if (!(reg_val & BIT(0))) {
374 + dev_err(&phydev->mdio.dev, "Calibration cycle timeout\n");
375 + return -ETIMEDOUT;
376 + }
377 +
378 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
379 + MTK_PHY_DA_CALIN_FLAG);
380 + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
381 + MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
382 + dev_dbg(&phydev->mdio.dev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
383 +
384 + return ret;
385 +}
386 +
387 +static int rext_fill_result(struct phy_device *phydev, u16 *buf)
388 +{
389 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
390 + MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
391 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
392 + MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
393 +
394 + return 0;
395 +}
396 +
397 +static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
398 +{
399 + u16 rext_cal_val[2];
400 +
401 + rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
402 + rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
403 + rext_fill_result(phydev, rext_cal_val);
404 +
405 + return 0;
406 +}
407 +
408 +static int rext_cal_sw(struct phy_device *phydev)
409 +{
410 + u8 rg_zcal_ctrl_def;
411 + u8 zcal_lower, zcal_upper, rg_zcal_ctrl;
412 + u8 lower_ret, upper_ret;
413 + u16 rext_cal_val[2];
414 + int ret;
415 +
416 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
417 + MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8);
418 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
419 + MTK_PHY_RG_TXVOS_CALEN);
420 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
421 + MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN |
422 + MTK_PHY_RG_REXT_CALEN);
423 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2,
424 + MTK_PHY_TST_DMY2_MASK, 0x1);
425 +
426 + rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1,
427 + MTK_PHY_RG_ANA_CAL_RG5) &
428 + MTK_PHY_RG_ZCAL_CTRL_MASK;
429 + zcal_lower = ZCAL_CTRL_MIN;
430 + zcal_upper = ZCAL_CTRL_MAX;
431 +
432 + dev_dbg(&phydev->mdio.dev, "Start REXT SW cal.\n");
433 + while ((zcal_upper - zcal_lower) > 1) {
434 + rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower + zcal_upper, 2);
435 + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
436 + MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl);
437 + if (ret == 1) {
438 + zcal_upper = rg_zcal_ctrl;
439 + upper_ret = ret;
440 + } else if (ret == 0) {
441 + zcal_lower = rg_zcal_ctrl;
442 + lower_ret = ret;
443 + } else {
444 + goto restore;
445 + }
446 + }
447 +
448 + if (zcal_lower == ZCAL_CTRL_MIN) {
449 + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
450 + MTK_PHY_RG_ANA_CAL_RG5,
451 + MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower);
452 + ret = lower_ret;
453 + } else if (zcal_upper == ZCAL_CTRL_MAX) {
454 + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
455 + MTK_PHY_RG_ANA_CAL_RG5,
456 + MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper);
457 + ret = upper_ret;
458 + }
459 + if (ret < 0)
460 + goto restore;
461 +
462 + ret = upper_ret - lower_ret;
463 + if (ret == 1) {
464 + rext_cal_val[0] = zcal_upper;
465 + rext_cal_val[1] = zcal_upper >> 3;
466 + rext_fill_result(phydev, rext_cal_val);
467 + dev_info(&phydev->mdio.dev, "REXT SW cal result: 0x%x\n",
468 + zcal_upper);
469 + ret = 0;
470 + } else {
471 + ret = -EINVAL;
472 + }
473 +
474 +restore:
475 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
476 + MTK_PHY_ANA_TEST_BUS_CTRL_RG,
477 + MTK_PHY_ANA_TEST_MODE_MASK);
478 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
479 + MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN |
480 + MTK_PHY_RG_REXT_CALEN);
481 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2,
482 + MTK_PHY_TST_DMY2_MASK);
483 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
484 + MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def);
485 +
486 + return ret;
487 +}
488 +
489 +static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
490 +{
491 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
492 + MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
493 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
494 + MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
495 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
496 + MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
497 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
498 + MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
499 +
500 + return 0;
501 +}
502 +
503 +static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
504 +{
505 + u16 tx_offset_cal_val[4];
506 +
507 + tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
508 + tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
509 + tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
510 + tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
511 +
512 + tx_offset_fill_result(phydev, tx_offset_cal_val);
513 +
514 + return 0;
515 +}
516 +
517 +static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
518 +{
519 + int i;
520 + int bias[16] = {0};
521 + const int vals_9461[16] = { 7, 1, 4, 7,
522 + 7, 1, 4, 7,
523 + 7, 1, 4, 7,
524 + 7, 1, 4, 7 };
525 + const int vals_9481[16] = { 10, 6, 6, 10,
526 + 10, 6, 6, 10,
527 + 10, 6, 6, 10,
528 + 10, 6, 6, 10 };
529 +
530 + switch (phydev->drv->phy_id) {
531 + case 0x03a29461:
532 + /* We add some calibration to efuse values
533 + * due to board level influence.
534 + * GBE: +7, TBT: +1, HBT: +4, TST: +7
535 + */
536 + memcpy(bias, (const void *)vals_9461, sizeof(bias));
537 + for (i = 0; i <= 12; i += 4) {
538 + if (likely(buf[i >> 2] + bias[i] >= 32)) {
539 + bias[i] -= 13;
540 + } else {
541 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
542 + 0x5c, 0x7 << i, bias[i] << i);
543 + bias[i + 1] += 13;
544 + bias[i + 2] += 13;
545 + bias[i + 3] += 13;
546 + }
547 + }
548 + break;
549 + case 0x03a29481:
550 + memcpy(bias, (const void *)vals_9481, sizeof(bias));
551 + break;
552 + default:
553 + break;
554 + }
555 +
556 + /* Prevent overflow */
557 + for (i = 0; i < 12; i++) {
558 + if (buf[i >> 2] + bias[i] > 63) {
559 + buf[i >> 2] = 63;
560 + bias[i] = 0;
561 + } else if (buf[i >> 2] + bias[i] < 0) {
562 + /* Bias caused by board design may change in the future.
563 + * So check negative cases, too.
564 + */
565 + buf[i >> 2] = 0;
566 + bias[i] = 0;
567 + }
568 + }
569 +
570 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
571 + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
572 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
573 + MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
574 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
575 + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
576 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
577 + MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
578 +
579 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
580 + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
581 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
582 + MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
583 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
584 + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
585 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
586 + MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
587 +
588 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
589 + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
590 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
591 + MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
592 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
593 + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
594 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
595 + MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
596 +
597 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
598 + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
599 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
600 + MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
601 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
602 + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
603 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
604 + MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
605 +
606 + return 0;
607 +}
608 +
609 +static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
610 +{
611 + u16 tx_amp_cal_val[4];
612 +
613 + tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
614 + tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
615 + tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
616 + tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
617 + tx_amp_fill_result(phydev, tx_amp_cal_val);
618 +
619 + return 0;
620 +}
621 +
622 +static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
623 + u8 txg_calen_x)
624 +{
625 + int bias = 0;
626 + u16 reg, val;
627 +
628 + switch (phydev->drv->phy_id) {
629 + case 0x03a29481:
630 + {
631 + bias = -2;
632 + break;
633 + }
634 + /* 0x03a29461 enters default case */
635 + default:
636 + break;
637 + }
638 +
639 + val = clamp_val(bias + tx_r50_cal_val, 0, 63);
640 +
641 + switch (txg_calen_x) {
642 + case PAIR_A:
643 + reg = MTK_PHY_DA_TX_R50_PAIR_A;
644 + break;
645 + case PAIR_B:
646 + reg = MTK_PHY_DA_TX_R50_PAIR_B;
647 + break;
648 + case PAIR_C:
649 + reg = MTK_PHY_DA_TX_R50_PAIR_C;
650 + break;
651 + case PAIR_D:
652 + reg = MTK_PHY_DA_TX_R50_PAIR_D;
653 + break;
654 + }
655 +
656 + phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
657 +
658 + return 0;
659 +}
660 +
661 +static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
662 + u8 txg_calen_x)
663 +{
664 + u16 tx_r50_cal_val;
665 +
666 + switch (txg_calen_x) {
667 + case PAIR_A:
668 + tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
669 + break;
670 + case PAIR_B:
671 + tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
672 + break;
673 + case PAIR_C:
674 + tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
675 + break;
676 + case PAIR_D:
677 + tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
678 + break;
679 + }
680 + tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
681 +
682 + return 0;
683 +}
684 +
685 +static int tx_r50_cal_sw(struct phy_device *phydev, u8 txg_calen_x)
686 +{
687 + u8 zcal_lower, zcal_upper, rg_zcal_ctrl;
688 + u8 lower_ret, upper_ret;
689 + u8 rg_zcal_ctrl_def;
690 + u16 tx_r50_cal_val;
691 + int ret;
692 +
693 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
694 + MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8);
695 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
696 + MTK_PHY_RG_TXVOS_CALEN);
697 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
698 + MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
699 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2,
700 + BIT(txg_calen_x * 4));
701 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2,
702 + MTK_PHY_TST_DMY2_MASK, 0x1);
703 +
704 + rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1,
705 + MTK_PHY_RG_ANA_CAL_RG5) &
706 + MTK_PHY_RG_ZCAL_CTRL_MASK;
707 + zcal_lower = ZCAL_CTRL_MIN;
708 + zcal_upper = ZCAL_CTRL_MAX;
709 +
710 + dev_dbg(&phydev->mdio.dev, "Start TX-R50 Pair%c SW cal.\n",
711 + pair[txg_calen_x]);
712 + while ((zcal_upper - zcal_lower) > 1) {
713 + rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower + zcal_upper, 2);
714 + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
715 + MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl);
716 + if (ret == 1) {
717 + zcal_upper = rg_zcal_ctrl;
718 + upper_ret = ret;
719 + } else if (ret == 0) {
720 + zcal_lower = rg_zcal_ctrl;
721 + lower_ret = ret;
722 + } else {
723 + goto restore;
724 + }
725 + }
726 +
727 + if (zcal_lower == ZCAL_CTRL_MIN) {
728 + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
729 + MTK_PHY_RG_ANA_CAL_RG5,
730 + MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower);
731 + ret = lower_ret;
732 + } else if (zcal_upper == ZCAL_CTRL_MAX) {
733 + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
734 + MTK_PHY_RG_ANA_CAL_RG5,
735 + MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper);
736 + ret = upper_ret;
737 + }
738 + if (ret < 0)
739 + goto restore;
740 +
741 + ret = upper_ret - lower_ret;
742 + if (ret == 1) {
743 + tx_r50_cal_val = mt798x_zcal_to_r50[zcal_upper];
744 + tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
745 + dev_info(&phydev->mdio.dev,
746 + "TX-R50 Pair%c SW cal result: 0x%x\n",
747 + pair[txg_calen_x], zcal_lower);
748 + ret = 0;
749 + } else {
750 + ret = -EINVAL;
751 + }
752 +
753 +restore:
754 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
755 + MTK_PHY_ANA_TEST_MODE_MASK);
756 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
757 + MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
758 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2,
759 + BIT(txg_calen_x * 4));
760 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2,
761 + MTK_PHY_TST_DMY2_MASK);
762 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
763 + MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def);
764 +
765 + return ret;
766 +}
767 +
768 +static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
769 +{
770 + u8 lower_idx, upper_idx, txreserve_val;
771 + u8 lower_ret, upper_ret;
772 + int ret;
773 +
774 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
775 + MTK_PHY_RG_ANA_CALEN);
776 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
777 + MTK_PHY_RG_CAL_CKINV);
778 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
779 + MTK_PHY_RG_TXVOS_CALEN);
780 +
781 + switch (rg_txreserve_x) {
782 + case PAIR_A:
783 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
784 + MTK_PHY_RG_DASN_DAC_IN0_A,
785 + MTK_PHY_DASN_DAC_IN0_A_MASK);
786 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
787 + MTK_PHY_RG_DASN_DAC_IN1_A,
788 + MTK_PHY_DASN_DAC_IN1_A_MASK);
789 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
790 + MTK_PHY_RG_ANA_CAL_RG0,
791 + MTK_PHY_RG_ZCALEN_A);
792 + break;
793 + case PAIR_B:
794 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
795 + MTK_PHY_RG_DASN_DAC_IN0_B,
796 + MTK_PHY_DASN_DAC_IN0_B_MASK);
797 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
798 + MTK_PHY_RG_DASN_DAC_IN1_B,
799 + MTK_PHY_DASN_DAC_IN1_B_MASK);
800 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
801 + MTK_PHY_RG_ANA_CAL_RG1,
802 + MTK_PHY_RG_ZCALEN_B);
803 + break;
804 + case PAIR_C:
805 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
806 + MTK_PHY_RG_DASN_DAC_IN0_C,
807 + MTK_PHY_DASN_DAC_IN0_C_MASK);
808 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
809 + MTK_PHY_RG_DASN_DAC_IN1_C,
810 + MTK_PHY_DASN_DAC_IN1_C_MASK);
811 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
812 + MTK_PHY_RG_ANA_CAL_RG1,
813 + MTK_PHY_RG_ZCALEN_C);
814 + break;
815 + case PAIR_D:
816 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
817 + MTK_PHY_RG_DASN_DAC_IN0_D,
818 + MTK_PHY_DASN_DAC_IN0_D_MASK);
819 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
820 + MTK_PHY_RG_DASN_DAC_IN1_D,
821 + MTK_PHY_DASN_DAC_IN1_D_MASK);
822 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
823 + MTK_PHY_RG_ANA_CAL_RG1,
824 + MTK_PHY_RG_ZCALEN_D);
825 + break;
826 + default:
827 + ret = -EINVAL;
828 + goto restore;
829 + }
830 +
831 + lower_idx = TXRESERVE_MIN;
832 + upper_idx = TXRESERVE_MAX;
833 +
834 + dev_dbg(&phydev->mdio.dev, "Start TX-VCM SW cal.\n");
835 + while ((upper_idx - lower_idx) > 1) {
836 + txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
837 + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
838 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
839 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
840 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
841 + MTK_PHY_DA_RX_PSBN_LP_MASK,
842 + txreserve_val << 12 | txreserve_val << 8 |
843 + txreserve_val << 4 | txreserve_val);
844 + if (ret == 1) {
845 + upper_idx = txreserve_val;
846 + upper_ret = ret;
847 + } else if (ret == 0) {
848 + lower_idx = txreserve_val;
849 + lower_ret = ret;
850 + } else {
851 + goto restore;
852 + }
853 + }
854 +
855 + if (lower_idx == TXRESERVE_MIN) {
856 + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
857 + MTK_PHY_RXADC_CTRL_RG9,
858 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
859 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
860 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
861 + MTK_PHY_DA_RX_PSBN_LP_MASK,
862 + lower_idx << 12 | lower_idx << 8 |
863 + lower_idx << 4 | lower_idx);
864 + ret = lower_ret;
865 + } else if (upper_idx == TXRESERVE_MAX) {
866 + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
867 + MTK_PHY_RXADC_CTRL_RG9,
868 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
869 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
870 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
871 + MTK_PHY_DA_RX_PSBN_LP_MASK,
872 + upper_idx << 12 | upper_idx << 8 |
873 + upper_idx << 4 | upper_idx);
874 + ret = upper_ret;
875 + }
876 + if (ret < 0)
877 + goto restore;
878 +
879 + /* We calibrate TX-VCM in different logic. Check upper index and then
880 + * lower index. If this calibration is valid, apply lower index's result.
881 + */
882 + ret = upper_ret - lower_ret;
883 + if (ret == 1) {
884 + ret = 0;
885 + /* Make sure we use upper_idx in our calibration system */
886 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
887 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
888 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
889 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
890 + MTK_PHY_DA_RX_PSBN_LP_MASK,
891 + upper_idx << 12 | upper_idx << 8 |
892 + upper_idx << 4 | upper_idx);
893 + dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n",
894 + upper_idx);
895 + } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
896 + lower_ret == 1) {
897 + ret = 0;
898 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
899 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
900 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
901 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
902 + MTK_PHY_DA_RX_PSBN_LP_MASK,
903 + lower_idx << 12 | lower_idx << 8 |
904 + lower_idx << 4 | lower_idx);
905 + dev_warn(&phydev->mdio.dev,
906 + "TX-VCM SW cal result at low margin 0x%x\n",
907 + lower_idx);
908 + } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
909 + lower_ret == 0) {
910 + ret = 0;
911 + dev_warn(&phydev->mdio.dev,
912 + "TX-VCM SW cal result at high margin 0x%x\n",
913 + upper_idx);
914 + } else {
915 + ret = -EINVAL;
916 + }
917 +
918 +restore:
919 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
920 + MTK_PHY_RG_ANA_CALEN);
921 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
922 + MTK_PHY_RG_TXVOS_CALEN);
923 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
924 + MTK_PHY_RG_ZCALEN_A);
925 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
926 + MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
927 + MTK_PHY_RG_ZCALEN_D);
928 +
929 + return ret;
930 +}
931 +
932 +static inline void mt7981_phy_finetune(struct phy_device *phydev)
933 +{
934 + u32 i;
935 +
936 + /* 100M eye finetune:
937 + * Keep middle level of TX MLT3 shapper as default.
938 + * Only change TX MLT3 overshoot level here.
939 + */
940 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1,
941 + 0x1ce);
942 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1,
943 + 0x1c1);
944 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0,
945 + 0x20f);
946 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0,
947 + 0x202);
948 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1,
949 + 0x3d0);
950 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1,
951 + 0x3c0);
952 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0,
953 + 0x13);
954 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0,
955 + 0x5);
956 +
957 + /* TX-AMP finetune:
958 + * 100M +4, 1000M +6 to default value.
959 + * If efuse values aren't valid, TX-AMP uses the below values.
960 + */
961 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 0x9824);
962 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
963 + 0x9026);
964 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
965 + 0x2624);
966 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
967 + 0x2426);
968 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
969 + 0x2624);
970 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
971 + 0x2426);
972 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
973 + 0x2624);
974 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
975 + 0x2426);
976 +
977 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
978 + /* EnabRandUpdTrig = 1 */
979 + __phy_write(phydev, 0x11, 0x2f00);
980 + __phy_write(phydev, 0x12, 0xe);
981 + __phy_write(phydev, 0x10, 0x8fb0);
982 +
983 + /* SlvDSPreadyTime = 0xc */
984 + __phy_write(phydev, 0x11, 0x671);
985 + __phy_write(phydev, 0x12, 0xc);
986 + __phy_write(phydev, 0x10, 0x8fae);
987 +
988 + /* NormMseLoThresh = 85 */
989 + __phy_write(phydev, 0x11, 0x55a0);
990 + __phy_write(phydev, 0x12, 0x0);
991 + __phy_write(phydev, 0x10, 0x83aa);
992 +
993 + /* InhibitDisableDfeTail1000 = 1 */
994 + __phy_write(phydev, 0x11, 0x2b);
995 + __phy_write(phydev, 0x12, 0x0);
996 + __phy_write(phydev, 0x10, 0x8f80);
997 +
998 + /* SSTr related */
999 + __phy_write(phydev, 0x11, 0xbaef);
1000 + __phy_write(phydev, 0x12, 0x2e);
1001 + __phy_write(phydev, 0x10, 0x968c);
1002 +
1003 + /* VcoSlicerThreshBitsHigh */
1004 + __phy_write(phydev, 0x11, 0x5555);
1005 + __phy_write(phydev, 0x12, 0x55);
1006 + __phy_write(phydev, 0x10, 0x8ec0);
1007 +
1008 + /* ResetSyncOffset = 6 */
1009 + __phy_write(phydev, 0x11, 0x600);
1010 + __phy_write(phydev, 0x12, 0x0);
1011 + __phy_write(phydev, 0x10, 0x8fc0);
1012 +
1013 + /* VgaDecRate = 1 */
1014 + __phy_write(phydev, 0x11, 0x4c2a);
1015 + __phy_write(phydev, 0x12, 0x3e);
1016 + __phy_write(phydev, 0x10, 0x8fa4);
1017 +
1018 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1019 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
1020 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
1021 + MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
1022 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
1023 +
1024 + /* rg_tr_lpf_cnt_val = 512 */
1025 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
1026 +
1027 + /* IIR2 related */
1028 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
1029 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
1030 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
1031 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
1032 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
1033 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
1034 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
1035 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
1036 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
1037 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
1038 +
1039 + /* FFE peaking */
1040 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
1041 + MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
1042 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
1043 + MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
1044 +
1045 + /* TX shape */
1046 + /* 10/100/1000 TX shaper is enabled by default */
1047 + for (i = 0x202; i < 0x230; i += 2) {
1048 + if (i == 0x20c || i == 0x218 || i == 0x224)
1049 + continue;
1050 + phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219);
1051 + phy_write_mmd(phydev, MDIO_MMD_VEND2, i + 1, 0x23);
1052 + }
1053 +}
1054 +
1055 +static inline void mt7988_phy_finetune(struct phy_device *phydev)
1056 +{
1057 + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
1058 + 0x020d, 0x0206, 0x0384, 0x03d0,
1059 + 0x03c6, 0x030a, 0x0011, 0x0005 };
1060 + int i;
1061 +
1062 + for (i = 0; i < MTK_PHY_TX_MLT3_END; i++)
1063 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
1064 +
1065 + /* TCT finetune */
1066 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
1067 +
1068 + /* Disable TX power saving */
1069 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
1070 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
1071 +
1072 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1073 + /* EnabRandUpdTrig = 1 */
1074 + __phy_write(phydev, 0x11, 0x2f00);
1075 + __phy_write(phydev, 0x12, 0xe);
1076 + __phy_write(phydev, 0x10, 0x8fb0);
1077 +
1078 + /* SlvDSPreadyTime = 0xc */
1079 + __phy_write(phydev, 0x11, 0x671);
1080 + __phy_write(phydev, 0x12, 0xc);
1081 + __phy_write(phydev, 0x10, 0x8fae);
1082 +
1083 + /* NormMseLoThresh = 85 */
1084 + __phy_write(phydev, 0x11, 0x55a0);
1085 + __phy_write(phydev, 0x12, 0x0);
1086 + __phy_write(phydev, 0x10, 0x83aa);
1087 +
1088 + /* InhibitDisableDfeTail1000 = 1 */
1089 + __phy_write(phydev, 0x11, 0x2b);
1090 + __phy_write(phydev, 0x12, 0x0);
1091 + __phy_write(phydev, 0x10, 0x8f80);
1092 +
1093 + /* SSTr related */
1094 + __phy_write(phydev, 0x11, 0xbaef);
1095 + __phy_write(phydev, 0x12, 0x2e);
1096 + __phy_write(phydev, 0x10, 0x968c);
1097 +
1098 + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
1099 + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
1100 + */
1101 + __phy_write(phydev, 0x11, 0xd10a);
1102 + __phy_write(phydev, 0x12, 0x34);
1103 + __phy_write(phydev, 0x10, 0x8f82);
1104 +
1105 + /* VcoSlicerThreshBitsHigh */
1106 + __phy_write(phydev, 0x11, 0x5555);
1107 + __phy_write(phydev, 0x12, 0x55);
1108 + __phy_write(phydev, 0x10, 0x8ec0);
1109 +
1110 + /* ResetSyncOffset = 5 */
1111 + __phy_write(phydev, 0x11, 0x500);
1112 + __phy_write(phydev, 0x12, 0x0);
1113 + __phy_write(phydev, 0x10, 0x8fc0);
1114 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1115 +
1116 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
1117 + /* TxClkOffset = 2 */
1118 + __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
1119 + FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
1120 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1121 +
1122 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
1123 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
1124 + MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
1125 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
1126 +
1127 + /* rg_tr_lpf_cnt_val = 512 */
1128 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
1129 +
1130 + /* IIR2 related */
1131 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
1132 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
1133 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
1134 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
1135 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
1136 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
1137 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
1138 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
1139 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
1140 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
1141 +
1142 + /* FFE peaking */
1143 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
1144 + MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
1145 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
1146 + MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
1147 +
1148 + /* TX shape */
1149 + /* 10/100/1000 TX shaper is enabled by default */
1150 + for (i = 0x202; i < 0x230; i += 2) {
1151 + if (i == 0x20c || i == 0x218 || i == 0x224)
1152 + continue;
1153 + phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219);
1154 + phy_write_mmd(phydev, MDIO_MMD_VEND2, i + 1, 0x23);
1155 + }
1156 +
1157 + /* Disable LDO pump */
1158 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
1159 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
1160 +
1161 + /* Adjust LDO output voltage */
1162 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
1163 +}
1164 +
1165 +static inline int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
1166 + u8 start_pair, u8 end_pair)
1167 +{
1168 + u8 pair_n;
1169 + int ret;
1170 +
1171 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1172 + /* TX_OFFSET & TX_AMP have no SW calibration. */
1173 + switch (cal_item) {
1174 + case REXT:
1175 + ret = rext_cal_sw(phydev);
1176 + break;
1177 + case TX_R50:
1178 + ret = tx_r50_cal_sw(phydev, pair_n);
1179 + break;
1180 + case TX_VCM:
1181 + ret = tx_vcm_cal_sw(phydev, pair_n);
1182 + break;
1183 + default:
1184 + return -EINVAL;
1185 + }
1186 + if (ret)
1187 + return ret;
1188 + }
1189 + return 0;
1190 +}
1191 +
1192 +static inline int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
1193 + u8 start_pair, u8 end_pair, u32 *buf)
1194 +{
1195 + u8 pair_n;
1196 + int ret;
1197 +
1198 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1199 + /* TX_VCM has no efuse calibration. */
1200 + switch (cal_item) {
1201 + case REXT:
1202 + ret = rext_cal_efuse(phydev, buf);
1203 + break;
1204 + case TX_OFFSET:
1205 + ret = tx_offset_cal_efuse(phydev, buf);
1206 + break;
1207 + case TX_AMP:
1208 + ret = tx_amp_cal_efuse(phydev, buf);
1209 + break;
1210 + case TX_R50:
1211 + ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1212 + break;
1213 + default:
1214 + return -EINVAL;
1215 + }
1216 + if (ret)
1217 + return ret;
1218 + }
1219 +
1220 + return 0;
1221 +}
1222 +
1223 +static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1224 + bool efs_valid, enum CAL_MODE cal_mode, u8 start_pair,
1225 + u8 end_pair, u32 *buf)
1226 +{
1227 + char cal_prop[5][20] = { "mediatek,rext", "mediatek,tx_offset",
1228 + "mediatek,tx_amp", "mediatek,tx_r50",
1229 + "mediatek,tx_vcm" };
1230 + const char *dts_cal_mode;
1231 + u8 final_cal_mode = 0;
1232 + bool is_cal = true;
1233 + int ret, cal_ret;
1234 +
1235 + ret = of_property_read_string(phydev->mdio.dev.of_node,
1236 + cal_prop[cal_item], &dts_cal_mode);
1237 +
1238 + switch (cal_mode) {
1239 + case SW_EFUSE_M:
1240 + if ((efs_valid && ret) ||
1241 + (efs_valid && !ret && strcmp("efuse", dts_cal_mode) == 0)) {
1242 + cal_ret = cal_efuse(phydev, cal_item, start_pair,
1243 + end_pair, buf);
1244 + final_cal_mode = EFUSE_K;
1245 + } else if ((!efs_valid && ret) ||
1246 + (!ret && strcmp("sw", dts_cal_mode) == 0)) {
1247 + cal_ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1248 + final_cal_mode = SW_K;
1249 + } else {
1250 + is_cal = false;
1251 + }
1252 + break;
1253 + case EFUSE_M:
1254 + if ((efs_valid && ret) ||
1255 + (efs_valid && !ret && strcmp("efuse", dts_cal_mode) == 0)) {
1256 + cal_ret = cal_efuse(phydev, cal_item, start_pair,
1257 + end_pair, buf);
1258 + final_cal_mode = EFUSE_K;
1259 + } else {
1260 + is_cal = false;
1261 + }
1262 + break;
1263 + case SW_M:
1264 + if (ret || (!ret && strcmp("sw", dts_cal_mode) == 0)) {
1265 + cal_ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1266 + final_cal_mode = SW_K;
1267 + } else {
1268 + is_cal = false;
1269 + }
1270 + break;
1271 + default:
1272 + return -EINVAL;
1273 + }
1274 +
1275 + if (cal_ret) {
1276 + dev_err(&phydev->mdio.dev, "[%s]cal failed\n", cal_prop[cal_item]);
1277 + return -EIO;
1278 + }
1279 +
1280 + if (!is_cal) {
1281 + dev_dbg(&phydev->mdio.dev, "[%s]K mode: %s(not supported)\n",
1282 + cal_prop[cal_item], dts_cal_mode);
1283 + return -EIO;
1284 + }
1285 +
1286 + dev_dbg(&phydev->mdio.dev, "[%s]K mode: %s(dts: %s), efs-valid: %s\n",
1287 + cal_prop[cal_item],
1288 + final_cal_mode ? "SW" : "EFUSE",
1289 + ret ? "not set" : dts_cal_mode,
1290 + efs_valid ? "yes" : "no");
1291 + return 0;
1292 +}
1293 +
1294 +static int mt798x_phy_calibration(struct phy_device *phydev)
1295 +{
1296 + int ret = 0;
1297 + u32 *buf;
1298 + bool efs_valid = true;
1299 + size_t len;
1300 + struct nvmem_cell *cell;
1301 +
1302 + if (phydev->interface != PHY_INTERFACE_MODE_GMII)
1303 + return -EINVAL;
1304 +
1305 + cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1306 + if (IS_ERR(cell)) {
1307 + if (PTR_ERR(cell) == -EPROBE_DEFER)
1308 + return PTR_ERR(cell);
1309 + return 0;
1310 + }
1311 +
1312 + buf = (u32 *)nvmem_cell_read(cell, &len);
1313 + if (IS_ERR(buf))
1314 + return PTR_ERR(buf);
1315 + nvmem_cell_put(cell);
1316 +
1317 + if (!buf[0] || !buf[1] || !buf[2] || !buf[3])
1318 + efs_valid = false;
1319 +
1320 + if (len < 4 * sizeof(u32)) {
1321 + dev_err(&phydev->mdio.dev, "invalid calibration data\n");
1322 + ret = -EINVAL;
1323 + goto out;
1324 + }
1325 +
1326 + ret = start_cal(phydev, REXT, efs_valid, SW_EFUSE_M,
1327 + NO_PAIR, NO_PAIR, buf);
1328 + if (ret)
1329 + goto out;
1330 + ret = start_cal(phydev, TX_OFFSET, efs_valid, EFUSE_M,
1331 + NO_PAIR, NO_PAIR, buf);
1332 + if (ret)
1333 + goto out;
1334 + ret = start_cal(phydev, TX_AMP, efs_valid, EFUSE_M,
1335 + NO_PAIR, NO_PAIR, buf);
1336 + if (ret)
1337 + goto out;
1338 + ret = start_cal(phydev, TX_R50, efs_valid, EFUSE_M,
1339 + PAIR_A, PAIR_D, buf);
1340 + if (ret)
1341 + goto out;
1342 + ret = start_cal(phydev, TX_VCM, efs_valid, SW_M,
1343 + PAIR_A, PAIR_A, buf);
1344 + if (ret)
1345 + goto out;
1346 +
1347 +out:
1348 + kfree(buf);
1349 + return ret;
1350 +}
1351 +
1352 +static int mt7981_phy_probe(struct phy_device *phydev)
1353 +{
1354 + mt7981_phy_finetune(phydev);
1355 +
1356 + return mt798x_phy_calibration(phydev);
1357 +}
1358 +
1359 +static int mt7988_phy_probe(struct phy_device *phydev)
1360 +{
1361 + struct device_node *np;
1362 + void __iomem *boottrap;
1363 + u32 reg;
1364 + int port;
1365 +
1366 + /* Setup LED polarity according to boottrap's polarity */
1367 + np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap");
1368 + if (!np)
1369 + return -ENOENT;
1370 + boottrap = of_iomap(np, 0);
1371 + if (!boottrap)
1372 + return -ENOMEM;
1373 + reg = readl(boottrap);
1374 + port = phydev->mdio.addr;
1375 + if ((port == GPHY_PORT0 && reg & BIT(8)) ||
1376 + (port == GPHY_PORT1 && reg & BIT(9)) ||
1377 + (port == GPHY_PORT2 && reg & BIT(10)) ||
1378 + (port == GPHY_PORT3 && reg & BIT(11))) {
1379 + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
1380 + MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_ON_LINK10 |
1381 + MTK_PHY_LED0_ON_LINK100 |
1382 + MTK_PHY_LED0_ON_LINK1000);
1383 + } else {
1384 + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
1385 + MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY |
1386 + MTK_PHY_LED0_ON_LINK10 |
1387 + MTK_PHY_LED0_ON_LINK100 |
1388 + MTK_PHY_LED0_ON_LINK1000);
1389 + }
1390 + phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
1391 + MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX |
1392 + MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX |
1393 + MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX);
1394 +
1395 + mt7988_phy_finetune(phydev);
1396 +
1397 + return mt798x_phy_calibration(phydev);
1398 +}
1399 +#endif
1400 +
1401 static struct phy_driver mtk_gephy_driver[] = {
1402 {
1403 PHY_ID_MATCH_EXACT(0x03a29412),
1404 @@ -97,6 +1422,30 @@ static struct phy_driver mtk_gephy_drive
1405 .read_page = mtk_gephy_read_page,
1406 .write_page = mtk_gephy_write_page,
1407 },
1408 +#ifdef CONFIG_MEDIATEK_GE_PHY_SOC
1409 + {
1410 + PHY_ID_MATCH_EXACT(0x03a29461),
1411 + .name = "MediaTek MT7981 PHY",
1412 + .probe = mt7981_phy_probe,
1413 + .config_intr = genphy_no_config_intr,
1414 + .handle_interrupt = genphy_handle_interrupt_no_ack,
1415 + .suspend = genphy_suspend,
1416 + .resume = genphy_resume,
1417 + .read_page = mtk_gephy_read_page,
1418 + .write_page = mtk_gephy_write_page,
1419 + },
1420 + {
1421 + PHY_ID_MATCH_EXACT(0x03a29481),
1422 + .name = "MediaTek MT7988 PHY",
1423 + .probe = mt7988_phy_probe,
1424 + .config_intr = genphy_no_config_intr,
1425 + .handle_interrupt = genphy_handle_interrupt_no_ack,
1426 + .suspend = genphy_suspend,
1427 + .resume = genphy_resume,
1428 + .read_page = mtk_gephy_read_page,
1429 + .write_page = mtk_gephy_write_page,
1430 + },
1431 +#endif
1432 };
1433
1434 module_phy_driver(mtk_gephy_driver);
1435 @@ -107,6 +1456,8 @@ static struct mdio_device_id __maybe_unu
1436 };
1437
1438 MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
1439 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1440 +MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1441 MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
1442 MODULE_LICENSE("GPL");
1443
OpenWrt Source Repository