target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch

   1 diff -urN a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
   2 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts  2019-12-02 14:33:30.126586402 +0800
   3 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts  2019-12-02 14:35:02.304005081 +0800
   4 @@ -53,6 +53,13 @@
   5                 };
   6         };
   7
   8 +       gsw: gsw@0 {
   9 +               compatible = "mediatek,mt753x";
  10 +               mediatek,ethsys = <&ethsys>;
  11 +               #address-cells = <1>;
  12 +               #size-cells = <0>;
  13 +       };
  14 +
  15         leds {
  16                 compatible = "gpio-leds";
  17
  18 @@ -146,6 +153,36 @@
  19         };
  20  };
  21
  22 +&gsw {
  23 +        mediatek,mdio = <&mdio>;
  24 +        mediatek,portmap = "wllll";
  25 +        mediatek,mdio_master_pinmux = <0>;
  26 +        reset-gpios = <&pio 54 0>;
  27 +        interrupt-parent = <&pio>;
  28 +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
  29 +        status = "okay";
  30 +
  31 +        port5: port@5 {
  32 +                compatible = "mediatek,mt753x-port";
  33 +                reg = <5>;
  34 +                phy-mode = "rgmii";
  35 +                fixed-link {
  36 +                        speed = <1000>;
  37 +                        full-duplex;
  38 +                };
  39 +        };
  40 +
  41 +        port6: port@6 {
  42 +                compatible = "mediatek,mt753x-port";
  43 +                reg = <6>;
  44 +                phy-mode = "sgmii";
  45 +                fixed-link {
  46 +                        speed = <2500>;
  47 +                        full-duplex;
  48 +                };
  49 +        };
  50 +};
  51 +
  52  &i2c1 {
  53         pinctrl-names = "default";
  54         pinctrl-0 = <&i2c1_pins>;
  55 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts      2020-01-12 19:21:53.000000000 +0800
  56 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts      2020-01-15 15:36:50.987901563 +0800
  57 @@ -1,7 +1,6 @@
  58  /*
  59 - * Copyright (c) 2017 MediaTek Inc.
  60 - * Author: Ming Huang <ming.huang@mediatek.com>
  61 - *        Sean Wang <sean.wang@mediatek.com>
  62 + * Copyright (c) 2018 MediaTek Inc.
  63 + * Author: Ryder Lee <ryder.lee@mediatek.com>
  64   *
  65   * SPDX-License-Identifier: (GPL-2.0 OR MIT)
  66   */
  67 @@ -14,8 +13,8 @@
  68  #include "mt6380.dtsi"
  69
  70  / {
  71 -       model = "MediaTek MT7622 RFB1 board";
  72 -       compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  73 +       model = "MT7622_MT7531 RFB";
  74 +       compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  75
  76         aliases {
  77                 serial0 = &uart0;
  78 @@ -23,7 +22,7 @@
  79
  80         chosen {
  81                 stdout-path = "serial0:115200n8";
  82 -               bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  83 +               bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  84         };
  85
  86         cpus {
  87 @@ -40,23 +39,45 @@
  88
  89         gpio-keys {
  90                 compatible = "gpio-keys";
  91 -               poll-interval = <100>;
  92
  93                 factory {
  94                         label = "factory";
  95                         linux,code = <BTN_0>;
  96 -                       gpios = <&pio 0 0>;
  97 +                       gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  98                 };
  99
 100                 wps {
 101                         label = "wps";
 102                         linux,code = <KEY_WPS_BUTTON>;
 103 -                       gpios = <&pio 102 0>;
 104 +                       gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
 105 +               };
 106 +       };
 107 +
 108 +       gsw: gsw@0 {
 109 +                compatible = "mediatek,mt753x";
 110 +                mediatek,ethsys = <&ethsys>;
 111 +                #address-cells = <1>;
 112 +                #size-cells = <0>;
 113 +        };
 114 +
 115 +       leds {
 116 +               compatible = "gpio-leds";
 117 +
 118 +               green {
 119 +                       label = "bpi-r64:pio:green";
 120 +                       gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
 121 +                       default-state = "off";
 122 +               };
 123 +
 124 +               red {
 125 +                       label = "bpi-r64:pio:red";
 126 +                       gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
 127 +                       default-state = "off";
 128                 };
 129         };
 130
 131         memory {
 132 -               reg = <0 0x40000000 0 0x20000000>;
 133 +               reg = <0 0x40000000 0 0x40000000>;
 134         };
 135
 136         reg_1p8v: regulator-1p8v {
 137 @@ -101,27 +122,67 @@
 138  };
 139
 140  &eth {
 141 -       pinctrl-names = "default";
 142 -       pinctrl-0 = <&eth_pins>;
 143         status = "okay";
 144 +       gmac0: mac@0 {
 145 +               compatible = "mediatek,eth-mac";
 146 +               reg = <0>;
 147 +               phy-mode = "2500base-x";
 148 +
 149 +               fixed-link {
 150 +                       speed = <2500>;
 151 +                       full-duplex;
 152 +                       pause;
 153 +               };
 154 +       };
 155
 156         gmac1: mac@1 {
 157                 compatible = "mediatek,eth-mac";
 158                 reg = <1>;
 159 -               phy-handle = <&phy5>;
 160 +               phy-mode = "rgmii";
 161 +
 162 +               fixed-link {
 163 +                       speed = <1000>;
 164 +                       full-duplex;
 165 +                       pause;
 166 +               };
 167         };
 168
 169 -       mdio-bus {
 170 +       mdio: mdio-bus {
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173 -
 174 -               phy5: ethernet-phy@5 {
 175 -                       reg = <5>;
 176 -                       phy-mode = "sgmii";
 177 -               };
 178         };
 179  };
 180
 181 +&gsw {
 182 +        mediatek,mdio = <&mdio>;
 183 +        mediatek,portmap = "llllw";
 184 +        mediatek,mdio_master_pinmux = <0>;
 185 +        reset-gpios = <&pio 54 0>;
 186 +        interrupt-parent = <&pio>;
 187 +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 188 +        status = "okay";
 189 +
 190 +        port5: port@5 {
 191 +                compatible = "mediatek,mt753x-port";
 192 +                reg = <5>;
 193 +                phy-mode = "rgmii";
 194 +                fixed-link {
 195 +                        speed = <1000>;
 196 +                        full-duplex;
 197 +                };
 198 +        };
 199 +
 200 +        port6: port@6 {
 201 +                compatible = "mediatek,mt753x-port";
 202 +                reg = <6>;
 203 +                phy-mode = "sgmii";
 204 +                fixed-link {
 205 +                        speed = <2500>;
 206 +                        full-duplex;
 207 +                };
 208 +        };
 209 +};
 210 +
 211  &i2c1 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&i2c1_pins>;
 214 @@ -185,15 +246,28 @@
 215
 216  &pcie {
 217         pinctrl-names = "default";
 218 -       pinctrl-0 = <&pcie0_pins>;
 219 +       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 220         status = "okay";
 221
 222         pcie@0,0 {
 223                 status = "okay";
 224         };
 225 +
 226 +       pcie@1,0 {
 227 +               status = "okay";
 228 +       };
 229  };
 230
 231  &pio {
 232 +       /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 233 +        * SATA functions. i.e. output-high: PCIe, output-low: SATA
 234 +        */
 235 +       asm_sel {
 236 +               gpio-hog;
 237 +               gpios = <90 GPIO_ACTIVE_HIGH>;
 238 +               output-high;
 239 +       };
 240 +
 241         /* eMMC is shared pin with parallel NAND */
 242         emmc_pins_default: emmc-pins-default {
 243                 mux {
 244 @@ -460,11 +534,11 @@
 245  };
 246
 247  &sata {
 248 -       status = "okay";
 249 +       status = "disable";
 250  };
 251
 252  &sata_phy {
 253 -       status = "okay";
 254 +       status = "disable";
 255  };
 256
 257  &spi0 {