target/linux/mediatek/patches-5.4/0227-arm-dts-Add-Unielec-U7623-DTS.patch

   1 From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Sun, 17 Jun 2018 14:41:47 +0200
   4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
   5
   6 ---
   7  arch/arm/boot/dts/Makefile                         |   1 +
   8  .../dts/mt7623a-unielec-u7623-02-emmc-512m.dts     |  18 +
   9  .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 366 +++++++++++++++++++++
  10  3 files changed, 385 insertions(+)
  11  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
  12  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  13
  14 --- a/arch/arm/boot/dts/Makefile
  15 +++ b/arch/arm/boot/dts/Makefile
  16 @@ -1193,6 +1193,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  17         mt7623a-rfb-nand.dtb \
  18         mt7623n-rfb-emmc.dtb \
  19         mt7623n-bananapi-bpi-r2.dtb \
  20 +       mt7623a-unielec-u7623-02-emmc-512m.dtb \
  21         mt7629-rfb.dtb \
  22         mt8127-moose.dtb \
  23         mt8135-evbp1.dtb
  24  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
  25 --- /dev/null
  26 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
  27 @@ -0,0 +1,18 @@
  28 +/*
  29 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  30 + *
  31 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  32 + */
  33 +
  34 +/dts-v1/;
  35 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
  36 +
  37 +/ {
  38 +       model = "UniElec U7623-02 eMMC (512M RAM)";
  39 +       compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
  40 +
  41 +       memory@80000000 {
  42 +               device_type = "memory";
  43 +               reg = <0 0x80000000 0 0x20000000>;
  44 +       };
  45 +};
  46 --- /dev/null
  47 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  48 @@ -0,0 +1,349 @@
  49 +/*
  50 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  51 + *
  52 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  53 + */
  54 +
  55 +#include <dt-bindings/input/input.h>
  56 +#include "mt7623.dtsi"
  57 +#include "mt6323.dtsi"
  58 +
  59 +/ {
  60 +       compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
  61 +
  62 +       aliases {
  63 +               serial2 = &uart2;
  64 +       };
  65 +
  66 +       chosen {
  67 +               bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
  68 +               stdout-path = "serial2:115200n8";
  69 +       };
  70 +
  71 +       cpus {
  72 +               cpu@0 {
  73 +                       proc-supply = <&mt6323_vproc_reg>;
  74 +               };
  75 +
  76 +               cpu@1 {
  77 +                       proc-supply = <&mt6323_vproc_reg>;
  78 +               };
  79 +
  80 +               cpu@2 {
  81 +                       proc-supply = <&mt6323_vproc_reg>;
  82 +               };
  83 +
  84 +               cpu@3 {
  85 +                       proc-supply = <&mt6323_vproc_reg>;
  86 +               };
  87 +       };
  88 +
  89 +       reg_1p8v: regulator-1p8v {
  90 +               compatible = "regulator-fixed";
  91 +               regulator-name = "fixed-1.8V";
  92 +               regulator-min-microvolt = <1800000>;
  93 +               regulator-max-microvolt = <1800000>;
  94 +               regulator-boot-on;
  95 +               regulator-always-on;
  96 +       };
  97 +
  98 +       reg_3p3v: regulator-3p3v {
  99 +               compatible = "regulator-fixed";
 100 +               regulator-name = "fixed-3.3V";
 101 +               regulator-min-microvolt = <3300000>;
 102 +               regulator-max-microvolt = <3300000>;
 103 +               regulator-boot-on;
 104 +               regulator-always-on;
 105 +       };
 106 +
 107 +       reg_5v: regulator-5v {
 108 +               compatible = "regulator-fixed";
 109 +               regulator-name = "fixed-5V";
 110 +               regulator-min-microvolt = <5000000>;
 111 +               regulator-max-microvolt = <5000000>;
 112 +               regulator-boot-on;
 113 +               regulator-always-on;
 114 +       };
 115 +
 116 +       gpio-keys {
 117 +               compatible = "gpio-keys";
 118 +               pinctrl-names = "default";
 119 +               pinctrl-0 = <&key_pins_a>;
 120 +
 121 +               factory {
 122 +                       label = "factory";
 123 +                       linux,code = <KEY_RESTART>;
 124 +                       gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 125 +               };
 126 +       };
 127 +
 128 +       leds {
 129 +               compatible = "gpio-leds";
 130 +               pinctrl-names = "default";
 131 +               pinctrl-0 = <&led_pins_unielec>;
 132 +
 133 +               led3 {
 134 +                       label = "u7623-01:green:led3";
 135 +                       gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 136 +                       default-state = "off";
 137 +               };
 138 +
 139 +               led4 {
 140 +                       label = "u7623-01:green:led4";
 141 +                       gpios = <&pio 15 GPIO_ACTIVE_LOW>;
 142 +                       default-state = "off";
 143 +               };
 144 +       };
 145 +
 146 +       mt7530: switch@0 {
 147 +               compatible = "mediatek,mt7530";
 148 +               #address-cells = <1>;
 149 +               #size-cells = <0>;
 150 +       };
 151 +};
 152 +
 153 +&crypto {
 154 +       status = "okay";
 155 +};
 156 +
 157 +&eth {
 158 +       status = "okay";
 159 +
 160 +       gmac0: mac@0 {
 161 +               compatible = "mediatek,eth-mac";
 162 +               reg = <0>;
 163 +               phy-mode = "trgmii";
 164 +
 165 +               fixed-link {
 166 +                       speed = <1000>;
 167 +                       full-duplex;
 168 +                       pause;
 169 +               };
 170 +       };
 171 +
 172 +       mdio: mdio-bus {
 173 +               #address-cells = <1>;
 174 +               #size-cells = <0>;
 175 +               phy5: ethernet-phy@5 {
 176 +                       reg = <5>;
 177 +                       phy-mode = "rgmii-rxid";
 178 +               };
 179 +       };
 180 +};
 181 +
 182 +&mt7530 {
 183 +       compatible = "mediatek,mt7530";
 184 +       #address-cells = <1>;
 185 +       #size-cells = <0>;
 186 +       reg = <0>;
 187 +       pinctrl-names = "default";
 188 +       mediatek,mcm;
 189 +       resets = <&ethsys 2>;
 190 +       reset-names = "mcm";
 191 +       core-supply = <&mt6323_vpa_reg>;
 192 +       io-supply = <&mt6323_vemc3v3_reg>;
 193 +
 194 +       dsa,mii-bus = <&mdio>;
 195 +
 196 +       ports {
 197 +               #address-cells = <1>;
 198 +               #size-cells = <0>;
 199 +               reg = <0>;
 200 +
 201 +               port@0 {
 202 +                       reg = <0>;
 203 +                       label = "lan0";
 204 +                       cpu = <&cpu_port0>;
 205 +               };
 206 +
 207 +               port@1 {
 208 +                       reg = <1>;
 209 +                       label = "lan1";
 210 +                       cpu = <&cpu_port0>;
 211 +               };
 212 +
 213 +               port@2 {
 214 +                       reg = <2>;
 215 +                       label = "lan2";
 216 +                       cpu = <&cpu_port0>;
 217 +               };
 218 +
 219 +               port@3 {
 220 +                       reg = <3>;
 221 +                       label = "lan3";
 222 +                       cpu = <&cpu_port0>;
 223 +               };
 224 +
 225 +               port@4 {
 226 +                       reg = <4>;
 227 +                       label = "wan";
 228 +                       cpu = <&cpu_port0>;
 229 +               };
 230 +
 231 +               cpu_port0: port@6 {
 232 +                       reg = <6>;
 233 +                       label = "cpu";
 234 +                       ethernet = <&gmac0>;
 235 +                       phy-mode = "trgmii";
 236 +
 237 +                       fixed-link {
 238 +                               speed = <1000>;
 239 +                               full-duplex;
 240 +                       };
 241 +               };
 242 +       };
 243 +};
 244 +
 245 +&mmc0 {
 246 +       pinctrl-names = "default", "state_uhs";
 247 +       pinctrl-0 = <&mmc0_pins_default>;
 248 +       pinctrl-1 = <&mmc0_pins_uhs>;
 249 +       status = "okay";
 250 +       bus-width = <8>;
 251 +       max-frequency = <50000000>;
 252 +       cap-mmc-highspeed;
 253 +       vmmc-supply = <&reg_3p3v>;
 254 +       vqmmc-supply = <&reg_1p8v>;
 255 +       non-removable;
 256 +};
 257 +
 258 +&pio {
 259 +       key_pins_a: keys-alt {
 260 +               pins-keys {
 261 +                       pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
 262 +                                <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
 263 +                       input-enable;
 264 +               };
 265 +       };
 266 +
 267 +       led_pins_unielec: leds-unielec {
 268 +               pins-leds {
 269 +                       pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
 270 +                                <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 271 +               };
 272 +       };
 273 +
 274 +       mmc0_pins_default: mmc0default {
 275 +               pins_cmd_dat {
 276 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 277 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 278 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 279 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 280 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 281 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 282 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 283 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 284 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 285 +                       input-enable;
 286 +                       bias-pull-up;
 287 +               };
 288 +
 289 +               pins_clk {
 290 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 291 +                       bias-pull-down;
 292 +               };
 293 +
 294 +               pins_rst {
 295 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 296 +                       bias-pull-up;
 297 +               };
 298 +       };
 299 +
 300 +       mmc0_pins_uhs: mmc0 {
 301 +               pins_cmd_dat {
 302 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 303 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 304 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 305 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 306 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 307 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 308 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 309 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 310 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 311 +                       input-enable;
 312 +                       drive-strength = <MTK_DRIVE_2mA>;
 313 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 314 +               };
 315 +
 316 +               pins_clk {
 317 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 318 +                       drive-strength = <MTK_DRIVE_2mA>;
 319 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 320 +               };
 321 +
 322 +               pins_rst {
 323 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 324 +                       bias-pull-up;
 325 +               };
 326 +       };
 327 +
 328 +       pcie_default: pcie_pin_default {
 329 +               pins_cmd_dat {
 330 +                       pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
 331 +                                <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
 332 +                       bias-disable;
 333 +               };
 334 +       };
 335 +};
 336 +
 337 +&pwm {
 338 +       pinctrl-names = "default";
 339 +       pinctrl-0 = <&pwm_pins_a>;
 340 +       status = "okay";
 341 +};
 342 +
 343 +&pwrap {
 344 +       mt6323 {
 345 +               mt6323led: led {
 346 +                       compatible = "mediatek,mt6323-led";
 347 +                       #address-cells = <1>;
 348 +                       #size-cells = <0>;
 349 +
 350 +                       led@0 {
 351 +                               reg = <0>;
 352 +                               label = "led0";
 353 +                               default-state = "off";
 354 +                       };
 355 +               };
 356 +       };
 357 +};
 358 +
 359 +&uart2 {
 360 +       pinctrl-names = "default";
 361 +       pinctrl-0 = <&uart2_pins_b>;
 362 +       status = "okay";
 363 +};
 364 +
 365 +&usb1 {
 366 +       vusb33-supply = <&reg_3p3v>;
 367 +       vbus-supply = <&reg_3p3v>;
 368 +       status = "okay";
 369 +};
 370 +
 371 +&u3phy1 {
 372 +       status = "okay";
 373 +};
 374 +
 375 +&u3phy2 {
 376 +       status = "okay";
 377 +       mediatek,phy-switch = <&hifsys>;
 378 +};
 379 +
 380 +&pcie {
 381 +       pinctrl-names = "default";
 382 +       pinctrl-0 = <&pcie_default>;
 383 +       status = "okay";
 384 +
 385 +       pcie@1,0 {
 386 +               status = "okay";
 387 +       };
 388 +
 389 +       pcie@2,0 {
 390 +               status = "okay";
 391 +       };
 392 +};
 393 +
 394 +&pcie1_phy {
 395 +       status = "okay";
 396 +};
 397 +