target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch

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  72 From: <chuanjia.liu@mediatek.com>
  73 To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
  74 Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding
  75 Date: Thu, 28 May 2020 14:16:45 +0800
  76 Message-ID: <20200528061648.32078-2-chuanjia.liu@mediatek.com>
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 105 X-BeenThere: linux-mediatek@lists.infradead.org
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 116 Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
 117  srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
 118  linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
 119  jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
 120  yong.wu@mediatek.com, bhelgaas@google.com,
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 122 Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
 123 Errors-To:
 124  linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
 125
 126 From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
 127
 128 There are two independent PCIe controllers in MT2712/MT7622 platform,
 129 and each of them should contain an independent MSI domain.
 130
 131 In current architecture, MSI domain will be inherited from the root
 132 bridge, and all of the devices will share the same MSI domain.
 133 Hence that, the PCIe devices will not work properly if the irq number
 134 which required is more than 32.
 135
 136 Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
 137 comply with the hardware design.
 138
 139 Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
 140 ---
 141  .../bindings/pci/mediatek-pcie-cfg.yaml       |  38 +++++
 142  .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
 143  2 files changed, 129 insertions(+), 53 deletions(-)
 144  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
 145
 146 --- /dev/null
 147 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
 148 @@ -0,0 +1,38 @@
 149 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 150 +%YAML 1.2
 151 +---
 152 +$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
 153 +$schema: http://devicetree.org/meta-schemas/core.yaml#
 154 +
 155 +title: Mediatek PCIECFG controller
 156 +
 157 +maintainers:
 158 +  - Chuanjia Liu <chuanjia.liu@mediatek.com>
 159 +  - Jianjun Wang <jianjun.wang@mediatek.com>
 160 +
 161 +description: |
 162 +  The MediaTek PCIECFG controller controls some feature about
 163 +  LTSSM, ASPM and so on.
 164 +
 165 +properties:
 166 +  compatible:
 167 +      items:
 168 +        - enum:
 169 +            - mediatek,mt7622-pciecfg
 170 +            - mediatek,mt7629-pciecfg
 171 +        - const: syscon
 172 +
 173 +  reg:
 174 +    maxItems: 1
 175 +
 176 +required:
 177 +  - compatible
 178 +  - reg
 179 +
 180 +examples:
 181 +  - |
 182 +    pciecfg: pciecfg@1a140000 {
 183 +        compatible = "mediatek,mt7622-pciecfg", "syscon";
 184 +        reg = <0 0x1a140000 0 0x1000>;
 185 +    };
 186 +...
 187 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 188 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 189 @@ -8,7 +8,7 @@ Required properties:
 190         "mediatek,mt7623-pcie"
 191         "mediatek,mt7629-pcie"
 192  - device_type: Must be "pci"
 193 -- reg: Base addresses and lengths of the PCIe subsys and root ports.
 194 +- reg: Base addresses and lengths of the root ports.
 195  - reg-names: Names of the above areas to use during resource lookup.
 196  - #address-cells: Address representation for root ports (must be 3)
 197  - #size-cells: Size representation for root ports (must be 2)
 198 @@ -19,10 +19,10 @@ Required properties:
 199     - sys_ckN :transaction layer and data link layer clock
 200    Required entries for MT2701/MT7623:
 201     - free_ck :for reference clock of PCIe subsys
 202 -  Required entries for MT2712/MT7622:
 203 +  Required entries for MT2712/MT7622/MT7629:
 204     - ahb_ckN :AHB slave interface operating clock for CSR access and RC
 205               initiated MMIO access
 206 -  Required entries for MT7622:
 207 +  Required entries for MT7622/MT7629:
 208     - axi_ckN :application layer MMIO channel operating clock
 209     - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
 210               pcie_mac_ck/pcie_pipe_ck is turned off
 211 @@ -47,10 +47,13 @@ Required properties for MT7623/MT2701:
 212  - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
 213    number of root ports.
 214
 215 -Required properties for MT2712/MT7622:
 216 +Required properties for MT2712/MT7622/MT7629:
 217  -interrupts: A list of interrupt outputs of the controller, must have one
 218              entry for each PCIe port
 219
 220 +Required properties for MT7622/MT7629:
 221 +- mediatek,pcie-subsys: Should be a phandle of the pciecfg node.
 222 +
 223  In addition, the device tree node must have sub-nodes describing each
 224  PCIe port interface, having the following mandatory properties:
 225
 226 @@ -143,56 +146,73 @@ Examples for MT7623:
 227
 228  Examples for MT2712:
 229
 230 -       pcie: pcie@11700000 {
 231 +       pcie1: pcie@112ff000 {
 232                 compatible = "mediatek,mt2712-pcie";
 233                 device_type = "pci";
 234 -               reg = <0 0x11700000 0 0x1000>,
 235 -                     <0 0x112ff000 0 0x1000>;
 236 -               reg-names = "port0", "port1";
 237 +               reg = <0 0x112ff000 0 0x1000>;
 238 +               reg-names = "port1";
 239                 #address-cells = <3>;
 240                 #size-cells = <2>;
 241 -               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 242 -                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 243 -               clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 244 -                        <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 245 -                        <&pericfg CLK_PERI_PCIE0>,
 246 +               interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 247 +               interrupt-names = "pcie_irq";
 248 +               clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 249                          <&pericfg CLK_PERI_PCIE1>;
 250 -               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
 251 -               phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
 252 -               phy-names = "pcie-phy0", "pcie-phy1";
 253 +               clock-names = "sys_ck1", "ahb_ck1";
 254 +               phys = <&u3port1 PHY_TYPE_PCIE>;
 255 +               phy-names = "pcie-phy1";
 256                 bus-range = <0x00 0xff>;
 257 -               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 258 +               ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
 259 +               status = "disabled";
 260
 261 -               pcie0: pcie@0,0 {
 262 -                       reg = <0x0000 0 0 0 0>;
 263 +               slot1: pcie@1,0 {
 264 +                       reg = <0x0800 0 0 0 0>;
 265                         #address-cells = <3>;
 266                         #size-cells = <2>;
 267                         #interrupt-cells = <1>;
 268                         ranges;
 269                         interrupt-map-mask = <0 0 0 7>;
 270 -                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 271 -                                       <0 0 0 2 &pcie_intc0 1>,
 272 -                                       <0 0 0 3 &pcie_intc0 2>,
 273 -                                       <0 0 0 4 &pcie_intc0 3>;
 274 -                       pcie_intc0: interrupt-controller {
 275 +                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 276 +                                       <0 0 0 2 &pcie_intc1 1>,
 277 +                                       <0 0 0 3 &pcie_intc1 2>,
 278 +                                       <0 0 0 4 &pcie_intc1 3>;
 279 +                       pcie_intc1: interrupt-controller {
 280                                 interrupt-controller;
 281                                 #address-cells = <0>;
 282                                 #interrupt-cells = <1>;
 283                         };
 284                 };
 285 +       };
 286
 287 -               pcie1: pcie@1,0 {
 288 -                       reg = <0x0800 0 0 0 0>;
 289 +       pcie0: pcie@11700000 {
 290 +               compatible = "mediatek,mt2712-pcie";
 291 +               device_type = "pci";
 292 +               reg = <0 0x11700000 0 0x1000>;
 293 +               reg-names = "port0";
 294 +               #address-cells = <3>;
 295 +               #size-cells = <2>;
 296 +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 297 +               interrupt-names = "pcie_irq";
 298 +               clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 299 +                        <&pericfg CLK_PERI_PCIE0>;
 300 +               clock-names = "sys_ck0", "ahb_ck0";
 301 +               phys = <&u3port0 PHY_TYPE_PCIE>;
 302 +               phy-names = "pcie-phy0";
 303 +               bus-range = <0x00 0xff>;
 304 +               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 305 +               status = "disabled";
 306 +
 307 +               slot0: pcie@0,0 {
 308 +                       reg = <0x0000 0 0 0 0>;
 309                         #address-cells = <3>;
 310                         #size-cells = <2>;
 311                         #interrupt-cells = <1>;
 312                         ranges;
 313                         interrupt-map-mask = <0 0 0 7>;
 314 -                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 315 -                                       <0 0 0 2 &pcie_intc1 1>,
 316 -                                       <0 0 0 3 &pcie_intc1 2>,
 317 -                                       <0 0 0 4 &pcie_intc1 3>;
 318 -                       pcie_intc1: interrupt-controller {
 319 +                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 320 +                                       <0 0 0 2 &pcie_intc0 1>,
 321 +                                       <0 0 0 3 &pcie_intc0 2>,
 322 +                                       <0 0 0 4 &pcie_intc0 3>;
 323 +                       pcie_intc0: interrupt-controller {
 324                                 interrupt-controller;
 325                                 #address-cells = <0>;
 326                                 #interrupt-cells = <1>;
 327 @@ -202,39 +222,31 @@ Examples for MT2712:
 328
 329  Examples for MT7622:
 330
 331 -       pcie: pcie@1a140000 {
 332 +       pcie0: pcie@1a143000 {
 333                 compatible = "mediatek,mt7622-pcie";
 334                 device_type = "pci";
 335 -               reg = <0 0x1a140000 0 0x1000>,
 336 -                     <0 0x1a143000 0 0x1000>,
 337 -                     <0 0x1a145000 0 0x1000>;
 338 -               reg-names = "subsys", "port0", "port1";
 339 +               reg = <0 0x1a143000 0 0x1000>;
 340 +               reg-names = "port0";
 341 +               mediatek,pcie-cfg = <&pciecfg>;
 342                 #address-cells = <3>;
 343                 #size-cells = <2>;
 344 -               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 345 -                            <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 346 +               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
 347 +               interrupt-names = "pcie_irq";
 348                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 349 -                        <&pciesys CLK_PCIE_P1_MAC_EN>,
 350                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 351 -                        <&pciesys CLK_PCIE_P1_AHB_EN>,
 352                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 353 -                        <&pciesys CLK_PCIE_P1_AUX_EN>,
 354                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 355 -                        <&pciesys CLK_PCIE_P1_AXI_EN>,
 356                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 357 -                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
 358 -                        <&pciesys CLK_PCIE_P0_PIPE_EN>,
 359 -                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
 360 -               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 361 -                             "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 362 -                             "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 363 -               phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
 364 -               phy-names = "pcie-phy0", "pcie-phy1";
 365 +                        <&pciesys CLK_PCIE_P0_PIPE_EN>;
 366 +               clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
 367 +                             "axi_ck0", "obff_ck0", "pipe_ck0";
 368 +
 369                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 370                 bus-range = <0x00 0xff>;
 371 -               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 372 +               ranges = <0x82000000 0 0x20000000  0 0x20000000  0 0x8000000>;
 373 +               status = "disabled";
 374
 375 -               pcie0: pcie@0,0 {
 376 +               slot0: pcie@0,0 {
 377                         reg = <0x0000 0 0 0 0>;
 378                         #address-cells = <3>;
 379                         #size-cells = <2>;
 380 @@ -251,8 +263,34 @@ Examples for MT7622:
 381                                 #interrupt-cells = <1>;
 382                         };
 383                 };
 384 +       };
 385
 386 -               pcie1: pcie@1,0 {
 387 +       pcie1: pcie@1a145000 {
 388 +               compatible = "mediatek,mt7622-pcie";
 389 +               device_type = "pci";
 390 +               reg = <0 0x1a145000 0 0x1000>;
 391 +               reg-names = "port1";
 392 +               mediatek,pcie-cfg = <&pciecfg>;
 393 +               #address-cells = <3>;
 394 +               #size-cells = <2>;
 395 +               interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 396 +               interrupt-names = "pcie_irq";
 397 +               clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 398 +                        /* designer has connect RC1 with p0_ahb clock */
 399 +                        <&pciesys CLK_PCIE_P0_AHB_EN>,
 400 +                        <&pciesys CLK_PCIE_P1_AUX_EN>,
 401 +                        <&pciesys CLK_PCIE_P1_AXI_EN>,
 402 +                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
 403 +                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
 404 +               clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
 405 +                             "axi_ck1", "obff_ck1", "pipe_ck1";
 406 +
 407 +               power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 408 +               bus-range = <0x00 0xff>;
 409 +               ranges = <0x82000000 0 0x28000000  0 0x28000000  0 0x8000000>;
 410 +               status = "disabled";
 411 +
 412 +               slot1: pcie@1,0 {
 413                         reg = <0x0800 0 0 0 0>;
 414                         #address-cells = <3>;
 415                         #size-cells = <2>;