target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch

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  71 From: <chuanjia.liu@mediatek.com>
  72 To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
  73 Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
  74  MT2712/MT7622
  75 Date: Thu, 28 May 2020 14:16:47 +0800
  76 Message-ID: <20200528061648.32078-4-chuanjia.liu@mediatek.com>
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 105 X-BeenThere: linux-mediatek@lists.infradead.org
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 114 List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mediatek>,
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 116 Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
 117  srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
 118  linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
 119  jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
 120  yong.wu@mediatek.com, bhelgaas@google.com,
 121  linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
 122 Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
 123 Errors-To:
 124  linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
 125
 126 From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
 127
 128 There are two independent PCIe controllers in MT2712/MT7622 platform,
 129 and each of them should contain an independent MSI domain.
 130
 131 In current architecture, MSI domain will be inherited from the root
 132 bridge, and all of the devices will share the same MSI domain.
 133 Hence that, the PCIe devices will not work properly if the irq number
 134 which required is more than 32.
 135
 136 Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
 137 comply with the hardware design.
 138
 139 Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
 140 ---
 141  arch/arm64/boot/dts/mediatek/mt2712e.dtsi     | 75 +++++++++++--------
 142  .../dts/mediatek/mt7622-bananapi-bpi-r64.dts  | 16 ++--
 143  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts  |  6 +-
 144  arch/arm64/boot/dts/mediatek/mt7622.dtsi      | 68 +++++++++++------
 145  4 files changed, 96 insertions(+), 69 deletions(-)
 146
 147 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
 148 +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
 149 @@ -791,60 +791,73 @@
 150                 };
 151         };
 152
 153 -       pcie: pcie@11700000 {
 154 +       pcie1: pcie@112ff000 {
 155                 compatible = "mediatek,mt2712-pcie";
 156                 device_type = "pci";
 157 -               reg = <0 0x11700000 0 0x1000>,
 158 -                     <0 0x112ff000 0 0x1000>;
 159 -               reg-names = "port0", "port1";
 160 +               reg = <0 0x112ff000 0 0x1000>;
 161 +               reg-names = "port1";
 162                 #address-cells = <3>;
 163                 #size-cells = <2>;
 164 -               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 165 -                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 166 -               clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 167 -                        <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 168 -                        <&pericfg CLK_PERI_PCIE0>,
 169 +               interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 170 +               interrupt-names = "pcie_irq";
 171 +               clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 172                          <&pericfg CLK_PERI_PCIE1>;
 173 -               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
 174 -               phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
 175 -               phy-names = "pcie-phy0", "pcie-phy1";
 176 +               clock-names = "sys_ck1", "ahb_ck1";
 177 +               phys = <&u3port1 PHY_TYPE_PCIE>;
 178 +               phy-names = "pcie-phy1";
 179                 bus-range = <0x00 0xff>;
 180 -               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 181 +               ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
 182 +               status = "disabled";
 183
 184 -               pcie0: pcie@0,0 {
 185 -                       device_type = "pci";
 186 -                       status = "disabled";
 187 -                       reg = <0x0000 0 0 0 0>;
 188 +               slot1: pcie@1,0 {
 189 +                       reg = <0x0800 0 0 0 0>;
 190                         #address-cells = <3>;
 191                         #size-cells = <2>;
 192                         #interrupt-cells = <1>;
 193                         ranges;
 194                         interrupt-map-mask = <0 0 0 7>;
 195 -                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 196 -                                       <0 0 0 2 &pcie_intc0 1>,
 197 -                                       <0 0 0 3 &pcie_intc0 2>,
 198 -                                       <0 0 0 4 &pcie_intc0 3>;
 199 -                       pcie_intc0: interrupt-controller {
 200 +                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 201 +                                       <0 0 0 2 &pcie_intc1 1>,
 202 +                                       <0 0 0 3 &pcie_intc1 2>,
 203 +                                       <0 0 0 4 &pcie_intc1 3>;
 204 +                       pcie_intc1: interrupt-controller {
 205                                 interrupt-controller;
 206                                 #address-cells = <0>;
 207                                 #interrupt-cells = <1>;
 208                         };
 209                 };
 210 +       };
 211
 212 -               pcie1: pcie@1,0 {
 213 -                       device_type = "pci";
 214 -                       status = "disabled";
 215 -                       reg = <0x0800 0 0 0 0>;
 216 +       pcie0: pcie@11700000 {
 217 +               compatible = "mediatek,mt2712-pcie";
 218 +               device_type = "pci";
 219 +               reg = <0 0x11700000 0 0x1000>;
 220 +               reg-names = "port0";
 221 +               #address-cells = <3>;
 222 +               #size-cells = <2>;
 223 +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 224 +               interrupt-names = "pcie_irq";
 225 +               clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 226 +                        <&pericfg CLK_PERI_PCIE0>;
 227 +               clock-names = "sys_ck0", "ahb_ck0";
 228 +               phys = <&u3port0 PHY_TYPE_PCIE>;
 229 +               phy-names = "pcie-phy0";
 230 +               bus-range = <0x00 0xff>;
 231 +               ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 232 +               status = "disabled";
 233 +
 234 +               slot0: pcie@0,0 {
 235 +                       reg = <0x0000 0 0 0 0>;
 236                         #address-cells = <3>;
 237                         #size-cells = <2>;
 238                         #interrupt-cells = <1>;
 239                         ranges;
 240                         interrupt-map-mask = <0 0 0 7>;
 241 -                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 242 -                                       <0 0 0 2 &pcie_intc1 1>,
 243 -                                       <0 0 0 3 &pcie_intc1 2>,
 244 -                                       <0 0 0 4 &pcie_intc1 3>;
 245 -                       pcie_intc1: interrupt-controller {
 246 +                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 247 +                                       <0 0 0 2 &pcie_intc0 1>,
 248 +                                       <0 0 0 3 &pcie_intc0 2>,
 249 +                                       <0 0 0 4 &pcie_intc0 3>;
 250 +                       pcie_intc0: interrupt-controller {
 251                                 interrupt-controller;
 252                                 #address-cells = <0>;
 253                                 #interrupt-cells = <1>;
 254 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 255 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 256 @@ -294,18 +294,16 @@
 257         };
 258  };
 259
 260 -&pcie {
 261 +&pcie0 {
 262         pinctrl-names = "default";
 263 -       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 264 +       pinctrl-0 = <&pcie0_pins>;
 265         status = "okay";
 266 +};
 267
 268 -       pcie@0,0 {
 269 -               status = "okay";
 270 -       };
 271 -
 272 -       pcie@1,0 {
 273 -               status = "okay";
 274 -       };
 275 +&pcie1 {
 276 +       pinctrl-names = "default";
 277 +       pinctrl-0 = <&pcie1_pins>;
 278 +       status = "okay";
 279  };
 280
 281  &pio {
 282 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 283 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 284 @@ -792,45 +792,41 @@
 285                 #reset-cells = <1>;
 286         };
 287
 288 -       pcie: pcie@1a140000 {
 289 +       pciecfg: pciecfg@1a140000 {
 290 +               compatible = "mediatek,mt7622-pciecfg", "syscon";
 291 +               reg = <0 0x1a140000 0 0x1000>;
 292 +       };
 293 +
 294 +       pcie0: pcie@1a143000 {
 295                 compatible = "mediatek,mt7622-pcie";
 296                 device_type = "pci";
 297 -               reg = <0 0x1a140000 0 0x1000>,
 298 -                     <0 0x1a143000 0 0x1000>,
 299 -                     <0 0x1a145000 0 0x1000>;
 300 -               reg-names = "subsys", "port0", "port1";
 301 +               reg = <0 0x1a143000 0 0x1000>;
 302 +               reg-names = "port0";
 303 +               mediatek,pcie-cfg = <&pciecfg>;
 304                 #address-cells = <3>;
 305                 #size-cells = <2>;
 306 -               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 307 -                            <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 308 +               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
 309 +               interrupt-names = "pcie_irq";
 310                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 311 -                        <&pciesys CLK_PCIE_P1_MAC_EN>,
 312 -                        <&pciesys CLK_PCIE_P0_AHB_EN>,
 313                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 314                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 315 -                        <&pciesys CLK_PCIE_P1_AUX_EN>,
 316                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 317 -                        <&pciesys CLK_PCIE_P1_AXI_EN>,
 318                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 319 -                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
 320 -                        <&pciesys CLK_PCIE_P0_PIPE_EN>,
 321 -                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
 322 -               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 323 -                             "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 324 -                             "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 325 +                        <&pciesys CLK_PCIE_P0_PIPE_EN>;
 326 +               clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
 327 +                             "axi_ck0", "obff_ck0", "pipe_ck0";
 328 +
 329                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 330                 bus-range = <0x00 0xff>;
 331 -               ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 332 +               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;
 333                 status = "disabled";
 334
 335 -               pcie0: pcie@0,0 {
 336 +               slot0: pcie@0,0 {
 337                         reg = <0x0000 0 0 0 0>;
 338                         #address-cells = <3>;
 339                         #size-cells = <2>;
 340                         #interrupt-cells = <1>;
 341                         ranges;
 342 -                       status = "disabled";
 343 -
 344                         interrupt-map-mask = <0 0 0 7>;
 345                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 346                                         <0 0 0 2 &pcie_intc0 1>,
 347 @@ -842,15 +838,39 @@
 348                                 #interrupt-cells = <1>;
 349                         };
 350                 };
 351 +       };
 352
 353 -               pcie1: pcie@1,0 {
 354 +       pcie1: pcie@1a145000 {
 355 +               compatible = "mediatek,mt7622-pcie";
 356 +               device_type = "pci";
 357 +               reg = <0 0x1a145000 0 0x1000>;
 358 +               reg-names = "port1";
 359 +               mediatek,pcie-cfg = <&pciecfg>;
 360 +               #address-cells = <3>;
 361 +               #size-cells = <2>;
 362 +               interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 363 +               interrupt-names = "pcie_irq";
 364 +               clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 365 +                        /* designer has connect RC1 with p0_ahb clock */
 366 +                        <&pciesys CLK_PCIE_P0_AHB_EN>,
 367 +                        <&pciesys CLK_PCIE_P1_AUX_EN>,
 368 +                        <&pciesys CLK_PCIE_P1_AXI_EN>,
 369 +                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
 370 +                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
 371 +               clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
 372 +                             "axi_ck1", "obff_ck1", "pipe_ck1";
 373 +
 374 +               power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 375 +               bus-range = <0x00 0xff>;
 376 +               ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;
 377 +               status = "disabled";
 378 +
 379 +               slot1: pcie@1,0 {
 380                         reg = <0x0800 0 0 0 0>;
 381                         #address-cells = <3>;
 382                         #size-cells = <2>;
 383                         #interrupt-cells = <1>;
 384                         ranges;
 385 -                       status = "disabled";
 386 -
 387                         interrupt-map-mask = <0 0 0 7>;
 388                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 389                                         <0 0 0 2 &pcie_intc1 1>,
 390 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 391 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 392 @@ -256,18 +256,16 @@
 393         };
 394  };
 395
 396 -&pcie {
 397 +&pcie0 {
 398         pinctrl-names = "default";
 399 -       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 400 +       pinctrl-0 = <&pcie0_pins>;
 401         status = "okay";
 402 +};
 403
 404 -       pcie@0,0 {
 405 -               status = "okay";
 406 -       };
 407 -
 408 -       pcie@1,0 {
 409 -               status = "okay";
 410 -       };
 411 +&pcie1 {
 412 +       pinctrl-names = "default";
 413 +       pinctrl-0 = <&pcie1_pins>;
 414 +       status = "okay";
 415  };
 416
 417  &pio {