target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch

   1 From d83532fe7eb9cc7b8cc39dd9f2bbd9873d4e390b Mon Sep 17 00:00:00 2001
   2 From: "pi-cheng.chen" <pi-cheng.chen@linaro.org>
   3 Date: Mon, 8 Jun 2015 20:29:20 +0800
   4 Subject: [PATCH 32/76] dt-bindings: mediatek: Add MT8173 cpufreq driver
   5  binding
   6
   7 This patch adds device tree binding document for MT8173 cpufreq driver.
   8
   9 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  10 ---
  11  .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt |  127 ++++++++++++++++++++
  12  1 file changed, 127 insertions(+)
  13  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
  14
  15 --- /dev/null
  16 +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
  17 @@ -0,0 +1,127 @@
  18 +
  19 +Mediatek MT8173 cpufreq driver
  20 +-------------------
  21 +
  22 +Mediatek MT8173 cpufreq driver for CPU frequency scaling.
  23 +
  24 +Required properties:
  25 +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
  26 +- clock-names: Should contain the following:
  27 +       "cpu"           - The multiplexer for clock input of CPU cluster.
  28 +       "intermediate"  - A parent of "cpu" clock which is used as "intermediate" clock
  29 +                         source (usually MAINPLL) when the original CPU PLL is under
  30 +                         transition and not stable yet.
  31 +- operating-points: Table of frequencies and voltage CPU could be transitioned into,
  32 +                   Frequency should be in KHz units and voltage should be in microvolts.
  33 +- proc-supply: Regulator for Vproc of CPU cluster.
  34 +
  35 +Optional properties:
  36 +- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
  37 +              needs to do "voltage trace" to step by step scale up/down Vproc and
  38 +              Vsram to fit SoC specific needs. When absent, the voltage scaling
  39 +              flow is handled by hardware, hence no software "voltage trace" is
  40 +              needed.
  41 +
  42 +Example:
  43 +--------
  44 +       cpu0: cpu@0 {
  45 +               device_type = "cpu";
  46 +               compatible = "arm,cortex-a53";
  47 +               reg = <0x000>;
  48 +               enable-method = "psci";
  49 +               cpu-idle-states = <&CPU_SLEEP_0>;
  50 +               clocks = <&infracfg CLK_INFRA_CA53SEL>,
  51 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
  52 +               clock-names = "cpu", "intermediate";
  53 +               operating-points = <
  54 +                       507000  859000
  55 +                       702000  908000
  56 +                       1001000 983000
  57 +                       1105000 1009000
  58 +                       1183000 1028000
  59 +                       1404000 1083000
  60 +                       1508000 1109000
  61 +                       1573000 1125000
  62 +               >;
  63 +       };
  64 +
  65 +       cpu1: cpu@1 {
  66 +               device_type = "cpu";
  67 +               compatible = "arm,cortex-a53";
  68 +               reg = <0x001>;
  69 +               enable-method = "psci";
  70 +               cpu-idle-states = <&CPU_SLEEP_0>;
  71 +               clocks = <&infracfg CLK_INFRA_CA53SEL>,
  72 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
  73 +               clock-names = "cpu", "intermediate";
  74 +               operating-points = <
  75 +                       507000  859000
  76 +                       702000  908000
  77 +                       1001000 983000
  78 +                       1105000 1009000
  79 +                       1183000 1028000
  80 +                       1404000 1083000
  81 +                       1508000 1109000
  82 +                       1573000 1125000
  83 +               >;
  84 +       };
  85 +
  86 +       cpu2: cpu@100 {
  87 +               device_type = "cpu";
  88 +               compatible = "arm,cortex-a57";
  89 +               reg = <0x100>;
  90 +               enable-method = "psci";
  91 +               cpu-idle-states = <&CPU_SLEEP_0>;
  92 +               clocks = <&infracfg CLK_INFRA_CA57SEL>,
  93 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
  94 +               clock-names = "cpu", "intermediate";
  95 +               operating-points = <
  96 +                       507000  828000
  97 +                       702000  867000
  98 +                       1001000 927000
  99 +                       1209000 968000
 100 +                       1404000 1007000
 101 +                       1612000 1049000
 102 +                       1807000 1089000
 103 +                       1989000 1125000
 104 +               >;
 105 +       };
 106 +
 107 +       cpu3: cpu@101 {
 108 +               device_type = "cpu";
 109 +               compatible = "arm,cortex-a57";
 110 +               reg = <0x101>;
 111 +               enable-method = "psci";
 112 +               cpu-idle-states = <&CPU_SLEEP_0>;
 113 +               clocks = <&infracfg CLK_INFRA_CA57SEL>,
 114 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
 115 +               clock-names = "cpu", "intermediate";
 116 +               operating-points = <
 117 +                       507000  828000
 118 +                       702000  867000
 119 +                       1001000 927000
 120 +                       1209000 968000
 121 +                       1404000 1007000
 122 +                       1612000 1049000
 123 +                       1807000 1089000
 124 +                       1989000 1125000
 125 +               >;
 126 +       };
 127 +
 128 +       &cpu0 {
 129 +               proc-supply = <&mt6397_vpca15_reg>;
 130 +       };
 131 +
 132 +       &cpu1 {
 133 +               proc-supply = <&mt6397_vpca15_reg>;
 134 +       };
 135 +
 136 +       &cpu2 {
 137 +               proc-supply = <&da9211_vcpu_reg>;
 138 +               sram-supply = <&mt6397_vsramca7_reg>;
 139 +       };
 140 +
 141 +       &cpu3 {
 142 +               proc-supply = <&da9211_vcpu_reg>;
 143 +               sram-supply = <&mt6397_vsramca7_reg>;
 144 +       };