target/linux/mediatek/patches/0067-arm-mediatek-add-mt7623-support.patch

   1 From 89556b1a4d98fbfe498c8f26e988cbb8266f7dfe Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Jun 2015 13:17:35 +0200
   4 Subject: [PATCH 67/76] arm: mediatek: add mt7623 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/arm/mach-mediatek/Kconfig                     |    6 ++
   9  arch/arm/mach-mediatek/mediatek.c                  |    2 +
  10  .../dt-bindings/reset-controller/mt7623-resets.h   |   59 ++++++++++++++++++++
  11  3 files changed, 67 insertions(+)
  12  create mode 100644 include/dt-bindings/reset-controller/mt7623-resets.h
  13
  14 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
  15 index 7704818..5393d25 100644
  16 --- a/arch/arm/mach-mediatek/Kconfig
  17 +++ b/arch/arm/mach-mediatek/Kconfig
  18 @@ -17,6 +17,12 @@ config MACH_MT6592
  19         bool "MediaTek MT6592 SoCs support"
  20         default ARCH_MEDIATEK
  21
  22 +config MACH_MT7623
  23 +       bool "MediaTek MT7623 SoCs support"
  24 +       default ARCH_MEDIATEK
  25 +       select ARCH_HAS_PCI
  26 +       select PCI
  27 +
  28  config MACH_MT8127
  29         bool "MediaTek MT8127 SoCs support"
  30         default ARCH_MEDIATEK
  31 diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
  32 index 6b38d67..ab8cf21 100644
  33 --- a/arch/arm/mach-mediatek/mediatek.c
  34 +++ b/arch/arm/mach-mediatek/mediatek.c
  35 @@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
  36         void __iomem *gpt_base = 0;
  37
  38         if (of_machine_is_compatible("mediatek,mt6589") ||
  39 +           of_machine_is_compatible("mediatek,mt7623") ||
  40             of_machine_is_compatible("mediatek,mt8135") ||
  41             of_machine_is_compatible("mediatek,mt8127")) {
  42                 /* turn on GPT6 which ungates arch timer clocks */
  43 @@ -48,6 +49,7 @@ static void __init mediatek_timer_init(void)
  44  static const char * const mediatek_board_dt_compat[] = {
  45         "mediatek,mt6589",
  46         "mediatek,mt6592",
  47 +       "mediatek,mt7623",
  48         "mediatek,mt8127",
  49         "mediatek,mt8135",
  50         NULL,
  51 diff --git a/include/dt-bindings/reset-controller/mt7623-resets.h b/include/dt-bindings/reset-controller/mt7623-resets.h
  52 new file mode 100644
  53 index 0000000..28a7d69
  54 --- /dev/null
  55 +++ b/include/dt-bindings/reset-controller/mt7623-resets.h
  56 @@ -0,0 +1,59 @@
  57 +/*
  58 + * Copyright (c) 2015 OpenWrt
  59 + * Author: John Crispin
  60 + *
  61 + * This program is free software; you can redistribute it and/or modify
  62 + * it under the terms of the GNU General Public License version 2 as
  63 + * published by the Free Software Foundation.
  64 + *
  65 + * This program is distributed in the hope that it will be useful,
  66 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  67 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  68 + * GNU General Public License for more details.
  69 + */
  70 +
  71 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7623
  72 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7623
  73 +
  74 +/* INFRACFG resets */
  75 +#define MT7623_INFRA_EMI_REG_RST       0
  76 +#define MT7623_INFRA_DRAMC0_A0_RST     1
  77 +#define MT7623_INFRA_FHCTL_RST         2
  78 +#define MT7623_INFRA_APCIRQ_EINT_RST   3
  79 +#define MT7623_INFRA_APXGPT_RST                4
  80 +#define MT7623_INFRA_SCPSYS_RST                5
  81 +#define MT7623_INFRA_KP_RST            6
  82 +#define MT7623_INFRA_PMIC_WRAP_RST     7
  83 +#define MT7623_INFRA_MIPI_RST          8
  84 +#define MT7623_INFRA_IRRX_RST          9
  85 +#define MT7623_INFRA_CEC_RST           10
  86 +#define MT7623_INFRA_EMI_RST           32
  87 +#define MT7623_INFRA_DRAMC0_RST                34
  88 +#define MT7623_INFRA_SMI_RST           37
  89 +#define MT7623_INFRA_M4U_RST           38
  90 +
  91 +/* PERICFG resets */
  92 +#define MT7623_PERI_UART0_SW_RST       0
  93 +#define MT7623_PERI_UART1_SW_RST       1
  94 +#define MT7623_PERI_UART2_SW_RST       2
  95 +#define MT7623_PERI_UART3_SW_RST       3
  96 +#define MT7623_PERI_GCPU_SW_RST                5
  97 +#define MT7623_PERI_BTIF_SW_RST                6
  98 +#define MT7623_PERI_PWM_SW_RST         8
  99 +#define MT7623_PERI_AUXADC_SW_RST      10
 100 +#define MT7623_PERI_DMA_SW_RST         11
 101 +#define MT7623_PERI_NFI_SW_RST         14
 102 +#define MT7623_PERI_NLI_SW_RST         15
 103 +#define MT7623_PERI_THERM_SW_RST       16
 104 +#define MT7623_PERI_MSDC0_SW_RST       17
 105 +#define MT7623_PERI_MSDC1_SW_RST       19
 106 +#define MT7623_PERI_MSDC2_SW_RST       20
 107 +#define MT7623_PERI_I2C0_SW_RST                22
 108 +#define MT7623_PERI_I2C1_SW_RST                23
 109 +#define MT7623_PERI_I2C2_SW_RST                24
 110 +#define MT7623_PERI_I2C3_SW_RST                25
 111 +#define MT7623_PERI_USB_SW_RST         28
 112 +#define MT7623_PERI_ETH_SW_RST         29
 113 +#define MT7623_PERI_SPI0_SW_RST                33
 114 +
 115 +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7623 */
 116 --
 117 1.7.10.4
 118