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base-files: define yes/no as valid boolean options
[openwrt/openwrt.git] / target / linux / mvebu / patches-3.10 / 0151-mtd-nand-pxa3xx-Introduce-multiple-page-I-O-support.patch
1 From cfd1799f9ec5c9820f371e1fcf2f3c458bd24ebb Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
3 Date: Thu, 14 Nov 2013 18:25:37 -0300
4 Subject: [PATCH 151/203] mtd: nand: pxa3xx: Introduce multiple page I/O
5 support
6
7 As preparation work to fully support large pages, this commit adds
8 the initial infrastructure to support splitted (aka chunked) I/O
9 operation. This commit adds support for read, and follow-up patches
10 will add write support.
11
12 When a read (aka READ0) command is issued, the driver loops issuing
13 the same command until all the requested data is transfered, changing
14 the 'extended' command field as needed.
15
16 For instance, if the driver is required to read a 4 KiB page, using a
17 chunk size of 2 KiB, the transaction is splitted in:
18 1. Monolithic read, first 2 KiB page chunk is read
19 2. Last naked read, second and last 2KiB page chunk is read
20
21 If ECC is enabled it is calculated on each chunk transfered and added
22 at a controller-fixed location after the data chunk that must be
23 spare area.
24
25 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
26 Tested-by: Daniel Mack <zonque@gmail.com>
27 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
28 ---
29 drivers/mtd/nand/pxa3xx_nand.c | 182 ++++++++++++++++++++++++++++++++++++++---
30 1 file changed, 172 insertions(+), 10 deletions(-)
31
32 --- a/drivers/mtd/nand/pxa3xx_nand.c
33 +++ b/drivers/mtd/nand/pxa3xx_nand.c
34 @@ -103,6 +103,8 @@
35 #define NDCB0_ST_ROW_EN (0x1 << 26)
36 #define NDCB0_AUTO_RS (0x1 << 25)
37 #define NDCB0_CSEL (0x1 << 24)
38 +#define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
39 +#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
40 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
41 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
42 #define NDCB0_NC (0x1 << 20)
43 @@ -113,6 +115,14 @@
44 #define NDCB0_CMD1_MASK (0xff)
45 #define NDCB0_ADDR_CYC_SHIFT (16)
46
47 +#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
48 +#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
49 +#define EXT_CMD_TYPE_READ 4 /* Read */
50 +#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
51 +#define EXT_CMD_TYPE_FINAL 3 /* Final command */
52 +#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
53 +#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
54 +
55 /* macros for registers read/write */
56 #define nand_writel(info, off, val) \
57 __raw_writel((val), (info)->mmio_base + (off))
58 @@ -206,8 +216,8 @@ struct pxa3xx_nand_info {
59 int use_spare; /* use spare ? */
60 int need_wait;
61
62 - unsigned int fifo_size; /* max. data size in the FIFO */
63 unsigned int data_size; /* data to be read from FIFO */
64 + unsigned int chunk_size; /* split commands chunk size */
65 unsigned int oob_size;
66 unsigned int spare_size;
67 unsigned int ecc_size;
68 @@ -271,6 +281,31 @@ static struct nand_bbt_descr bbt_mirror_
69 .pattern = bbt_mirror_pattern
70 };
71
72 +static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
73 + .eccbytes = 64,
74 + .eccpos = {
75 + 32, 33, 34, 35, 36, 37, 38, 39,
76 + 40, 41, 42, 43, 44, 45, 46, 47,
77 + 48, 49, 50, 51, 52, 53, 54, 55,
78 + 56, 57, 58, 59, 60, 61, 62, 63,
79 + 96, 97, 98, 99, 100, 101, 102, 103,
80 + 104, 105, 106, 107, 108, 109, 110, 111,
81 + 112, 113, 114, 115, 116, 117, 118, 119,
82 + 120, 121, 122, 123, 124, 125, 126, 127},
83 + /* Bootrom looks in bytes 0 & 5 for bad blocks */
84 + .oobfree = { {6, 26}, { 64, 32} }
85 +};
86 +
87 +static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
88 + .eccbytes = 128,
89 + .eccpos = {
90 + 32, 33, 34, 35, 36, 37, 38, 39,
91 + 40, 41, 42, 43, 44, 45, 46, 47,
92 + 48, 49, 50, 51, 52, 53, 54, 55,
93 + 56, 57, 58, 59, 60, 61, 62, 63},
94 + .oobfree = { }
95 +};
96 +
97 /* Define a default flash type setting serve as flash detecting only */
98 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
99
100 @@ -433,7 +468,7 @@ static void disable_int(struct pxa3xx_na
101
102 static void handle_data_pio(struct pxa3xx_nand_info *info)
103 {
104 - unsigned int do_bytes = min(info->data_size, info->fifo_size);
105 + unsigned int do_bytes = min(info->data_size, info->chunk_size);
106
107 switch (info->state) {
108 case STATE_PIO_WRITING:
109 @@ -670,7 +705,7 @@ static void prepare_start_command(struct
110 }
111
112 static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
113 - uint16_t column, int page_addr)
114 + int ext_cmd_type, uint16_t column, int page_addr)
115 {
116 int addr_cycle, exec_cmd;
117 struct pxa3xx_nand_host *host;
118 @@ -703,9 +738,20 @@ static int prepare_set_command(struct px
119 if (command == NAND_CMD_READOOB)
120 info->buf_start += mtd->writesize;
121
122 - /* Second command setting for large pages */
123 - if (mtd->writesize >= PAGE_CHUNK_SIZE)
124 + /*
125 + * Multiple page read needs an 'extended command type' field,
126 + * which is either naked-read or last-read according to the
127 + * state.
128 + */
129 + if (mtd->writesize == PAGE_CHUNK_SIZE) {
130 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
131 + } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
132 + info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
133 + | NDCB0_LEN_OVRD
134 + | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
135 + info->ndcb3 = info->chunk_size +
136 + info->oob_size;
137 + }
138
139 set_command_address(info, mtd->writesize, column, page_addr);
140 break;
141 @@ -821,7 +867,8 @@ static void pxa3xx_nand_cmdfunc(struct m
142 prepare_start_command(info, command);
143
144 info->state = STATE_PREPARED;
145 - exec_cmd = prepare_set_command(info, command, column, page_addr);
146 + exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
147 +
148 if (exec_cmd) {
149 init_completion(&info->cmd_complete);
150 init_completion(&info->dev_ready);
151 @@ -839,6 +886,93 @@ static void pxa3xx_nand_cmdfunc(struct m
152 info->state = STATE_IDLE;
153 }
154
155 +static void armada370_nand_cmdfunc(struct mtd_info *mtd,
156 + const unsigned command,
157 + int column, int page_addr)
158 +{
159 + struct pxa3xx_nand_host *host = mtd->priv;
160 + struct pxa3xx_nand_info *info = host->info_data;
161 + int ret, exec_cmd, ext_cmd_type;
162 +
163 + /*
164 + * if this is a x16 device then convert the input
165 + * "byte" address into a "word" address appropriate
166 + * for indexing a word-oriented device
167 + */
168 + if (info->reg_ndcr & NDCR_DWIDTH_M)
169 + column /= 2;
170 +
171 + /*
172 + * There may be different NAND chip hooked to
173 + * different chip select, so check whether
174 + * chip select has been changed, if yes, reset the timing
175 + */
176 + if (info->cs != host->cs) {
177 + info->cs = host->cs;
178 + nand_writel(info, NDTR0CS0, info->ndtr0cs0);
179 + nand_writel(info, NDTR1CS0, info->ndtr1cs0);
180 + }
181 +
182 + /* Select the extended command for the first command */
183 + switch (command) {
184 + case NAND_CMD_READ0:
185 + case NAND_CMD_READOOB:
186 + ext_cmd_type = EXT_CMD_TYPE_MONO;
187 + break;
188 + default:
189 + ext_cmd_type = 0;
190 + }
191 +
192 + prepare_start_command(info, command);
193 +
194 + /*
195 + * Prepare the "is ready" completion before starting a command
196 + * transaction sequence. If the command is not executed the
197 + * completion will be completed, see below.
198 + *
199 + * We can do that inside the loop because the command variable
200 + * is invariant and thus so is the exec_cmd.
201 + */
202 + info->need_wait = 1;
203 + init_completion(&info->dev_ready);
204 + do {
205 + info->state = STATE_PREPARED;
206 + exec_cmd = prepare_set_command(info, command, ext_cmd_type,
207 + column, page_addr);
208 + if (!exec_cmd) {
209 + info->need_wait = 0;
210 + complete(&info->dev_ready);
211 + break;
212 + }
213 +
214 + init_completion(&info->cmd_complete);
215 + pxa3xx_nand_start(info);
216 +
217 + ret = wait_for_completion_timeout(&info->cmd_complete,
218 + CHIP_DELAY_TIMEOUT);
219 + if (!ret) {
220 + dev_err(&info->pdev->dev, "Wait time out!!!\n");
221 + /* Stop State Machine for next command cycle */
222 + pxa3xx_nand_stop(info);
223 + break;
224 + }
225 +
226 + /* Check if the sequence is complete */
227 + if (info->data_size == 0)
228 + break;
229 +
230 + if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
231 + /* Last read: issue a 'last naked read' */
232 + if (info->data_size == info->chunk_size)
233 + ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
234 + else
235 + ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
236 + }
237 + } while (1);
238 +
239 + info->state = STATE_IDLE;
240 +}
241 +
242 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
243 struct nand_chip *chip, const uint8_t *buf, int oob_required)
244 {
245 @@ -1019,13 +1153,14 @@ static int pxa3xx_nand_detect_config(str
246
247 if (ndcr & NDCR_PAGE_SZ) {
248 /* Controller's FIFO size */
249 - info->fifo_size = 2048;
250 + info->chunk_size = 2048;
251 host->read_id_bytes = 4;
252 } else {
253 - info->fifo_size = 512;
254 + info->chunk_size = 512;
255 host->read_id_bytes = 2;
256 }
257
258 + /* Set an initial chunk size */
259 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
260 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
261 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
262 @@ -1129,6 +1264,7 @@ static int pxa_ecc_init(struct pxa3xx_na
263 * is used with non-ONFI compliant devices.
264 */
265 if (page_size == 2048) {
266 + info->chunk_size = 2048;
267 info->spare_size = 40;
268 info->ecc_size = 24;
269 ecc->mode = NAND_ECC_HW;
270 @@ -1137,6 +1273,7 @@ static int pxa_ecc_init(struct pxa3xx_na
271 return 1;
272
273 } else if (page_size == 512) {
274 + info->chunk_size = 512;
275 info->spare_size = 8;
276 info->ecc_size = 8;
277 ecc->mode = NAND_ECC_HW;
278 @@ -1151,7 +1288,28 @@ static int armada370_ecc_init(struct pxa
279 struct nand_ecc_ctrl *ecc,
280 int strength, int page_size)
281 {
282 - /* Unimplemented yet */
283 + if (strength == 4 && page_size == 4096) {
284 + info->ecc_bch = 1;
285 + info->chunk_size = 2048;
286 + info->spare_size = 32;
287 + info->ecc_size = 32;
288 + ecc->mode = NAND_ECC_HW;
289 + ecc->size = info->chunk_size;
290 + ecc->layout = &ecc_layout_4KB_bch4bit;
291 + ecc->strength = 16;
292 + return 1;
293 +
294 + } else if (strength == 8 && page_size == 4096) {
295 + info->ecc_bch = 1;
296 + info->chunk_size = 1024;
297 + info->spare_size = 0;
298 + info->ecc_size = 32;
299 + ecc->mode = NAND_ECC_HW;
300 + ecc->size = info->chunk_size;
301 + ecc->layout = &ecc_layout_4KB_bch8bit;
302 + ecc->strength = 16;
303 + return 1;
304 + }
305 return 0;
306 }
307
308 @@ -1319,12 +1477,16 @@ static int alloc_nand_resource(struct pl
309 chip->controller = &info->controller;
310 chip->waitfunc = pxa3xx_nand_waitfunc;
311 chip->select_chip = pxa3xx_nand_select_chip;
312 - chip->cmdfunc = pxa3xx_nand_cmdfunc;
313 chip->read_word = pxa3xx_nand_read_word;
314 chip->read_byte = pxa3xx_nand_read_byte;
315 chip->read_buf = pxa3xx_nand_read_buf;
316 chip->write_buf = pxa3xx_nand_write_buf;
317 chip->options |= NAND_NO_SUBPAGE_WRITE;
318 +
319 + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
320 + chip->cmdfunc = armada370_nand_cmdfunc;
321 + else
322 + chip->cmdfunc = pxa3xx_nand_cmdfunc;
323 }
324
325 spin_lock_init(&chip->controller->lock);
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