2cb8a17f07c1cc0e6a3eb58cac0a642ce5c81221
[openwrt/openwrt.git] / target / linux / mvebu / patches-3.8 / 037-arm_mvebu_add_pcie_dt_a370.patch
1 The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
2 necessary Device Tree informations to make these interfaces availabel.
3
4 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
5 ---
6 arch/arm/boot/dts/armada-370.dtsi | 25 +++++++++++++++++++++++++
7 1 file changed, 25 insertions(+)
8
9 --- a/arch/arm/boot/dts/armada-370.dtsi
10 +++ b/arch/arm/boot/dts/armada-370.dtsi
11 @@ -153,5 +153,29 @@
12 clocks = <&coreclk 0>;
13 };
14
15 + pcie-controller {
16 + compatible = "marvell,armada-370-xp-pcie";
17 + status = "disabled";
18 + #address-cells = <1>;
19 + #size-cells = <1>;
20 + ranges = <0 0xd0040000 0x2000
21 + 0x2000 0xd0080000 0x2000>;
22 +
23 + pcie0@0xd0040000 {
24 + reg = <0x0 0x2000>;
25 + interrupts = <58>;
26 + clocks = <&gateclk 5>;
27 + status = "disabled";
28 + marvell,pcie-port = <0>;
29 + };
30 +
31 + pcie1@0xd0080000 {
32 + reg = <0x2000 0x2000>;
33 + interrupts = <62>;
34 + clocks = <&gateclk 9>;
35 + status = "disabled";
36 + marvell,pcie-port = <1>;
37 + };
38 + };
39 };
40 };