target/linux/mvebu/patches-5.4/402-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch

   1 From f4c7d053d7f77cd5c1a1ba7c7ce085ddba13d1d7 Mon Sep 17 00:00:00 2001
   2 From: Remi Pommarel <repk@triplefau.lt>
   3 Date: Wed, 22 May 2019 23:33:50 +0200
   4 Subject: [PATCH] PCI: aardvark: Wait for endpoint to be ready before training
   5  link
   6
   7 When configuring pcie reset pin from gpio (e.g. initially set by
   8 u-boot) to pcie function this pin goes low for a brief moment
   9 asserting the PERST# signal. Thus connected device enters fundamental
  10 reset process and link configuration can only begin after a minimal
  11 100ms delay (see [1]).
  12
  13 Because the pin configuration comes from the "default" pinctrl it is
  14 implicitly configured before the probe callback is called:
  15
  16 driver_probe_device()
  17   really_probe()
  18     ...
  19     pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset
  20                            function and PERST# is asserted */
  21     ...
  22     drv->probe()
  23
  24 [1] "PCI Express Base Specification", REV. 4.0
  25     PCI Express, February 19 2014, 6.6.1 Conventional Reset
  26
  27 Signed-off-by: Remi Pommarel <repk@triplefau.lt>
  28 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  29 Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  30 ---
  31  drivers/pci/controller/pci-aardvark.c | 8 ++++++++
  32  1 file changed, 8 insertions(+)
  33
  34 --- a/drivers/pci/controller/pci-aardvark.c
  35 +++ b/drivers/pci/controller/pci-aardvark.c
  36 @@ -337,6 +337,14 @@ static void advk_pcie_setup_hw(struct ad
  37         reg |= PIO_CTRL_ADDR_WIN_DISABLE;
  38         advk_writel(pcie, reg, PIO_CTRL);
  39
  40 +       /*
  41 +        * PERST# signal could have been asserted by pinctrl subsystem before
  42 +        * probe() callback has been called, making the endpoint going into
  43 +        * fundamental reset. As required by PCI Express spec a delay for at
  44 +        * least 100ms after such a reset before link training is needed.
  45 +        */
  46 +       msleep(PCI_PM_D3COLD_WAIT);
  47 +
  48         /* Start link training */
  49         reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
  50         reg |= PCIE_CORE_LINK_TRAINING;