target/linux/olpc/files/drivers/media/video/cafe_ccic-regs.h

   1 /*
   2  * Register definitions for the m88alp01 camera interface.  Offsets in bytes
   3  * as given in the spec.
   4  *
   5  * Copyright 2006 One Laptop Per Child Association, Inc.
   6  *
   7  * Written by Jonathan Corbet, corbet@lwn.net.
   8  *
   9  * This file may be distributed under the terms of the GNU General
  10  * Public License, version 2.
  11  */
  12 #define REG_Y0BAR       0x00
  13 #define REG_Y1BAR       0x04
  14 #define REG_Y2BAR       0x08
  15 /* ... */
  16
  17 #define REG_IMGPITCH    0x24    /* Image pitch register */
  18 #define   IMGP_YP_SHFT    2             /* Y pitch params */
  19 #define   IMGP_YP_MASK    0x00003ffc    /* Y pitch field */
  20 #define   IMGP_UVP_SHFT   18            /* UV pitch (planar) */
  21 #define   IMGP_UVP_MASK   0x3ffc0000
  22 #define REG_IRQSTATRAW  0x28    /* RAW IRQ Status */
  23 #define   IRQ_EOF0        0x00000001    /* End of frame 0 */
  24 #define   IRQ_EOF1        0x00000002    /* End of frame 1 */
  25 #define   IRQ_EOF2        0x00000004    /* End of frame 2 */
  26 #define   IRQ_SOF0        0x00000008    /* Start of frame 0 */
  27 #define   IRQ_SOF1        0x00000010    /* Start of frame 1 */
  28 #define   IRQ_SOF2        0x00000020    /* Start of frame 2 */
  29 #define   IRQ_OVERFLOW    0x00000040    /* FIFO overflow */
  30 #define   IRQ_TWSIW       0x00010000    /* TWSI (smbus) write */
  31 #define   IRQ_TWSIR       0x00020000    /* TWSI read */
  32 #define   IRQ_TWSIE       0x00040000    /* TWSI error */
  33 #define   TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
  34 #define   FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
  35 #define   ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
  36 #define REG_IRQMASK     0x2c    /* IRQ mask - same bits as IRQSTAT */
  37 #define REG_IRQSTAT     0x30    /* IRQ status / clear */
  38
  39 #define REG_IMGSIZE     0x34    /* Image size */
  40 #define  IMGSZ_V_MASK     0x1fff0000
  41 #define  IMGSZ_V_SHIFT    16
  42 #define  IMGSZ_H_MASK     0x00003fff
  43 #define REG_IMGOFFSET   0x38    /* IMage offset */
  44
  45 #define REG_CTRL0       0x3c    /* Control 0 */
  46 #define   C0_ENABLE       0x00000001    /* Makes the whole thing go */
  47
  48 /* Mask for all the format bits */
  49 #define   C0_DF_MASK      0x00fffffc    /* Bits 2-23 */
  50
  51 /* RGB ordering */
  52 #define   C0_RGB4_RGBX    0x00000000
  53 #define   C0_RGB4_XRGB    0x00000004
  54 #define   C0_RGB4_BGRX    0x00000008
  55 #define   C0_RGB4_XBGR    0x0000000c
  56 #define   C0_RGB5_RGGB    0x00000000
  57 #define   C0_RGB5_GRBG    0x00000004
  58 #define   C0_RGB5_GBRG    0x00000008
  59 #define   C0_RGB5_BGGR    0x0000000c
  60
  61 /* Spec has two fields for DIN and DOUT, but they must match, so
  62    combine them here. */
  63 #define   C0_DF_YUV       0x00000000    /* Data is YUV      */
  64 #define   C0_DF_RGB       0x000000a0    /* ... RGB                  */
  65 #define   C0_DF_BAYER     0x00000140    /* ... Bayer                */
  66 /* 8-8-8 must be missing from the below - ask */
  67 #define   C0_RGBF_565     0x00000000
  68 #define   C0_RGBF_444     0x00000800
  69 #define   C0_RGB_BGR      0x00001000    /* Blue comes first */
  70 #define   C0_YUV_PLANAR   0x00000000    /* YUV 422 planar format */
  71 #define   C0_YUV_PACKED   0x00008000    /* YUV 422 packed       */
  72 #define   C0_YUV_420PL    0x0000a000    /* YUV 420 planar       */
  73 /* Think that 420 packed must be 111 - ask */
  74 #define   C0_YUVE_YUYV    0x00000000    /* Y1CbY0Cr             */
  75 #define   C0_YUVE_YVYU    0x00010000    /* Y1CrY0Cb             */
  76 #define   C0_YUVE_VYUY    0x00020000    /* CrY1CbY0             */
  77 #define   C0_YUVE_UYVY    0x00030000    /* CbY1CrY0             */
  78 #define   C0_YUVE_XYUV    0x00000000    /* 420: .YUV            */
  79 #define   C0_YUVE_XYVU    0x00010000    /* 420: .YVU            */
  80 #define   C0_YUVE_XUVY    0x00020000    /* 420: .UVY            */
  81 #define   C0_YUVE_XVUY    0x00030000    /* 420: .VUY            */
  82 /* Bayer bits 18,19 if needed */
  83 #define   C0_HPOL_LOW     0x01000000    /* HSYNC polarity active low */
  84 #define   C0_VPOL_LOW     0x02000000    /* VSYNC polarity active low */
  85 #define   C0_VCLK_LOW     0x04000000    /* VCLK on falling edge */
  86 #define   C0_DOWNSCALE    0x08000000    /* Enable downscaler */
  87 #define   C0_SIFM_MASK    0xc0000000    /* SIF mode bits */
  88 #define   C0_SIF_HVSYNC   0x00000000    /* Use H/VSYNC */
  89 #define   CO_SOF_NOSYNC   0x40000000    /* Use inband active signaling */
  90
  91
  92 #define REG_CTRL1       0x40    /* Control 1 */
  93 #define   C1_444ALPHA     0x00f00000    /* Alpha field in RGB444 */
  94 #define   C1_ALPHA_SHFT   20
  95 #define   C1_DMAB32       0x00000000    /* 32-byte DMA burst */
  96 #define   C1_DMAB16       0x02000000    /* 16-byte DMA burst */
  97 #define   C1_DMAB64       0x04000000    /* 64-byte DMA burst */
  98 #define   C1_DMAB_MASK    0x06000000
  99 #define   C1_TWOBUFS      0x08000000    /* Use only two DMA buffers */
 100 #define   C1_PWRDWN       0x10000000    /* Power down */
 101
 102 #define REG_CLKCTRL     0x88    /* Clock control */
 103 #define   CLK_DIV_MASK    0x0000ffff    /* Upper bits RW "reserved" */
 104
 105 #define REG_GPR         0xb4    /* General purpose register.  This
 106                                    controls inputs to the power and reset
 107                                    pins on the OV7670 used with OLPC;
 108                                    other deployments could differ.  */
 109 #define   GPR_C1EN        0x00000020    /* Pad 1 (power down) enable */
 110 #define   GPR_C0EN        0x00000010    /* Pad 0 (reset) enable */
 111 #define   GPR_C1          0x00000002    /* Control 1 value */
 112 /*
 113  * Control 0 is wired to reset on OLPC machines.  For ov7x sensors,
 114  * it is active low, for 0v6x, instead, it's active high.  What
 115  * fun.
 116  */
 117 #define   GPR_C0          0x00000001    /* Control 0 value */
 118
 119 #define REG_TWSIC0      0xb8    /* TWSI (smbus) control 0 */
 120 #define   TWSIC0_EN       0x00000001    /* TWSI enable */
 121 #define   TWSIC0_MODE     0x00000002    /* 1 = 16-bit, 0 = 8-bit */
 122 #define   TWSIC0_SID      0x000003fc    /* Slave ID */
 123 #define   TWSIC0_SID_SHIFT 2
 124 #define   TWSIC0_CLKDIV   0x0007fc00    /* Clock divider */
 125 #define   TWSIC0_MASKACK  0x00400000    /* Mask ack from sensor */
 126 #define   TWSIC0_OVMAGIC  0x00800000    /* Make it work on OV sensors */
 127
 128 #define REG_TWSIC1      0xbc    /* TWSI control 1 */
 129 #define   TWSIC1_DATA     0x0000ffff    /* Data to/from camchip */
 130 #define   TWSIC1_ADDR     0x00ff0000    /* Address (register) */
 131 #define   TWSIC1_ADDR_SHIFT 16
 132 #define   TWSIC1_READ     0x01000000    /* Set for read op */
 133 #define   TWSIC1_WSTAT    0x02000000    /* Write status */
 134 #define   TWSIC1_RVALID   0x04000000    /* Read data valid */
 135 #define   TWSIC1_ERROR    0x08000000    /* Something screwed up */
 136
 137
 138 #define REG_UBAR        0xc4    /* Upper base address register */
 139
 140 /*
 141  * Here's the weird global control registers which are said to live
 142  * way up here.
 143  */
 144 #define REG_GL_CSR     0x3004  /* Control/status register */
 145 #define   GCSR_SRS       0x00000001     /* SW Reset set */
 146 #define   GCSR_SRC       0x00000002     /* SW Reset clear */
 147 #define   GCSR_MRS       0x00000004     /* Master reset set */
 148 #define   GCSR_MRC       0x00000008     /* HW Reset clear */
 149 #define   GCSR_CCIC_EN   0x00004000    /* CCIC Clock enable */
 150 #define REG_GL_IMASK   0x300c  /* Interrupt mask register */
 151 #define   GIMSK_CCIC_EN          0x00000004    /* CCIC Interrupt enable */
 152
 153 #define REG_GL_FCR      0x3038  /* GPIO functional control register */
 154 #define   GFCR_GPIO_ON    0x08          /* Camera GPIO enabled */
 155 #define REG_GL_GPIOR    0x315c  /* GPIO register */
 156 #define   GGPIO_OUT             0x80000 /* GPIO output */
 157 #define   GGPIO_VAL             0x00008 /* Output pin value */
 158
 159 #define REG_LEN                REG_GL_IMASK + 4
 160
 161
 162 /*
 163  * Useful stuff that probably belongs somewhere global.
 164  */
 165 #define VGA_WIDTH       640
 166 #define VGA_HEIGHT      480