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oxnas: fix duplicate include in clk-oxnas
[openwrt/openwrt.git] / target / linux / oxnas / files / drivers / ata / sata_oxnas.c
1 /*
2 * sata_oxnas
3 * A driver to interface the 934 based sata core present in the ox820
4 * with libata and scsi
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
31
32 #include <mach/utils.h>
33
34 /* sgdma request structure */
35 struct sgdma_request {
36 volatile u32 qualifier;
37 volatile u32 control;
38 dma_addr_t src_pa;
39 dma_addr_t dst_pa;
40 } __packed __aligned(4);
41
42
43 /* Controller information */
44 enum {
45 SATA_OXNAS_MAX_PRD = 254,
46 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
47 sizeof(struct ata_bmdma_prd) +
48 sizeof(struct sgdma_request),
49 SATA_OXNAS_MAX_PORTS = 2,
50 /** The different Oxsemi SATA core version numbers */
51 SATA_OXNAS_CORE_VERSION = 0x1f3,
52 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
53 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
54 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
55 SATA_OXNAS_QUEUE_DEPTH = 32,
56
57 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
58 };
59
60
61 /*
62 * SATA Port Registers
63 */
64 enum {
65 /** sata host port register offsets */
66 ORB1 = 0x00,
67 ORB2 = 0x04,
68 ORB3 = 0x08,
69 ORB4 = 0x0C,
70 ORB5 = 0x10,
71 MASTER_STATUS = 0x10,
72 FIS_CTRL = 0x18,
73 FIS_DATA = 0x1C,
74 INT_STATUS = 0x30,
75 INT_CLEAR = 0x30,
76 INT_ENABLE = 0x34,
77 INT_DISABLE = 0x38,
78 VERSION = 0x3C,
79 SATA_CONTROL = 0x5C,
80 SATA_COMMAND = 0x60,
81 HID_FEATURES = 0x64,
82 PORT_CONTROL = 0x68,
83 DRIVE_CONTROL = 0x6C,
84 /** These registers allow access to the link layer registers
85 that reside in a different clock domain to the processor bus */
86 LINK_DATA = 0x70,
87 LINK_RD_ADDR = 0x74,
88 LINK_WR_ADDR = 0x78,
89 LINK_CONTROL = 0x7C,
90 /* window control */
91 WIN1LO = 0x80,
92 WIN1HI = 0x84,
93 WIN2LO = 0x88,
94 WIN2HI = 0x8C,
95 WIN0_CONTROL = 0x90,
96 };
97
98 /** sata port register bits */
99 enum{
100 /**
101 * commands to issue in the master status to tell it to move shadow ,
102 * registers to the actual device ,
103 */
104 SATA_OPCODE_MASK = 0x00000007,
105 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
106 CMD_WRITE_TO_ORB_REGS = 0x2,
107 CMD_SYNC_ESCAPE = 0x7,
108 CMD_CORE_BUSY = (1 << 7),
109 CMD_DRIVE_SELECT_SHIFT = 12,
110 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
111
112 /** interrupt bits */
113 INT_END_OF_CMD = 1 << 0,
114 INT_LINK_SERROR = 1 << 1,
115 INT_ERROR = 1 << 2,
116 INT_LINK_IRQ = 1 << 3,
117 INT_REG_ACCESS_ERR = 1 << 7,
118 INT_BIST_FIS = 1 << 11,
119 INT_MASKABLE = INT_END_OF_CMD |
120 INT_LINK_SERROR |
121 INT_ERROR |
122 INT_LINK_IRQ |
123 INT_REG_ACCESS_ERR |
124 INT_BIST_FIS,
125 INT_WANT = INT_END_OF_CMD |
126 INT_LINK_SERROR |
127 INT_REG_ACCESS_ERR |
128 INT_ERROR,
129 INT_ERRORS = INT_LINK_SERROR |
130 INT_REG_ACCESS_ERR |
131 INT_ERROR,
132
133 /** raw interrupt bits, unmaskable, but do not generate interrupts */
134 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
135 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
136 RAW_ERROR = INT_ERROR << 16,
137 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
138 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
139 RAW_BIST_FIS = INT_BIST_FIS << 16,
140 RAW_WANT = INT_WANT << 16,
141 RAW_ERRORS = INT_ERRORS << 16,
142
143 /**
144 * variables to write to the device control register to set the current
145 * device, ie. master or slave.
146 */
147 DR_CON_48 = 2,
148 DR_CON_28 = 0,
149
150 SATA_CTL_ERR_MASK = 0x00000016,
151
152 };
153
154 /* ATA SGDMA register offsets */
155 enum {
156 SGDMA_CONTROL = 0x0,
157 SGDMA_STATUS = 0x4,
158 SGDMA_REQUESTPTR = 0x8,
159 SGDMA_RESETS = 0xC,
160 SGDMA_CORESIZE = 0x10,
161 };
162
163 /* DMA controller register offsets */
164 enum {
165 DMA_CONTROL = 0x0,
166 DMA_CORESIZE = 0x20,
167
168 DMA_CONTROL_RESET = (1 << 12),
169 };
170
171 enum {
172 /* see DMA core docs for the values. Out means from memory (bus A) out
173 * to disk (bus B) */
174 SGDMA_REQCTL0OUT = 0x0497c03d,
175 /* burst mode disabled when no micro code used */
176 SGDMA_REQCTL0IN = 0x0493a3c1,
177 SGDMA_REQCTL1OUT = 0x0497c07d,
178 SGDMA_REQCTL1IN = 0x0497a3c5,
179 SGDMA_CONTROL_NOGO = 0x3e,
180 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
181 SGDMA_ERRORMASK = 0x3f,
182 SGDMA_BUSY = 0x80,
183
184 SGDMA_RESETS_CTRL = 1 << 0,
185 SGDMA_RESETS_ARBT = 1 << 1,
186 SGDMA_RESETS_AHB = 1 << 2,
187 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
188 SGDMA_RESETS_ARBT |
189 SGDMA_RESETS_AHB,
190
191 /* Final EOTs */
192 SGDMA_REQQUAL = 0x00220001,
193
194 };
195
196 /** SATA core register offsets */
197 enum {
198 DM_DBG1 = 0x000,
199 RAID_SET = 0x004,
200 DM_DBG2 = 0x008,
201 DATACOUNT_PORT0 = 0x010,
202 DATACOUNT_PORT1 = 0x014,
203 CORE_INT_STATUS = 0x030,
204 CORE_INT_CLEAR = 0x030,
205 CORE_INT_ENABLE = 0x034,
206 CORE_INT_DISABLE = 0x038,
207 CORE_REBUILD_ENABLE = 0x050,
208 CORE_FAILED_PORT_R = 0x054,
209 DEVICE_CONTROL = 0x068,
210 EXCESS = 0x06C,
211 RAID_SIZE_LOW = 0x070,
212 RAID_SIZE_HIGH = 0x074,
213 PORT_ERROR_MASK = 0x078,
214 IDLE_STATUS = 0x07C,
215 RAID_CONTROL = 0x090,
216 DATA_PLANE_CTRL = 0x0AC,
217 CORE_DATAPLANE_STAT = 0x0b8,
218 PROC_PC = 0x100,
219 CONFIG_IN = 0x3d8,
220 PROC_START = 0x3f0,
221 PROC_RESET = 0x3f4,
222 UCODE_STORE = 0x1000,
223 RAID_WP_BOT_LOW = 0x1FF0,
224 RAID_WP_BOT_HIGH = 0x1FF4,
225 RAID_WP_TOP_LOW = 0x1FF8,
226 RAID_WP_TOP_HIGH = 0x1FFC,
227 DATA_MUX_RAM0 = 0x8000,
228 DATA_MUX_RAM1 = 0xA000,
229 PORT_SIZE = 0x10000,
230 };
231
232 enum {
233 /* Sata core debug1 register bits */
234 CORE_PORT0_DATA_DIR_BIT = 20,
235 CORE_PORT1_DATA_DIR_BIT = 21,
236 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
237 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
238
239 /** sata core control register bits */
240 SCTL_CLR_ERR = 0x00003016,
241 RAID_CLR_ERR = 0x0000011e,
242
243 /* Interrupts direct from the ports */
244 NORMAL_INTS_WANTED = 0x00000303,
245
246 /* shift these left by port number */
247 COREINT_HOST = 0x00000001,
248 COREINT_END = 0x00000100,
249 CORERAW_HOST = COREINT_HOST << 16,
250 CORERAW_END = COREINT_END << 16,
251
252 /* Interrupts from the RAID controller only */
253 RAID_INTS_WANTED = 0x00008300,
254
255 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
256 IDLE_CORES = (1 << 18) | (1 << 19),
257
258 /* Data plane control error-mask mask and bit, these bit in the data
259 * plane control mask out errors from the ports that prevent the SGDMA
260 * care from sending an interrupt */
261 DPC_ERROR_MASK = 0x00000300,
262 DPC_ERROR_MASK_BIT = 0x00000100,
263 /* enable jbod micro-code */
264 DPC_JBOD_UCODE = 1 << 0,
265 DPC_FIS_SWCH = 1 << 1,
266
267 /** Device Control register bits */
268 DEVICE_CONTROL_DMABT = 1 << 4,
269 DEVICE_CONTROL_ABORT = 1 << 2,
270 DEVICE_CONTROL_PAD = 1 << 3,
271 DEVICE_CONTROL_PADPAT = 1 << 16,
272 DEVICE_CONTROL_PRTRST = 1 << 8,
273 DEVICE_CONTROL_RAMRST = 1 << 12,
274 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
275
276 /** oxsemi HW raid modes */
277 OXNASSATA_NOTRAID = 0,
278 OXNASSATA_RAID0 = 1,
279 OXNASSATA_RAID1 = 2,
280 /** OX820 specific HW-RAID register values */
281 RAID_TWODISKS = 3,
282 UNKNOWN_MODE = ~0,
283
284 CONFIG_IN_RESUME = 2,
285 };
286
287 /* SATA PHY Registers */
288 enum {
289 PHY_STAT = 0x00,
290 PHY_DATA = 0x04,
291 };
292
293 enum {
294 STAT_READ_VALID = (1 << 21),
295 STAT_CR_ACK = (1 << 20),
296 STAT_CR_READ = (1 << 19),
297 STAT_CR_WRITE = (1 << 18),
298 STAT_CAP_DATA = (1 << 17),
299 STAT_CAP_ADDR = (1 << 16),
300
301 STAT_ACK_ANY = STAT_CR_ACK |
302 STAT_CR_READ |
303 STAT_CR_WRITE |
304 STAT_CAP_DATA |
305 STAT_CAP_ADDR,
306
307 CR_READ_ENABLE = (1 << 16),
308 CR_WRITE_ENABLE = (1 << 17),
309 CR_CAP_DATA = (1 << 18),
310 };
311
312 enum {
313 /* Link layer registers */
314 SERROR_IRQ_MASK = 5,
315 };
316
317 enum {
318 OXNAS_SATA_SOFTRESET = 1,
319 OXNAS_SATA_REINIT = 2,
320 };
321
322 enum {
323 OXNAS_SATA_UCODE_RAID0,
324 OXNAS_SATA_UCODE_RAID1,
325 OXNAS_SATA_UCODE_JBOD,
326 OXNAS_SATA_UCODE_NONE,
327 };
328
329 enum {
330 SATA_UNLOCKED,
331 SATA_WRITER,
332 SATA_READER,
333 SATA_REBUILD,
334 SATA_HWRAID,
335 SATA_SCSI_STACK
336 };
337
338 typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
339
340 struct sata_oxnas_host_priv {
341 void __iomem *port_base;
342 void __iomem *dmactl_base;
343 void __iomem *sgdma_base;
344 void __iomem *core_base;
345 void __iomem *phy_base;
346 dma_addr_t dma_base;
347 void __iomem *dma_base_va;
348 size_t dma_size;
349 int irq;
350 int n_ports;
351 int current_ucode;
352 u32 port_frozen;
353 u32 port_in_eh;
354 struct clk *clk;
355 struct reset_control *rst_sata;
356 struct reset_control *rst_link;
357 struct reset_control *rst_phy;
358 spinlock_t phy_lock;
359 spinlock_t core_lock;
360 int core_locked;
361 int reentrant_port_no;
362 int hw_lock_count;
363 int direct_lock_count;
364 void *locker_uid;
365 int current_locker_type;
366 int scsi_nonblocking_attempts;
367 oxnas_sata_isr_callback_t isr_callback;
368 void *isr_arg;
369 wait_queue_head_t fast_wait_queue;
370 wait_queue_head_t scsi_wait_queue;
371 };
372
373
374 struct sata_oxnas_port_priv {
375 void __iomem *port_base;
376 void __iomem *dmactl_base;
377 void __iomem *sgdma_base;
378 void __iomem *core_base;
379 struct sgdma_request *sgdma_request;
380 dma_addr_t sgdma_request_pa;
381 };
382
383 static u8 sata_oxnas_check_status(struct ata_port *ap);
384 static int sata_oxnas_cleanup(struct ata_host *ah);
385 static void sata_oxnas_tf_load(struct ata_port *ap,
386 const struct ata_taskfile *tf);
387 static void sata_oxnas_irq_on(struct ata_port *ap);
388 static void sata_oxnas_post_reset_init(struct ata_port *ap);
389
390 static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
391 int timeout_jiffies);
392 static void sata_oxnas_release_hw(struct ata_port *ap);
393
394 static const void *HW_LOCKER_UID = (void *)0xdeadbeef;
395
396 /***************************************************************************
397 * ASIC access
398 ***************************************************************************/
399 static void wait_cr_ack(void __iomem *phy_base)
400 {
401 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
402 ; /* wait for an ack bit to be set */
403 }
404
405 static u16 read_cr(void __iomem *phy_base, u16 address)
406 {
407 iowrite32((u32)address, phy_base + PHY_STAT);
408 wait_cr_ack(phy_base);
409 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
410 wait_cr_ack(phy_base);
411 return (u16)ioread32(phy_base + PHY_STAT);
412 }
413
414 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
415 {
416 iowrite32((u32)address, phy_base + PHY_STAT);
417 wait_cr_ack(phy_base);
418 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
419 wait_cr_ack(phy_base);
420 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
421 wait_cr_ack(phy_base);
422 }
423
424 #define PH_GAIN 2
425 #define FR_GAIN 3
426 #define PH_GAIN_OFFSET 6
427 #define FR_GAIN_OFFSET 8
428 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
429 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
430 #define USE_INT_SETTING (1<<5)
431
432 void workaround5458(struct ata_host *ah)
433 {
434 struct sata_oxnas_host_priv *hd = ah->private_data;
435 void __iomem *phy_base = hd->phy_base;
436 u16 rx_control;
437 unsigned i;
438
439 for (i = 0; i < 2; i++) {
440 rx_control = read_cr(phy_base, 0x201d + (i << 8));
441 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
442 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
443 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
444 write_cr(phy_base, rx_control, 0x201d+(i<<8));
445 }
446 }
447
448 /**
449 * allows access to the link layer registers
450 * @param link_reg the link layer register to access (oxsemi indexing ie
451 * 00 = static config, 04 = phy ctrl)
452 */
453 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
454 {
455 struct sata_oxnas_port_priv *pd = ap->private_data;
456 struct sata_oxnas_host_priv *hd = ap->host->private_data;
457 void __iomem *port_base = pd->port_base;
458 u32 patience;
459 unsigned long flags;
460
461 DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
462
463 spin_lock_irqsave(&hd->phy_lock, flags);
464 iowrite32(val, port_base + LINK_DATA);
465
466 /* accessed twice as a work around for a bug in the SATA abp bridge
467 * hardware (bug 6828) */
468 iowrite32(link_reg , port_base + LINK_WR_ADDR);
469 ioread32(port_base + LINK_WR_ADDR);
470
471 for (patience = 0x100000; patience > 0; --patience) {
472 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
473 break;
474 }
475 spin_unlock_irqrestore(&hd->phy_lock, flags);
476 }
477
478 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
479 u32 val)
480 {
481 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
482 return 0;
483 }
484
485 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
486 u32 val)
487 {
488 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
489 }
490
491 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
492 {
493 struct sata_oxnas_port_priv *pd = ap->private_data;
494 struct sata_oxnas_host_priv *hd = ap->host->private_data;
495 void __iomem *port_base = pd->port_base;
496 u32 result;
497 u32 patience;
498 unsigned long flags;
499
500 spin_lock_irqsave(&hd->phy_lock, flags);
501 /* accessed twice as a work around for a bug in the SATA abp bridge
502 * hardware (bug 6828) */
503 iowrite32(link_reg, port_base + LINK_RD_ADDR);
504 ioread32(port_base + LINK_RD_ADDR);
505
506 for (patience = 0x100000; patience > 0; --patience) {
507 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
508 break;
509 }
510 if (patience == 0)
511 DPRINTK("link read timed out for port %d\n", ap->port_no);
512
513 result = ioread32(port_base + LINK_DATA);
514 spin_unlock_irqrestore(&hd->phy_lock, flags);
515
516 return result;
517 }
518
519 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
520 u32 *val)
521 {
522 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
523 return 0;
524 }
525
526 static int sata_oxnas_scr_read(struct ata_link *link,
527 unsigned int sc_reg, u32 *val)
528 {
529 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
530 }
531
532 /**
533 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
534 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
535 * in the SATA core.
536 *
537 * @param ap hardware with the registers in
538 */
539 static void sata_oxnas_irq_clear(struct ata_port *ap)
540 {
541 struct sata_oxnas_port_priv *port_priv = ap->private_data;
542
543 /* clear pending interrupts */
544 iowrite32(~0, port_priv->port_base + INT_CLEAR);
545 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
546 }
547
548 /**
549 * qc_issue is used to make a command active, once the hardware and S/G tables
550 * have been prepared. IDE BMDMA drivers use the helper function
551 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
552 * drivers roll their own ->qc_issue implementation, using this as the
553 * "issue new ATA command to hardware" hook.
554 * @param qc the queued command to issue
555 */
556 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
557 {
558 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
559 struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
560
561 void __iomem *port_base = pd->port_base;
562 void __iomem *core_base = pd->core_base;
563 int port_no = qc->ap->port_no;
564 int no_microcode = (hd->current_ucode == UNKNOWN_MODE);
565 u32 reg;
566
567 /* check the core is idle */
568 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
569 int count = 0;
570
571 DPRINTK("core busy for a command on port %d\n",
572 qc->ap->port_no);
573 do {
574 mdelay(1);
575 if (++count > 100) {
576 DPRINTK("core busy for a command on port %d\n",
577 qc->ap->port_no);
578 /* CrazyDumpDebug(); */
579 sata_oxnas_cleanup(qc->ap->host);
580 }
581 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
582 }
583
584 /* enable passing of error signals to DMA sub-core by clearing the
585 * appropriate bit */
586 reg = ioread32(core_base + DATA_PLANE_CTRL);
587 if (no_microcode)
588 reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
589 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
590 iowrite32(reg, core_base + DATA_PLANE_CTRL);
591
592 /* Disable all interrupts for ports and RAID controller */
593 iowrite32(~0, port_base + INT_DISABLE);
594
595 /* Disable all interrupts for core */
596 iowrite32(~0, core_base + CORE_INT_DISABLE);
597 wmb();
598
599 /* Load the command settings into the orb registers */
600 sata_oxnas_tf_load(qc->ap, &qc->tf);
601
602 /* both pio and dma commands use dma */
603 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
604 /* Start the DMA */
605 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
606 wmb();
607 }
608
609 /* enable End of command interrupt */
610 iowrite32(INT_WANT, port_base + INT_ENABLE);
611 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
612 wmb();
613
614 /* Start the command */
615 reg = ioread32(port_base + SATA_COMMAND);
616 reg &= ~SATA_OPCODE_MASK;
617 reg |= CMD_WRITE_TO_ORB_REGS;
618 iowrite32(reg , port_base + SATA_COMMAND);
619 wmb();
620
621 return 0;
622 }
623
624 /**
625 * Will schedule the libATA error handler on the premise that there has
626 * been a hotplug event on the port specified
627 */
628 void sata_oxnas_checkforhotplug(struct ata_port *ap)
629 {
630 DPRINTK("ENTER\n");
631
632 ata_ehi_hotplugged(&ap->link.eh_info);
633 ata_port_freeze(ap);
634 }
635
636
637 /**************************************************************************/
638 /* Locking */
639 /**************************************************************************/
640 /**
641 * The underlying function that controls access to the sata core
642 *
643 * @return non-zero indicates that you have acquired exclusive access to the
644 * sata core.
645 */
646 static int __acquire_sata_core(
647 struct ata_host *ah,
648 int port_no,
649 oxnas_sata_isr_callback_t callback,
650 void *arg,
651 int may_sleep,
652 int timeout_jiffies,
653 int hw_access,
654 void *uid,
655 int locker_type)
656 {
657 unsigned long end = jiffies + timeout_jiffies;
658 int acquired = 0;
659 unsigned long flags;
660 int timed_out = 0;
661 struct sata_oxnas_host_priv *hd;
662
663 DEFINE_WAIT(wait);
664
665 if (!ah)
666 return acquired;
667
668 hd = ah->private_data;
669
670 spin_lock_irqsave(&hd->core_lock, flags);
671
672 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
673 "callback %p, hw_access %d, core_locked %d, "
674 "reentrant_port_no %d, isr_callback %p\n",
675 uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
676 callback, hw_access, hd->core_locked, hd->reentrant_port_no,
677 hd->isr_callback);
678
679 while (!timed_out) {
680 if (hd->core_locked ||
681 (!hw_access && hd->scsi_nonblocking_attempts)) {
682 /* Can only allow access if from SCSI/SATA stack and if
683 * reentrant access is allowed and this access is to the
684 * same port for which the lock is current held
685 */
686 if (hw_access && (port_no == hd->reentrant_port_no)) {
687 BUG_ON(!hd->hw_lock_count);
688 ++(hd->hw_lock_count);
689
690 DPRINTK("Allow SCSI/SATA re-entrant access to "
691 "uid %p port %d\n", uid, port_no);
692 acquired = 1;
693 break;
694 } else if (!hw_access) {
695 if ((locker_type == SATA_READER) &&
696 (hd->current_locker_type == SATA_READER)) {
697 WARN(1,
698 "Already locked by reader, "
699 "uid %p, locker_uid %p, "
700 "port %d, h/w count %d, "
701 "d count %d, hw_access %d\n",
702 uid, hd->locker_uid, port_no,
703 hd->hw_lock_count,
704 hd->direct_lock_count,
705 hw_access);
706 goto check_uid;
707 }
708
709 if ((locker_type != SATA_READER) &&
710 (locker_type != SATA_WRITER)) {
711 goto wait_for_lock;
712 }
713
714 check_uid:
715 WARN(uid == hd->locker_uid, "Attempt to lock "
716 "by locker type %d uid %p, already "
717 "locked by locker type %d with "
718 "locker_uid %p, port %d, "
719 "h/w count %d, d count %d, "
720 "hw_access %d\n", locker_type, uid,
721 hd->current_locker_type,
722 hd->locker_uid, port_no,
723 hd->hw_lock_count,
724 hd->direct_lock_count, hw_access);
725 }
726 } else {
727 WARN(hd->hw_lock_count || hd->direct_lock_count,
728 "Core unlocked but counts non-zero: uid %p, "
729 "locker_uid %p, port %d, h/w count %d, "
730 "d count %d, hw_access %d\n", uid,
731 hd->locker_uid, port_no, hd->hw_lock_count,
732 hd->direct_lock_count, hw_access);
733
734 BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
735
736 WARN(hd->locker_uid, "Attempt to lock uid %p when "
737 "locker_uid %p is non-zero, port %d, "
738 "h/w count %d, d count %d, hw_access %d\n",
739 uid, hd->locker_uid, port_no, hd->hw_lock_count,
740 hd->direct_lock_count, hw_access);
741
742 if (!hw_access) {
743 /* Direct access attempting to acquire
744 * non-contented lock
745 */
746 /* Must have callback for direct access */
747 BUG_ON(!callback);
748 /* Sanity check lock state */
749 BUG_ON(hd->reentrant_port_no != -1);
750
751 hd->isr_callback = callback;
752 hd->isr_arg = arg;
753 ++(hd->direct_lock_count);
754
755 hd->current_locker_type = locker_type;
756 } else {
757 /* SCSI/SATA attempting to acquire
758 * non-contented lock
759 */
760 /* No callbacks for SCSI/SATA access */
761 BUG_ON(callback);
762 /* No callback args for SCSI/SATA access */
763 BUG_ON(arg);
764
765 /* Sanity check lock state */
766 BUG_ON(hd->isr_callback);
767 BUG_ON(hd->isr_arg);
768
769 ++(hd->hw_lock_count);
770 hd->reentrant_port_no = port_no;
771
772 hd->current_locker_type = SATA_SCSI_STACK;
773 }
774
775 hd->core_locked = 1;
776 hd->locker_uid = uid;
777 acquired = 1;
778 break;
779 }
780
781 wait_for_lock:
782 if (!may_sleep) {
783 DPRINTK("Denying for uid %p locker_type %d, "
784 "hw_access %d, port %d, current_locker_type %d as "
785 "cannot sleep\n", uid, locker_type, hw_access, port_no,
786 hd->current_locker_type);
787
788 if (hw_access)
789 ++(hd->scsi_nonblocking_attempts);
790
791 break;
792 }
793
794 /* Core is locked and we're allowed to sleep, so wait to be
795 * awoken when the core is unlocked
796 */
797 for (;;) {
798 prepare_to_wait(hw_access ? &hd->scsi_wait_queue :
799 &hd->fast_wait_queue,
800 &wait, TASK_UNINTERRUPTIBLE);
801 if (!hd->core_locked &&
802 !(!hw_access && hd->scsi_nonblocking_attempts)) {
803 /* We're going to use variables that will have
804 * been changed by the waker prior to clearing
805 * core_locked so we need to ensure we see
806 * changes to all those variables
807 */
808 smp_rmb();
809 break;
810 }
811 if (time_after(jiffies, end)) {
812 printk(KERN_WARNING "__acquire_sata_core() "
813 "uid %p failing for port %d timed out, "
814 "locker_uid %p, h/w count %d, "
815 "d count %d, callback %p, hw_access %d, "
816 "core_locked %d, reentrant_port_no %d, "
817 "isr_callback %p, isr_arg %p\n", uid,
818 port_no, hd->locker_uid,
819 hd->hw_lock_count,
820 hd->direct_lock_count, callback,
821 hw_access, hd->core_locked,
822 hd->reentrant_port_no, hd->isr_callback,
823 hd->isr_arg);
824 timed_out = 1;
825 break;
826 }
827 spin_unlock_irqrestore(&hd->core_lock, flags);
828 if (!schedule_timeout(4*HZ)) {
829 printk(KERN_INFO "__acquire_sata_core() uid %p, "
830 "locker_uid %p, timed-out of "
831 "schedule(), checking overall timeout\n",
832 uid, hd->locker_uid);
833 }
834 spin_lock_irqsave(&hd->core_lock, flags);
835 }
836 finish_wait(hw_access ? &hd->scsi_wait_queue :
837 &hd->fast_wait_queue, &wait);
838 }
839
840 if (hw_access && acquired) {
841 if (hd->scsi_nonblocking_attempts)
842 hd->scsi_nonblocking_attempts = 0;
843
844 /* Wake any other SCSI/SATA waiters so they can get reentrant
845 * access to the same port if appropriate. This is because if
846 * the SATA core is locked by fast access, or SCSI/SATA access
847 * to other port, then can have >1 SCSI/SATA waiters on the wait
848 * list so want to give reentrant accessors a chance to get
849 * access ASAP
850 */
851 if (!list_empty(&hd->scsi_wait_queue.task_list))
852 wake_up(&hd->scsi_wait_queue);
853 }
854
855 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
856 uid, acquired, port_no, callback);
857
858 spin_unlock_irqrestore(&hd->core_lock, flags);
859
860 return acquired;
861 }
862
863 int sata_core_has_fast_waiters(struct ata_host *ah)
864 {
865 int has_waiters;
866 unsigned long flags;
867 struct sata_oxnas_host_priv *hd = ah->private_data;
868
869 spin_lock_irqsave(&hd->core_lock, flags);
870 has_waiters = !list_empty(&hd->fast_wait_queue.task_list);
871 spin_unlock_irqrestore(&hd->core_lock, flags);
872
873 return has_waiters;
874 }
875 EXPORT_SYMBOL(sata_core_has_fast_waiters);
876
877 int sata_core_has_scsi_waiters(struct ata_host *ah)
878 {
879 int has_waiters;
880 unsigned long flags;
881 struct sata_oxnas_host_priv *hd = ah->private_data;
882
883 spin_lock_irqsave(&hd->core_lock, flags);
884 has_waiters = hd->scsi_nonblocking_attempts ||
885 !list_empty(&hd->scsi_wait_queue.task_list);
886 spin_unlock_irqrestore(&hd->core_lock, flags);
887
888 return has_waiters;
889 }
890 EXPORT_SYMBOL(sata_core_has_scsi_waiters);
891
892 /*
893 * ata_port operation to gain ownership of the SATA hardware prior to issuing
894 * a command against a SATA host. Allows any number of users of the port against
895 * which the lock was first acquired, thus enforcing that only one SATA core
896 * port may be operated on at once.
897 */
898 static int sata_oxnas_acquire_hw(
899 struct ata_port *ap,
900 int may_sleep,
901 int timeout_jiffies)
902 {
903 return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,
904 timeout_jiffies, 1, (void *)HW_LOCKER_UID,
905 SATA_SCSI_STACK);
906 }
907
908 /*
909 * operation to release ownership of the SATA hardware
910 */
911 static void sata_oxnas_release_hw(struct ata_port *ap)
912 {
913 unsigned long flags;
914 int released = 0;
915 struct sata_oxnas_host_priv *hd = ap->host->private_data;
916
917 spin_lock_irqsave(&hd->core_lock, flags);
918
919 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
920 "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
921 ap->port_no, hd->hw_lock_count, hd->direct_lock_count,
922 hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
923
924 if (!hd->core_locked) {
925 /* Nobody holds the SATA lock */
926 printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n",
927 ap->port_no);
928 released = 1;
929 } else if (!hd->hw_lock_count) {
930 /* SCSI/SATA has released without holding the lock */
931 printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, "
932 "port_no %d\n", ap->port_no);
933 } else {
934 /* Trap incorrect usage */
935 BUG_ON(hd->reentrant_port_no == -1);
936 BUG_ON(ap->port_no != hd->reentrant_port_no);
937 BUG_ON(hd->direct_lock_count);
938 BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
939
940 WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),
941 "Invalid locker uid %p, h/w count %d, d count %d, "
942 "reentrant_port_no %d, core_locked %d, "
943 "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count,
944 hd->direct_lock_count, hd->reentrant_port_no,
945 hd->core_locked, hd->isr_callback);
946
947 if (--(hd->hw_lock_count)) {
948 DPRINTK("Still nested port_no %d\n", ap->port_no);
949 } else {
950 DPRINTK("Release port_no %d\n", ap->port_no);
951 hd->reentrant_port_no = -1;
952 hd->isr_callback = NULL;
953 hd->current_locker_type = SATA_UNLOCKED;
954 hd->locker_uid = 0;
955 hd->core_locked = 0;
956 released = 1;
957 wake_up(!list_empty(&hd->scsi_wait_queue.task_list) ?
958 &hd->scsi_wait_queue :
959 &hd->fast_wait_queue);
960 }
961 }
962
963 DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no,
964 hd->hw_lock_count);
965
966 spin_unlock_irqrestore(&hd->core_lock, flags);
967
968 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
969 /* if (released)
970 ox820hwraid_restart_queue();
971 } */
972 }
973
974 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
975 {
976 struct sata_oxnas_host_priv *hd = ah->private_data;
977
978 smp_rmb();
979 return hd->port_in_eh || hd->port_frozen;
980 }
981
982
983 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
984 {
985 struct sata_oxnas_host_priv *hd = ap->host->private_data;
986
987 return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
988 (hd->n_ports > 1 &&
989 (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &
990 CMD_CORE_BUSY));
991 }
992
993 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
994 {
995 struct sata_oxnas_port_priv *pd = ap->private_data;
996
997 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
998 }
999
1000
1001 /**
1002 * Turns on the cores clock and resets it
1003 */
1004 static void sata_oxnas_reset_core(struct ata_host *ah)
1005 {
1006 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1007 int n;
1008
1009 DPRINTK("ENTER\n");
1010 clk_prepare_enable(host_priv->clk);
1011
1012 reset_control_assert(host_priv->rst_sata);
1013 reset_control_assert(host_priv->rst_link);
1014 reset_control_assert(host_priv->rst_phy);
1015
1016 udelay(50);
1017
1018 /* un-reset the PHY, then Link and Controller */
1019 reset_control_deassert(host_priv->rst_phy);
1020 udelay(50);
1021
1022 reset_control_deassert(host_priv->rst_sata);
1023 reset_control_deassert(host_priv->rst_link);
1024 udelay(50);
1025
1026 workaround5458(ah);
1027 /* tune for sata compatibility */
1028 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
1029
1030 for (n = 0; n < host_priv->n_ports; n++) {
1031 /* each port in turn */
1032 sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
1033 }
1034 udelay(50);
1035 }
1036
1037
1038 /**
1039 * Called after an identify device command has worked out what kind of device
1040 * is on the port
1041 *
1042 * @param port The port to configure
1043 * @param pdev The hardware associated with controlling the port
1044 */
1045 static void sata_oxnas_dev_config(struct ata_device *pdev)
1046 {
1047 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
1048 void __iomem *port_base = pd->port_base;
1049 u32 reg;
1050
1051 DPRINTK("ENTER\n");
1052 /* Set the bits to put the port into 28 or 48-bit node */
1053 reg = ioread32(port_base + DRIVE_CONTROL);
1054 reg &= ~3;
1055 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
1056 iowrite32(reg, port_base + DRIVE_CONTROL);
1057
1058 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1059 if (pdev->flags & ATA_DFLAG_LBA48) {
1060 reg = ioread32(port_base + PORT_CONTROL);
1061 reg |= 2;
1062 iowrite32(reg, port_base + PORT_CONTROL);
1063 }
1064 }
1065 /**
1066 * called to write a taskfile into the ORB registers
1067 * @param ap hardware with the registers in
1068 * @param tf taskfile to write to the registers
1069 */
1070 static void sata_oxnas_tf_load(struct ata_port *ap,
1071 const struct ata_taskfile *tf)
1072 {
1073 u32 count = 0;
1074 u32 Orb1 = 0;
1075 u32 Orb2 = 0;
1076 u32 Orb3 = 0;
1077 u32 Orb4 = 0;
1078 u32 Command_Reg;
1079
1080 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1081 void __iomem *port_base = port_priv->port_base;
1082 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
1083
1084 /* wait a maximum of 10ms for the core to be idle */
1085 do {
1086 Command_Reg = ioread32(port_base + SATA_COMMAND);
1087 if (!(Command_Reg & CMD_CORE_BUSY))
1088 break;
1089 count++;
1090 udelay(50);
1091 } while (count < 200);
1092
1093 /* check if the ctl register has interrupts disabled or enabled and
1094 * modify the interrupt enable registers on the ata core as required */
1095 if (tf->ctl & ATA_NIEN) {
1096 /* interrupts disabled */
1097 u32 mask = (COREINT_END << ap->port_no);
1098
1099 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
1100 sata_oxnas_irq_clear(ap);
1101 } else {
1102 sata_oxnas_irq_on(ap);
1103 }
1104
1105 Orb2 |= (tf->command) << 24;
1106
1107 /* write 48 or 28 bit tf parameters */
1108 if (is_addr) {
1109 /* set LBA bit as it's an address */
1110 Orb1 |= (tf->device & ATA_LBA) << 24;
1111
1112 if (tf->flags & ATA_TFLAG_LBA48) {
1113 Orb1 |= ATA_LBA << 24;
1114 Orb2 |= (tf->hob_nsect) << 8;
1115 Orb3 |= (tf->hob_lbal) << 24;
1116 Orb4 |= (tf->hob_lbam) << 0;
1117 Orb4 |= (tf->hob_lbah) << 8;
1118 Orb4 |= (tf->hob_feature) << 16;
1119 } else {
1120 Orb3 |= (tf->device & 0xf) << 24;
1121 }
1122
1123 /* write 28-bit lba */
1124 Orb2 |= (tf->nsect) << 0;
1125 Orb2 |= (tf->feature) << 16;
1126 Orb3 |= (tf->lbal) << 0;
1127 Orb3 |= (tf->lbam) << 8;
1128 Orb3 |= (tf->lbah) << 16;
1129 Orb4 |= (tf->ctl) << 24;
1130 }
1131
1132 if (tf->flags & ATA_TFLAG_DEVICE)
1133 Orb1 |= (tf->device) << 24;
1134
1135 ap->last_ctl = tf->ctl;
1136
1137 /* write values to registers */
1138 iowrite32(Orb1, port_base + ORB1);
1139 iowrite32(Orb2, port_base + ORB2);
1140 iowrite32(Orb3, port_base + ORB3);
1141 iowrite32(Orb4, port_base + ORB4);
1142 }
1143
1144
1145 void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
1146 {
1147 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1148 void __iomem *core_base = host_priv->core_base;
1149
1150 unsigned int *src;
1151 void __iomem *dst;
1152 unsigned int progmicrocode = 0;
1153 unsigned int changeparameters = 0;
1154
1155 u32 previous_mode;
1156
1157 /* these micro-code programs _should_ include the version word */
1158
1159 /* JBOD */
1160 static const unsigned int jbod[] = {
1161 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1162 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1163 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1164 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1165 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1166 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1167 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1168 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1169 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1170 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1171 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1172 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1173 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1174 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1175 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1176 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1177 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1178 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1179 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1180 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1181 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1182 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1183 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1184 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1185 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1186 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1187 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1188 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1189 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1190 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1191 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1192 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1193 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1194 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1195 0x00718908, 0x0208A206, 0x00EE0005, ~0
1196 };
1197
1198 /* Bi-Modal RAID-0/1 */
1199 static const unsigned int raid[] = {
1200 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1201 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1202 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1203 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1204 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1205 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1206 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1207 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1208 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1209 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1210 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1211 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1212 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1213 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1214 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1215 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1216 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1217 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1218 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1219 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1220 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1221 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1222 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1223 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1224 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1225 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1226 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1227 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1228 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1229 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1230 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1231 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1232 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1233 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1234 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1235 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1236 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1237 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1238 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1239 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1240 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1241 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1242 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1243 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1244 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1245 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1246 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1247 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1248 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1249 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1250 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1251 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1252 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1253 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1254 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1255 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1256 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1257 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1258 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1259 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1260 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1261 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1262 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1263 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1264 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1265 0x02400000, ~0
1266 };
1267
1268 DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
1269
1270 if (force)
1271 previous_mode = UNKNOWN_MODE;
1272 else
1273 previous_mode = host_priv->current_ucode;
1274
1275 if (mode == previous_mode)
1276 return;
1277
1278 host_priv->current_ucode = mode;
1279
1280 /* decide what needs to be done using the STD in my logbook */
1281 switch (previous_mode) {
1282 case OXNASSATA_RAID1:
1283 switch (mode) {
1284 case OXNASSATA_RAID0:
1285 changeparameters = 1;
1286 break;
1287 case OXNASSATA_NOTRAID:
1288 changeparameters = 1;
1289 progmicrocode = 1;
1290 break;
1291 }
1292 break;
1293 case OXNASSATA_RAID0:
1294 switch (mode) {
1295 case OXNASSATA_RAID1:
1296 changeparameters = 1;
1297 break;
1298 case OXNASSATA_NOTRAID:
1299 changeparameters = 1;
1300 progmicrocode = 1;
1301 break;
1302 }
1303 break;
1304 case OXNASSATA_NOTRAID:
1305 switch (mode) {
1306 case OXNASSATA_RAID0:
1307 case OXNASSATA_RAID1:
1308 changeparameters = 1;
1309 progmicrocode = 1;
1310 break;
1311 }
1312 break;
1313 case UNKNOWN_MODE:
1314 changeparameters = 1;
1315 progmicrocode = 1;
1316 break;
1317 }
1318
1319 /* no need to reprogram everything if already in the right mode */
1320 if (progmicrocode) {
1321 /* reset micro-code processor */
1322 iowrite32(1, core_base + PROC_RESET);
1323 wmb();
1324
1325 /* select micro-code */
1326 switch (mode) {
1327 case OXNASSATA_RAID1:
1328 case OXNASSATA_RAID0:
1329 VPRINTK("Loading RAID micro-code\n");
1330 src = (unsigned int *)&raid[1];
1331 break;
1332 case OXNASSATA_NOTRAID:
1333 VPRINTK("Loading JBOD micro-code\n");
1334 src = (unsigned int *)&jbod[1];
1335 break;
1336 default:
1337 BUG();
1338 break;
1339 }
1340
1341 /* load micro code */
1342 dst = core_base + UCODE_STORE;
1343 while (*src != ~0) {
1344 iowrite32(*src, dst);
1345 src++;
1346 dst += sizeof(*src);
1347 }
1348 wmb();
1349 }
1350
1351 if (changeparameters) {
1352 u32 reg;
1353 /* set other mode dependent flags */
1354 switch (mode) {
1355 case OXNASSATA_RAID1:
1356 /* clear JBOD mode */
1357 reg = ioread32(core_base + DATA_PLANE_CTRL);
1358 reg |= DPC_JBOD_UCODE;
1359 reg &= ~DPC_FIS_SWCH;
1360 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1361 wmb();
1362
1363 /* set the hardware up for RAID-1 */
1364 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1365 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1366 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1367 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1368 iowrite32(0, core_base + RAID_SIZE_LOW);
1369 iowrite32(0, core_base + RAID_SIZE_HIGH);
1370 wmb();
1371 break;
1372 case OXNASSATA_RAID0:
1373 /* clear JBOD mode */
1374 reg = ioread32(core_base + DATA_PLANE_CTRL);
1375 reg |= DPC_JBOD_UCODE;
1376 reg &= ~DPC_FIS_SWCH;
1377 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1378 wmb();
1379
1380 /* set the hardware up for RAID-1 */
1381 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1382 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1383 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1384 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1385 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
1386 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
1387 wmb();
1388 break;
1389 case OXNASSATA_NOTRAID:
1390 /* enable jbod mode */
1391 reg = ioread32(core_base + DATA_PLANE_CTRL);
1392 reg &= ~DPC_JBOD_UCODE;
1393 reg &= ~DPC_FIS_SWCH;
1394 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1395 wmb();
1396
1397 /* start micro-code processor*/
1398 iowrite32(1, core_base + PROC_START);
1399 break;
1400 default:
1401 reg = ioread32(core_base + DATA_PLANE_CTRL);
1402 reg |= DPC_JBOD_UCODE;
1403 reg &= ~DPC_FIS_SWCH;
1404 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1405 wmb();
1406 break;
1407 }
1408 }
1409 }
1410
1411 /**
1412 * sends a sync-escape if there is a link present
1413 */
1414 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
1415 {
1416 struct sata_oxnas_port_priv *pd = ap->private_data;
1417 u32 reg;
1418
1419 /* read the SSTATUS register and only send a sync escape if there is a
1420 * link active */
1421 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
1422 reg = ioread32(pd->port_base + SATA_COMMAND);
1423 reg &= ~SATA_OPCODE_MASK;
1424 reg |= CMD_SYNC_ESCAPE;
1425 iowrite32(reg, pd->port_base + SATA_COMMAND);
1426 }
1427 }
1428
1429 /* clears errors */
1430 static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
1431 {
1432 struct sata_oxnas_port_priv *pd = ap->private_data;
1433 u32 *base = pd->port_base;
1434 u32 reg;
1435
1436 reg = ioread32(base + SATA_CONTROL);
1437 reg &= SATA_CTL_ERR_MASK;
1438 iowrite32(reg, base + SATA_CONTROL);
1439 }
1440
1441 static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
1442 {
1443 struct sata_oxnas_port_priv *pd = ap->private_data;
1444
1445 iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
1446 }
1447
1448 static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
1449 {
1450 struct sata_oxnas_port_priv *pd = ap->private_data;
1451 u32 reg;
1452
1453 reg = ioread32(pd->dmactl_base + DMA_CONTROL);
1454 if (assert)
1455 reg |= DMA_CONTROL_RESET;
1456 else
1457 reg &= ~DMA_CONTROL_RESET;
1458
1459 iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
1460 };
1461
1462 /**
1463 * Clears the error caused by the core's registers being accessed when the
1464 * core is busy.
1465 */
1466 static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
1467 {
1468 struct sata_oxnas_port_priv *pd = ap->private_data;
1469 u32 *base = pd->port_base;
1470 u32 reg;
1471
1472 reg = ioread32(base + INT_STATUS);
1473
1474 DPRINTK("ENTER\n");
1475 if (reg & INT_REG_ACCESS_ERR) {
1476 DPRINTK("clearing register access error on port %d\n",
1477 ap->port_no);
1478 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1479 }
1480 reg = ioread32(base + INT_STATUS);
1481 if (reg & INT_REG_ACCESS_ERR)
1482 DPRINTK("register access error didn't clear\n");
1483 }
1484
1485 static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
1486 {
1487 struct sata_oxnas_port_priv *pd = ap->private_data;
1488 u32 *base = pd->port_base;
1489 u32 reg;
1490
1491 reg = ioread32(base + SATA_CONTROL);
1492 reg |= SCTL_CLR_ERR;
1493 iowrite32(reg, base + SATA_CONTROL);
1494 }
1495
1496 static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
1497 {
1498 return;
1499 };
1500
1501 /**
1502 * Clean up all the state machines in the sata core.
1503 * @return post cleanup action required
1504 */
1505 static int sata_oxnas_cleanup(struct ata_host *ah)
1506 {
1507 struct sata_oxnas_host_priv *hd = ah->private_data;
1508 int actions_required = 0;
1509 int n;
1510
1511 printk(KERN_INFO "sata_oxnas: resetting SATA core\n");
1512 /* core not recovering, reset it */
1513 mdelay(5);
1514 sata_oxnas_reset_core(ah);
1515 mdelay(5);
1516 actions_required |= OXNAS_SATA_REINIT;
1517 /* Perform any SATA core re-initialisation after reset post reset init
1518 * needs to be called for both ports as there's one reset for both
1519 * ports */
1520 for (n = 0; n < hd->n_ports; n++)
1521 sata_oxnas_post_reset_init(ah->ports[n]);
1522
1523
1524 return actions_required;
1525 }
1526
1527 /**
1528 * ata_qc_new - Request an available ATA command, for queueing
1529 * @ap: Port associated with device @dev
1530 * @return non zero will refuse a new command, zero will may grant on subject
1531 * to conditions elsewhere.
1532 *
1533 */
1534 static int sata_oxnas_qc_new(struct ata_port *ap)
1535 {
1536 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1537
1538 DPRINTK("port %d\n", ap->port_no);
1539 smp_rmb();
1540 if (hd->port_frozen || hd->port_in_eh)
1541 return 1;
1542 else
1543 return !sata_oxnas_acquire_hw(ap, 0, 0);
1544 }
1545
1546 /**
1547 * releases the lock on the port the command used
1548 */
1549 static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
1550 {
1551 DPRINTK("\n");
1552 sata_oxnas_release_hw(qc->ap);
1553 }
1554
1555 static void sata_oxnas_freeze(struct ata_port *ap)
1556 {
1557 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1558
1559 DPRINTK("\n");
1560 hd->port_frozen |= BIT(ap->port_no);
1561 smp_wmb();
1562 }
1563
1564 static void sata_oxnas_thaw(struct ata_port *ap)
1565 {
1566 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1567
1568 DPRINTK("\n");
1569 hd->port_frozen &= ~BIT(ap->port_no);
1570 smp_wmb();
1571 }
1572
1573 void sata_oxnas_freeze_host(struct ata_port *ap)
1574 {
1575 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1576
1577 DPRINTK("ENTER\n");
1578 hd->port_in_eh |= BIT(ap->port_no);
1579 smp_wmb();
1580 }
1581
1582 void sata_oxnas_thaw_host(struct ata_port *ap)
1583 {
1584 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1585
1586 DPRINTK("ENTER\n");
1587 hd->port_in_eh &= ~BIT(ap->port_no);
1588 smp_wmb();
1589 }
1590
1591 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1592 {
1593 DPRINTK("ENTER\n");
1594 /* If the core is busy here, make it idle */
1595 if (qc->flags & ATA_QCFLAG_FAILED)
1596 sata_oxnas_cleanup(qc->ap->host);
1597 }
1598
1599
1600 /**
1601 * turn on the interrupts
1602 *
1603 * @param ap Hardware with the registers in
1604 */
1605 static void sata_oxnas_irq_on(struct ata_port *ap)
1606 {
1607 struct sata_oxnas_port_priv *pd = ap->private_data;
1608 u32 mask = (COREINT_END << ap->port_no);
1609
1610 /* Clear pending interrupts */
1611 iowrite32(~0, pd->port_base + INT_CLEAR);
1612 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1613 wmb();
1614
1615 /* enable End of command interrupt */
1616 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1617 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1618 }
1619
1620
1621 /** @return true if the port has a cable connected */
1622 int sata_oxnas_check_link(struct ata_port *ap)
1623 {
1624 int reg;
1625
1626 sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
1627 /* Check for the cable present indicated by SCR status bit-0 set */
1628 return reg & 0x1;
1629 }
1630
1631 /**
1632 * ata_std_postreset - standard postreset callback
1633 * @link: the target ata_link
1634 * @classes: classes of attached devices
1635 *
1636 * This function is invoked after a successful reset. Note that
1637 * the device might have been reset more than once using
1638 * different reset methods before postreset is invoked.
1639 *
1640 * LOCKING:
1641 * Kernel thread context (may sleep)
1642 */
1643 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1644 {
1645 struct ata_port *ap = link->ap;
1646 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1647
1648 unsigned int dev;
1649
1650 DPRINTK("ENTER\n");
1651 ata_std_postreset(link, classes);
1652
1653 /* turn on phy error detection by removing the masks */
1654 sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
1655 if (hd->n_ports > 1)
1656 sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
1657
1658 /* bail out if no device is present */
1659 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1660 DPRINTK("EXIT, no device\n");
1661 return;
1662 }
1663
1664 /* go through all the devices and configure them */
1665 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1666 if (ap->link.device[dev].class == ATA_DEV_ATA)
1667 sata_oxnas_dev_config(&(ap->link.device[dev]));
1668 }
1669
1670 DPRINTK("EXIT\n");
1671 }
1672
1673 /**
1674 * Called to read the hardware registers / DMA buffers, to
1675 * obtain the current set of taskfile register values.
1676 * @param ap hardware with the registers in
1677 * @param tf taskfile to read the registers into
1678 */
1679 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1680 {
1681 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1682 void __iomem *port_base = port_priv->port_base;
1683 /* read the orb registers */
1684 u32 Orb1 = ioread32(port_base + ORB1);
1685 u32 Orb2 = ioread32(port_base + ORB2);
1686 u32 Orb3 = ioread32(port_base + ORB3);
1687 u32 Orb4 = ioread32(port_base + ORB4);
1688
1689 /* read common 28/48 bit tf parameters */
1690 tf->device = (Orb1 >> 24);
1691 tf->nsect = (Orb2 >> 0);
1692 tf->feature = (Orb2 >> 16);
1693 tf->command = sata_oxnas_check_status(ap);
1694
1695 /* read 48 or 28 bit tf parameters */
1696 if (tf->flags & ATA_TFLAG_LBA48) {
1697 tf->hob_nsect = (Orb2 >> 8);
1698 tf->lbal = (Orb3 >> 0);
1699 tf->lbam = (Orb3 >> 8);
1700 tf->lbah = (Orb3 >> 16);
1701 tf->hob_lbal = (Orb3 >> 24);
1702 tf->hob_lbam = (Orb4 >> 0);
1703 tf->hob_lbah = (Orb4 >> 8);
1704 /* feature ext and control are write only */
1705 } else {
1706 /* read 28-bit lba */
1707 tf->lbal = (Orb3 >> 0);
1708 tf->lbam = (Orb3 >> 8);
1709 tf->lbah = (Orb3 >> 16);
1710 }
1711 }
1712
1713 /**
1714 * Read a result task-file from the sata core registers.
1715 */
1716 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1717 {
1718 /* Read the most recently received FIS from the SATA core ORB registers
1719 and convert to an ATA taskfile */
1720 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1721 return true;
1722 }
1723
1724 /**
1725 * Reads the Status ATA shadow register from hardware.
1726 *
1727 * @return The status register
1728 */
1729 static u8 sata_oxnas_check_status(struct ata_port *ap)
1730 {
1731 u32 Reg;
1732 u8 status;
1733 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1734 void __iomem *port_base = port_priv->port_base;
1735
1736 /* read byte 3 of Orb2 register */
1737 status = ioread32(port_base + ORB2) >> 24;
1738
1739 /* check for the drive going missing indicated by SCR status bits
1740 * 0-3 = 0 */
1741 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1742
1743 if (!(Reg & 0x1)) {
1744 status |= ATA_DF;
1745 status |= ATA_ERR;
1746 }
1747
1748 return status;
1749 }
1750
1751 static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
1752 int no_microcode)
1753 {
1754 struct sata_oxnas_host_priv *hd = ah->private_data;
1755
1756 DPRINTK("ENTER\n");
1757 if (no_microcode) {
1758 u32 reg;
1759
1760 sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
1761 reg = ioread32(hd->core_base + DEVICE_CONTROL);
1762 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1763 iowrite32(reg, hd->core_base + DEVICE_CONTROL);
1764 } else {
1765 /* JBOD uCode */
1766 sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
1767 /* Turn the work around off as it may have been left on by any
1768 * HW-RAID code that we've been working with */
1769 iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
1770 }
1771 }
1772
1773 /**
1774 * Prepare as much as possible for a command without involving anything that is
1775 * shared between ports.
1776 */
1777 static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1778 {
1779 struct sata_oxnas_port_priv *pd;
1780 int port_no = qc->ap->port_no;
1781
1782 /* if the port's not connected, complete now with an error */
1783 if (!sata_oxnas_check_link(qc->ap)) {
1784 ata_port_err(qc->ap,
1785 "port %d not connected completing with error\n",
1786 port_no);
1787 qc->err_mask |= AC_ERR_ATA_BUS;
1788 ata_qc_complete(qc);
1789 }
1790
1791 sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
1792
1793 /* both pio and dma commands use dma */
1794 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1795
1796 /* program the scatterlist into the prd table */
1797 ata_bmdma_qc_prep(qc);
1798
1799 /* point the sgdma controller at the dma request structure */
1800 pd = qc->ap->private_data;
1801
1802 iowrite32(pd->sgdma_request_pa,
1803 pd->sgdma_base + SGDMA_REQUESTPTR);
1804
1805 /* setup the request table */
1806 if (port_no == 0) {
1807 pd->sgdma_request->control =
1808 (qc->dma_dir == DMA_FROM_DEVICE) ?
1809 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1810 } else {
1811 pd->sgdma_request->control =
1812 (qc->dma_dir == DMA_FROM_DEVICE) ?
1813 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1814 }
1815 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1816 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1817 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1818 smp_wmb();
1819
1820 /* tell it to wait */
1821 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1822 }
1823 }
1824
1825 static int sata_oxnas_port_start(struct ata_port *ap)
1826 {
1827 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1828 struct device *dev = ap->host->dev;
1829 struct sata_oxnas_port_priv *pp;
1830 void *mem;
1831 dma_addr_t mem_dma;
1832
1833 DPRINTK("ENTER\n");
1834
1835 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1836 if (!pp)
1837 return -ENOMEM;
1838
1839 pp->port_base = host_priv->port_base +
1840 (ap->port_no ? PORT_SIZE : 0);
1841 pp->dmactl_base = host_priv->dmactl_base +
1842 (ap->port_no ? DMA_CORESIZE : 0);
1843 pp->sgdma_base = host_priv->sgdma_base +
1844 (ap->port_no ? SGDMA_CORESIZE : 0);
1845 pp->core_base = host_priv->core_base;
1846
1847 /* preallocated */
1848 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
1849 DPRINTK("using preallocated DMA\n");
1850 mem_dma = host_priv->dma_base +
1851 (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
1852 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1853 } else {
1854 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1855 GFP_KERNEL);
1856 }
1857 if (!mem)
1858 goto err_ret;
1859
1860 pp->sgdma_request_pa = mem_dma;
1861 pp->sgdma_request = mem;
1862
1863 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1864 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1865
1866 ap->private_data = pp;
1867
1868 sata_oxnas_post_reset_init(ap);
1869
1870 return 0;
1871
1872 err_ret:
1873 kfree(pp);
1874 return -ENOMEM;
1875
1876 }
1877
1878 static void sata_oxnas_port_stop(struct ata_port *ap)
1879 {
1880 struct device *dev = ap->host->dev;
1881 struct sata_oxnas_port_priv *pp = ap->private_data;
1882 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1883
1884 DPRINTK("ENTER\n");
1885 ap->private_data = NULL;
1886 if (host_priv->dma_size) {
1887 iounmap(pp->sgdma_request);
1888 } else {
1889 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1890 pp->sgdma_request, pp->sgdma_request_pa);
1891 }
1892
1893 kfree(pp);
1894 }
1895
1896
1897 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1898 {
1899 uint dev;
1900
1901 /* force to load u-code only once after reset */
1902 sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
1903
1904 /* turn on phy error detection by removing the masks */
1905 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1906
1907 /* enable hotplug event detection */
1908 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1909 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1910 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1911
1912 /* enable interrupts for ports */
1913 sata_oxnas_irq_on(ap);
1914
1915 /* go through all the devices and configure them */
1916 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1917 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1918 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1919 sata_oxnas_dev_config(&(ap->link.device[dev]));
1920 }
1921 }
1922
1923 /* clean up any remaining errors */
1924 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1925 VPRINTK("done\n");
1926 }
1927
1928 /**
1929 * host_stop() is called when the rmmod or hot unplug process begins. The
1930 * hook must stop all hardware interrupts, DMA engines, etc.
1931 *
1932 * @param ap hardware with the registers in
1933 */
1934 static void sata_oxnas_host_stop(struct ata_host *host_set)
1935 {
1936 DPRINTK("\n");
1937 }
1938
1939
1940 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1941 static void sata_oxnas_error_handler(struct ata_port *ap)
1942 {
1943 DPRINTK("Enter port_no %d\n", ap->port_no);
1944 sata_oxnas_freeze_host(ap);
1945
1946 /* If the core is busy here, make it idle */
1947 sata_oxnas_cleanup(ap->host);
1948
1949 ata_std_error_handler(ap);
1950
1951 sata_oxnas_thaw_host(ap);
1952 }
1953
1954 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1955 unsigned long deadline)
1956 {
1957 struct ata_port *ap = link->ap;
1958 struct sata_oxnas_port_priv *pd = ap->private_data;
1959 void __iomem *port_base = pd->port_base;
1960 int rc;
1961
1962 struct ata_taskfile tf;
1963 u32 Command_Reg;
1964
1965 DPRINTK("ENTER\n");
1966
1967 port_base = pd->port_base;
1968
1969 if (ata_link_offline(link)) {
1970 DPRINTK("PHY reports no device\n");
1971 *class = ATA_DEV_NONE;
1972 goto out;
1973 }
1974
1975 /* write value to register */
1976 iowrite32(0, port_base + ORB1);
1977 iowrite32(0, port_base + ORB2);
1978 iowrite32(0, port_base + ORB3);
1979 iowrite32((ap->ctl) << 24, port_base + ORB4);
1980
1981 /* command the core to send a control FIS */
1982 Command_Reg = ioread32(port_base + SATA_COMMAND);
1983 Command_Reg &= ~SATA_OPCODE_MASK;
1984 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1985 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1986 udelay(20); /* FIXME: flush */
1987
1988 /* write value to register */
1989 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
1990
1991 /* command the core to send a control FIS */
1992 Command_Reg &= ~SATA_OPCODE_MASK;
1993 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1994 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1995 udelay(20); /* FIXME: flush */
1996
1997 /* write value to register */
1998 iowrite32((ap->ctl) << 24, port_base + ORB4);
1999
2000 /* command the core to send a control FIS */
2001 Command_Reg &= ~SATA_OPCODE_MASK;
2002 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2003 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2004
2005 msleep(150);
2006
2007 rc = ata_sff_wait_ready(link, deadline);
2008
2009 /* if link is occupied, -ENODEV too is an error */
2010 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2011 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2012 return rc;
2013 }
2014
2015 /* determine by signature whether we have ATA or ATAPI devices */
2016 sata_oxnas_tf_read(ap, &tf);
2017 *class = ata_dev_classify(&tf);
2018
2019 if (*class == ATA_DEV_UNKNOWN)
2020 *class = ATA_DEV_NONE;
2021
2022 out:
2023 DPRINTK("EXIT, class=%u\n", *class);
2024 return 0;
2025 }
2026
2027
2028 int sata_oxnas_init_controller(struct ata_host *host)
2029 {
2030 return 0;
2031 }
2032
2033 /**
2034 * Ref bug-6320
2035 *
2036 * This code is a work around for a DMA hardware bug that will repeat the
2037 * penultimate 8-bytes on some reads. This code will check that the amount
2038 * of data transferred is a multiple of 512 bytes, if not the in it will
2039 * fetch the correct data from a buffer in the SATA core and copy it into
2040 * memory.
2041 *
2042 * @param port SATA port to check and if necessary, correct.
2043 */
2044 static int sata_oxnas_bug_6320_detect(struct ata_port *ap)
2045 {
2046 struct sata_oxnas_port_priv *pd = ap->private_data;
2047 void __iomem *core_base = pd->core_base;
2048 int is_read;
2049 int quads_transferred;
2050 int remainder;
2051 int sector_quads_remaining;
2052 int bug_present = 0;
2053
2054 /* Only want to apply fix to reads */
2055 is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
2056 BIT(CORE_PORT1_DATA_DIR_BIT) :
2057 BIT(CORE_PORT0_DATA_DIR_BIT)));
2058
2059 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
2060 transferred (datacount_port register counts quads transferred) */
2061 quads_transferred =
2062 ioread32(core_base + (ap->port_no ?
2063 DATACOUNT_PORT1 : DATACOUNT_PORT0));
2064
2065 remainder = quads_transferred & 0x7f;
2066 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
2067
2068 if (is_read && (sector_quads_remaining == 2)) {
2069 bug_present = 1;
2070 } else if (sector_quads_remaining) {
2071 if (is_read) {
2072 ata_port_warn(ap, "SATA read fixup cannot deal with "
2073 "%d quads remaining\n",
2074 sector_quads_remaining);
2075 } else {
2076 ata_port_warn(ap, "SATA write fixup of %d quads "
2077 "remaining not supported\n",
2078 sector_quads_remaining);
2079 }
2080 }
2081
2082 return bug_present;
2083 }
2084
2085 /* This port done an interrupt */
2086 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
2087 {
2088 struct ata_queued_cmd *qc;
2089 struct sata_oxnas_port_priv *pd = ap->private_data;
2090 void __iomem *port_base = pd->port_base;
2091
2092 u32 int_status;
2093 unsigned long flags = 0;
2094
2095 DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no,
2096 ioread32(port_base + INT_STATUS));
2097
2098 if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
2099 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
2100 DPRINTK("completing non-ncq cmd\n");
2101
2102 if (qc)
2103 ata_qc_complete(qc);
2104
2105 return;
2106 }
2107
2108 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2109
2110
2111 /* record the port's interrupt */
2112 int_status = ioread32(port_base + INT_STATUS);
2113
2114 /* If there's no command associated with this IRQ, ignore it. We may get
2115 * spurious interrupts when cleaning-up after a failed command, ignore
2116 * these too. */
2117 if (likely(qc)) {
2118 /* get the status before any error cleanup */
2119 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
2120 if (force_error) {
2121 /* Pretend there has been a link error */
2122 qc->err_mask |= AC_ERR_ATA_BUS;
2123 DPRINTK(" ####force error####\n");
2124 }
2125 /* tell libata we're done */
2126 local_irq_save(flags);
2127 sata_oxnas_irq_clear(ap);
2128 local_irq_restore(flags);
2129 ata_qc_complete(qc);
2130 } else {
2131 VPRINTK("Ignoring interrupt, can't find the command tag="
2132 "%d %08x\n", ap->link.active_tag, ap->qc_active);
2133 }
2134
2135 /* maybe a hotplug event */
2136 if (unlikely(int_status & INT_LINK_SERROR)) {
2137 u32 serror;
2138
2139 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
2140 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
2141 ata_ehi_hotplugged(&ap->link.eh_info);
2142 ata_port_freeze(ap);
2143 }
2144 }
2145 }
2146
2147 /**
2148 * irq_handler is the interrupt handling routine registered with the system,
2149 * by libata.
2150 */
2151 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
2152 {
2153 struct ata_host *ah = dev_instance;
2154 struct sata_oxnas_host_priv *hd = ah->private_data;
2155 void __iomem *core_base = hd->core_base;
2156
2157 u32 int_status;
2158 irqreturn_t ret = IRQ_NONE;
2159 u32 port_no;
2160 u32 mask;
2161 int bug_present;
2162
2163 /* loop until there are no more interrupts */
2164 while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
2165 (COREINT_END | (COREINT_END << 1)))) {
2166
2167 /* clear any interrupt */
2168 iowrite32(int_status, core_base + CORE_INT_CLEAR);
2169
2170 /* Only need workaround_bug_6320 for single disk systems as dual
2171 * disk will use uCode which prevents this read underrun problem
2172 * from occurring.
2173 * All single disk systems will use port 0 */
2174 for (port_no = 0; port_no < hd->n_ports; ++port_no) {
2175 /* check the raw end of command interrupt to see if the
2176 * port is done */
2177 mask = (COREINT_END << port_no);
2178 if (!(int_status & mask))
2179 continue;
2180
2181 /* this port had an interrupt, clear it */
2182 iowrite32(mask, core_base + CORE_INT_CLEAR);
2183 /* check for bug 6320 only if no microcode was loaded */
2184 bug_present = (hd->current_ucode == UNKNOWN_MODE) &&
2185 sata_oxnas_bug_6320_detect(ah->ports[port_no]);
2186
2187 sata_oxnas_port_irq(ah->ports[port_no],
2188 bug_present);
2189 ret = IRQ_HANDLED;
2190 }
2191 }
2192
2193 return ret;
2194 }
2195
2196 /*
2197 * scsi mid-layer and libata interface structures
2198 */
2199 static struct scsi_host_template sata_oxnas_sht = {
2200 ATA_NCQ_SHT("sata_oxnas"),
2201 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
2202 .sg_tablesize = SATA_OXNAS_MAX_PRD,
2203 .dma_boundary = ATA_DMA_BOUNDARY,
2204 .unchecked_isa_dma = 0,
2205 };
2206
2207
2208 static struct ata_port_operations sata_oxnas_ops = {
2209 .inherits = &sata_port_ops,
2210 .qc_prep = sata_oxnas_qc_prep,
2211 .qc_issue = sata_oxnas_qc_issue,
2212 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
2213 .qc_new = sata_oxnas_qc_new,
2214 .qc_free = sata_oxnas_qc_free,
2215
2216 .scr_read = sata_oxnas_scr_read,
2217 .scr_write = sata_oxnas_scr_write,
2218
2219 .freeze = sata_oxnas_freeze,
2220 .thaw = sata_oxnas_thaw,
2221 .softreset = sata_oxnas_softreset,
2222 /* .hardreset = sata_oxnas_hardreset, */
2223 .postreset = sata_oxnas_postreset,
2224 .error_handler = sata_oxnas_error_handler,
2225 .post_internal_cmd = sata_oxnas_post_internal_cmd,
2226
2227 .port_start = sata_oxnas_port_start,
2228 .port_stop = sata_oxnas_port_stop,
2229
2230 .host_stop = sata_oxnas_host_stop,
2231 /* .pmp_attach = sata_oxnas_pmp_attach, */
2232 /* .pmp_detach = sata_oxnas_pmp_detach, */
2233 .sff_check_status = sata_oxnas_check_status,
2234 .acquire_hw = sata_oxnas_acquire_hw,
2235 };
2236
2237 static const struct ata_port_info sata_oxnas_port_info = {
2238 .flags = SATA_OXNAS_HOST_FLAGS,
2239 .pio_mask = ATA_PIO4,
2240 .udma_mask = ATA_UDMA6,
2241 .port_ops = &sata_oxnas_ops,
2242 };
2243
2244 static int sata_oxnas_probe(struct platform_device *ofdev)
2245 {
2246 int retval = -ENXIO;
2247 int n_ports = 0;
2248 void __iomem *port_base = NULL;
2249 void __iomem *dmactl_base = NULL;
2250 void __iomem *sgdma_base = NULL;
2251 void __iomem *core_base = NULL;
2252 void __iomem *phy_base = NULL;
2253 struct reset_control *rstc;
2254
2255 struct resource res = {};
2256 struct sata_oxnas_host_priv *host_priv = NULL;
2257 int irq = 0;
2258 struct ata_host *host = NULL;
2259 struct clk *clk = NULL;
2260
2261 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
2262
2263 of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
2264 if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
2265 goto error_exit_with_cleanup;
2266
2267 port_base = of_iomap(ofdev->dev.of_node, 0);
2268 if (!port_base)
2269 goto error_exit_with_cleanup;
2270
2271 dmactl_base = of_iomap(ofdev->dev.of_node, 1);
2272 if (!dmactl_base)
2273 goto error_exit_with_cleanup;
2274
2275 sgdma_base = of_iomap(ofdev->dev.of_node, 2);
2276 if (!sgdma_base)
2277 goto error_exit_with_cleanup;
2278
2279 core_base = of_iomap(ofdev->dev.of_node, 3);
2280 if (!core_base)
2281 goto error_exit_with_cleanup;
2282
2283 phy_base = of_iomap(ofdev->dev.of_node, 4);
2284 if (!phy_base)
2285 goto error_exit_with_cleanup;
2286
2287 host_priv = devm_kzalloc(&ofdev->dev,
2288 sizeof(struct sata_oxnas_host_priv),
2289 GFP_KERNEL);
2290 if (!host_priv)
2291 goto error_exit_with_cleanup;
2292
2293 host_priv->port_base = port_base;
2294 host_priv->dmactl_base = dmactl_base;
2295 host_priv->sgdma_base = sgdma_base;
2296 host_priv->core_base = core_base;
2297 host_priv->phy_base = phy_base;
2298 host_priv->n_ports = n_ports;
2299 host_priv->current_ucode = UNKNOWN_MODE;
2300
2301 if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
2302 host_priv->dma_base = res.start;
2303 host_priv->dma_size = resource_size(&res);
2304 }
2305
2306 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
2307 if (!irq) {
2308 dev_err(&ofdev->dev, "invalid irq from platform\n");
2309 goto error_exit_with_cleanup;
2310 }
2311 host_priv->irq = irq;
2312
2313 clk = of_clk_get(ofdev->dev.of_node, 0);
2314 if (IS_ERR(clk)) {
2315 retval = PTR_ERR(clk);
2316 clk = NULL;
2317 goto error_exit_with_cleanup;
2318 }
2319 host_priv->clk = clk;
2320
2321 rstc = devm_reset_control_get(&ofdev->dev, "sata");
2322 if (IS_ERR(rstc)) {
2323 retval = PTR_ERR(rstc);
2324 goto error_exit_with_cleanup;
2325 }
2326 host_priv->rst_sata = rstc;
2327
2328 rstc = devm_reset_control_get(&ofdev->dev, "link");
2329 if (IS_ERR(rstc)) {
2330 retval = PTR_ERR(rstc);
2331 goto error_exit_with_cleanup;
2332 }
2333 host_priv->rst_link = rstc;
2334
2335 rstc = devm_reset_control_get(&ofdev->dev, "phy");
2336 if (IS_ERR(rstc)) {
2337 retval = PTR_ERR(rstc);
2338 goto error_exit_with_cleanup;
2339 }
2340 host_priv->rst_phy = rstc;
2341
2342 /* allocate host structure */
2343 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);
2344
2345 if (!host) {
2346 retval = -ENOMEM;
2347 goto error_exit_with_cleanup;
2348 }
2349 host->private_data = host_priv;
2350 host->iomap = port_base;
2351
2352 /* initialize core locking and queues */
2353 init_waitqueue_head(&host_priv->fast_wait_queue);
2354 init_waitqueue_head(&host_priv->scsi_wait_queue);
2355 spin_lock_init(&host_priv->phy_lock);
2356 spin_lock_init(&host_priv->core_lock);
2357 host_priv->core_locked = 0;
2358 host_priv->reentrant_port_no = -1;
2359 host_priv->hw_lock_count = 0;
2360 host_priv->direct_lock_count = 0;
2361 host_priv->locker_uid = 0;
2362 host_priv->current_locker_type = SATA_UNLOCKED;
2363 host_priv->isr_arg = NULL;
2364 host_priv->isr_callback = NULL;
2365
2366 /* initialize host controller */
2367 retval = sata_oxnas_init_controller(host);
2368 if (retval)
2369 goto error_exit_with_cleanup;
2370
2371 /*
2372 * Now, register with libATA core, this will also initiate the
2373 * device discovery process, invoking our port_start() handler &
2374 * error_handler() to execute a dummy softreset EH session
2375 */
2376 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
2377 &sata_oxnas_sht);
2378
2379 return 0;
2380
2381 error_exit_with_cleanup:
2382 if (irq)
2383 irq_dispose_mapping(host_priv->irq);
2384 if (clk)
2385 clk_put(clk);
2386 if (host)
2387 ata_host_detach(host);
2388 if (port_base)
2389 iounmap(port_base);
2390 if (sgdma_base)
2391 iounmap(sgdma_base);
2392 if (core_base)
2393 iounmap(core_base);
2394 if (phy_base)
2395 iounmap(phy_base);
2396 return retval;
2397 }
2398
2399
2400 static int sata_oxnas_remove(struct platform_device *ofdev)
2401 {
2402 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
2403 struct sata_oxnas_host_priv *host_priv = host->private_data;
2404
2405 ata_host_detach(host);
2406
2407 irq_dispose_mapping(host_priv->irq);
2408 iounmap(host_priv->port_base);
2409 iounmap(host_priv->sgdma_base);
2410 iounmap(host_priv->core_base);
2411
2412 /* reset Controller, Link and PHY */
2413 reset_control_assert(host_priv->rst_sata);
2414 reset_control_assert(host_priv->rst_link);
2415 reset_control_assert(host_priv->rst_phy);
2416
2417 /* Disable the clock to the SATA block */
2418 clk_disable_unprepare(host_priv->clk);
2419 clk_put(host_priv->clk);
2420
2421 return 0;
2422 }
2423
2424 #ifdef CONFIG_PM
2425 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
2426 {
2427 struct ata_host *host = dev_get_drvdata(&op->dev);
2428
2429 return ata_host_suspend(host, state);
2430 }
2431
2432 static int sata_oxnas_resume(struct platform_device *op)
2433 {
2434 struct ata_host *host = dev_get_drvdata(&op->dev);
2435 int ret;
2436
2437 ret = sata_oxnas_init_controller(host);
2438 if (ret) {
2439 dev_err(&op->dev, "Error initializing hardware\n");
2440 return ret;
2441 }
2442 ata_host_resume(host);
2443 return 0;
2444 }
2445 #endif
2446
2447
2448
2449 static struct of_device_id oxnas_sata_match[] = {
2450 {
2451 .compatible = "plxtech,nas782x-sata",
2452 },
2453 {},
2454 };
2455
2456 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
2457
2458 static struct platform_driver oxnas_sata_driver = {
2459 .driver = {
2460 .name = "oxnas-sata",
2461 .owner = THIS_MODULE,
2462 .of_match_table = oxnas_sata_match,
2463 },
2464 .probe = sata_oxnas_probe,
2465 .remove = sata_oxnas_remove,
2466 #ifdef CONFIG_PM
2467 .suspend = sata_oxnas_suspend,
2468 .resume = sata_oxnas_resume,
2469 #endif
2470 };
2471
2472 module_platform_driver(oxnas_sata_driver);
2473
2474 MODULE_LICENSE("GPL");
2475 MODULE_VERSION("1.0");
2476 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2477 MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");
OpenWrt Source Repository