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oxnas: add copyright header to sata_oxnas
[openwrt/openwrt.git] / target / linux / oxnas / files / drivers / ata / sata_oxnas.c
1 /*
2 * sata_oxnas
3 * A driver to interface the 934 based sata core present in the ox820
4 * with libata and scsi
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/clk.h>
29 #include <linux/reset.h>
30
31 #include <mach/utils.h>
32
33 /* sgdma request structure */
34 struct sgdma_request {
35 volatile u32 qualifier;
36 volatile u32 control;
37 dma_addr_t src_pa;
38 dma_addr_t dst_pa;
39 } __packed __aligned(4);
40
41
42 /* Controller information */
43 enum {
44 SATA_OXNAS_MAX_PRD = 254,
45 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
46 sizeof(struct ata_bmdma_prd) +
47 sizeof(struct sgdma_request),
48 SATA_OXNAS_MAX_PORTS = 1,
49 /** The different Oxsemi SATA core version numbers */
50 SATA_OXNAS_CORE_VERSION = 0x1f3,
51 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
52 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
53 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
54 SATA_OXNAS_QUEUE_DEPTH = 32,
55
56 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
57 };
58
59
60 /*
61 * SATA Port Registers
62 */
63 enum {
64 /** sata host port register offsets */
65 ORB1 = 0x00,
66 ORB2 = 0x04,
67 ORB3 = 0x08,
68 ORB4 = 0x0C,
69 ORB5 = 0x10,
70 MASTER_STATUS = 0x10,
71 FIS_CTRL = 0x18,
72 FIS_DATA = 0x1C,
73 INT_STATUS = 0x30,
74 INT_CLEAR = 0x30,
75 INT_ENABLE = 0x34,
76 INT_DISABLE = 0x38,
77 VERSION = 0x3C,
78 SATA_CONTROL = 0x5C,
79 SATA_COMMAND = 0x60,
80 HID_FEATURES = 0x64,
81 PORT_CONTROL = 0x68,
82 DRIVE_CONTROL = 0x6C,
83 /** These registers allow access to the link layer registers
84 that reside in a different clock domain to the processor bus */
85 LINK_DATA = 0x70,
86 LINK_RD_ADDR = 0x74,
87 LINK_WR_ADDR = 0x78,
88 LINK_CONTROL = 0x7C,
89 /* window control */
90 WIN1LO = 0x80,
91 WIN1HI = 0x84,
92 WIN2LO = 0x88,
93 WIN2HI = 0x8C,
94 WIN0_CONTROL = 0x90,
95
96 };
97
98 /** sata port register bits */
99 enum{
100 /**
101 * commands to issue in the master status to tell it to move shadow ,
102 * registers to the actual device ,
103 */
104 SATA_OPCODE_MASK = 0x00000007,
105 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
106 CMD_WRITE_TO_ORB_REGS = 0x2,
107 CMD_SYNC_ESCAPE = 0x7,
108 CMD_CORE_BUSY = (1 << 7),
109 CMD_DRIVE_SELECT_SHIFT = 12,
110 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
111
112 /** interrupt bits */
113 INT_END_OF_CMD = 1 << 0,
114 INT_LINK_SERROR = 1 << 1,
115 INT_ERROR = 1 << 2,
116 INT_LINK_IRQ = 1 << 3,
117 INT_REG_ACCESS_ERR = 1 << 7,
118 INT_BIST_FIS = 1 << 11,
119 INT_MASKABLE = INT_END_OF_CMD |
120 INT_LINK_SERROR |
121 INT_ERROR |
122 INT_LINK_IRQ |
123 INT_REG_ACCESS_ERR |
124 INT_BIST_FIS,
125 INT_WANT = INT_END_OF_CMD |
126 INT_LINK_SERROR |
127 INT_REG_ACCESS_ERR |
128 INT_ERROR,
129 INT_ERRORS = INT_LINK_SERROR |
130 INT_REG_ACCESS_ERR |
131 INT_ERROR,
132
133 /** raw interrupt bits, unmaskable, but do not generate interrupts */
134 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
135 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
136 RAW_ERROR = INT_ERROR << 16,
137 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
138 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
139 RAW_BIST_FIS = INT_BIST_FIS << 16,
140 RAW_WANT = INT_WANT << 16,
141 RAW_ERRORS = INT_ERRORS << 16,
142
143 /**
144 * variables to write to the device control register to set the current
145 * device, ie. master or slave.
146 */
147 DR_CON_48 = 2,
148 DR_CON_28 = 0,
149
150 SATA_CTL_ERR_MASK = 0x00000016,
151
152 };
153
154 /* ATA SGDMA register offsets */
155 enum {
156 SGDMA_CONTROL = 0x0,
157 SGDMA_STATUS = 0x4,
158 SGDMA_REQUESTPTR = 0x8,
159 SGDMA_RESETS = 0xC,
160 SGDMA_CORESIZE = 0x10,
161 };
162
163 enum {
164 /* see DMA core docs for the values. Out means from memory (bus A) out
165 * to disk (bus B) */
166 SGDMA_REQCTL0OUT = 0x0497c03d,
167 /* burst mode disabled when no micro code used */
168 SGDMA_REQCTL0IN = 0x0493a3c1,
169 SGDMA_REQCTL1OUT = 0x0497c07d,
170 SGDMA_REQCTL1IN = 0x0497a3c5,
171 SGDMA_CONTROL_NOGO = 0x3e,
172 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
173 SGDMA_ERRORMASK = 0x3f,
174 SGDMA_BUSY = 0x80,
175
176 SGDMA_RESETS_CTRL = 1 << 0,
177 SGDMA_RESETS_ARBT = 1 << 1,
178 SGDMA_RESETS_AHB = 1 << 2,
179 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
180 SGDMA_RESETS_ARBT |
181 SGDMA_RESETS_AHB,
182
183 /* Final EOTs */
184 SGDMA_REQQUAL = 0x00220001,
185
186 };
187
188 /** SATA core register offsets */
189 enum {
190 DM_DBG1 = 0x000,
191 RAID_SET = 0x004,
192 DM_DBG2 = 0x008,
193 DATACOUNT_PORT0 = 0x010,
194 DATACOUNT_PORT1 = 0x014,
195 CORE_INT_STATUS = 0x030,
196 CORE_INT_CLEAR = 0x030,
197 CORE_INT_ENABLE = 0x034,
198 CORE_INT_DISABLE = 0x038,
199 CORE_REBUILD_ENABLE = 0x050,
200 CORE_FAILED_PORT_R = 0x054,
201 DEVICE_CONTROL = 0x068,
202 EXCESS = 0x06C,
203 RAID_SIZE_LOW = 0x070,
204 RAID_SIZE_HIGH = 0x074,
205 PORT_ERROR_MASK = 0x078,
206 IDLE_STATUS = 0x07C,
207 RAID_CONTROL = 0x090,
208 DATA_PLANE_CTRL = 0x0AC,
209 CORE_DATAPLANE_STAT = 0x0b8,
210 PROC_PC = 0x100,
211 CONFIG_IN = 0x3d8,
212 PROC_START = 0x3f0,
213 PROC_RESET = 0x3f4,
214 UCODE_STORE = 0x1000,
215 RAID_WP_BOT_LOW = 0x1FF0,
216 RAID_WP_BOT_HIGH = 0x1FF4,
217 RAID_WP_TOP_LOW = 0x1FF8,
218 RAID_WP_TOP_HIGH = 0x1FFC,
219 DATA_MUX_RAM0 = 0x8000,
220 DATA_MUX_RAM1 = 0xA000,
221 };
222
223 enum {
224 /* Sata core debug1 register bits */
225 CORE_PORT0_DATA_DIR_BIT = 20,
226 CORE_PORT1_DATA_DIR_BIT = 21,
227 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
228 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
229
230 /** sata core control register bits */
231 SCTL_CLR_ERR = 0x00003016,
232 RAID_CLR_ERR = 0x0000011e,
233
234 /* Interrupts direct from the ports */
235 NORMAL_INTS_WANTED = 0x00000303,
236
237 /* shift these left by port number */
238 COREINT_HOST = 0x00000001,
239 COREINT_END = 0x00000100,
240 CORERAW_HOST = COREINT_HOST << 16,
241 CORERAW_END = COREINT_END << 16,
242
243 /* Interrupts from the RAID controller only */
244 RAID_INTS_WANTED = 0x00008300,
245
246 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
247 IDLE_CORES = (1 << 18) | (1 << 19),
248
249 /* Data plane control error-mask mask and bit, these bit in the data
250 * plane control mask out errors from the ports that prevent the SGDMA
251 * care from sending an interrupt */
252 DPC_ERROR_MASK = 0x00000300,
253 DPC_ERROR_MASK_BIT = 0x00000100,
254 /* enable jbod micro-code */
255 DPC_JBOD_UCODE = 1 << 0,
256 DPC_FIS_SWCH = 1 << 1,
257
258 /** Device Control register bits */
259 DEVICE_CONTROL_DMABT = 1 << 4,
260 DEVICE_CONTROL_ABORT = 1 << 2,
261 DEVICE_CONTROL_PAD = 1 << 3,
262 DEVICE_CONTROL_PADPAT = 1 << 16,
263 DEVICE_CONTROL_PRTRST = 1 << 8,
264 DEVICE_CONTROL_RAMRST = 1 << 12,
265 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
266
267 /** oxsemi HW raid modes */
268 OXNASSATA_NOTRAID = 0,
269 OXNASSATA_RAID0 = 1,
270 OXNASSATA_RAID1 = 2,
271 /** OX820 specific HW-RAID register values */
272 RAID_TWODISKS = 3,
273 UNKNOWN_MODE = ~0,
274 };
275
276 /* SATA PHY Registers */
277 enum {
278 PHY_STAT = 0x00,
279 PHY_DATA = 0x04,
280 };
281
282 enum {
283 STAT_READ_VALID = (1 << 21),
284 STAT_CR_ACK = (1 << 20),
285 STAT_CR_READ = (1 << 19),
286 STAT_CR_WRITE = (1 << 18),
287 STAT_CAP_DATA = (1 << 17),
288 STAT_CAP_ADDR = (1 << 16),
289
290 STAT_ACK_ANY = STAT_CR_ACK |
291 STAT_CR_READ |
292 STAT_CR_WRITE |
293 STAT_CAP_DATA |
294 STAT_CAP_ADDR,
295
296 CR_READ_ENABLE = (1 << 16),
297 CR_WRITE_ENABLE = (1 << 17),
298 CR_CAP_DATA = (1 << 18),
299 };
300
301 enum {
302 /* Link layer registers */
303 SERROR_IRQ_MASK = 5,
304 };
305
306 enum {
307 OXNAS_SATA_SOFTRESET = 1,
308 OXNAS_SATA_REINIT = 2,
309 };
310
311 enum {
312 OXNAS_SATA_UCODE_RAID0,
313 OXNAS_SATA_UCODE_RAID1,
314 OXNAS_SATA_UCODE_JBOD,
315 OXNAS_SATA_UCODE_NONE,
316 };
317
318 struct sata_oxnas_host_priv {
319 void __iomem *port_base[SATA_OXNAS_MAX_PORTS];
320 void __iomem *sgdma_base[SATA_OXNAS_MAX_PORTS];
321 void __iomem *core_base;
322 void __iomem *phy_base;
323 dma_addr_t dma_base;
324 void __iomem *dma_base_va;
325 size_t dma_size;
326 int irq;
327 u32 port_in_eh;
328 struct clk *clk;
329 struct reset_control *rst_sata;
330 struct reset_control *rst_link;
331 struct reset_control *rst_phy;
332 };
333
334
335 struct sata_oxnas_port_priv {
336 void __iomem *port_base;
337 void __iomem *sgdma_base;
338 void __iomem *core_base;
339 struct sgdma_request *sgdma_request;
340 dma_addr_t sgdma_request_pa;
341 };
342
343 static u8 sata_oxnas_check_status(struct ata_port *ap);
344 static int sata_oxnas_cleanup(struct ata_host *ah);
345 static void sata_oxnas_tf_load(struct ata_port *ap,
346 const struct ata_taskfile *tf);
347 static void sata_oxnas_irq_on(struct ata_port *ap);
348 static void sata_oxnas_post_reset_init(struct ata_port *ap);
349
350 /* ??????????????????????????????????? */
351 static void wait_cr_ack(void __iomem *phy_base)
352 {
353 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
354 ; /* wait for an ack bit to be set */
355 }
356
357 static u16 read_cr(void __iomem *phy_base, u16 address)
358 {
359 iowrite32((u32)address, phy_base + PHY_STAT);
360 wait_cr_ack(phy_base);
361 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
362 wait_cr_ack(phy_base);
363 return (u16)ioread32(phy_base + PHY_STAT);
364 }
365
366 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
367 {
368 iowrite32((u32)address, phy_base + PHY_STAT);
369 wait_cr_ack(phy_base);
370 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
371 wait_cr_ack(phy_base);
372 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
373 wait_cr_ack(phy_base);
374 }
375
376 #define PH_GAIN 2
377 #define FR_GAIN 3
378 #define PH_GAIN_OFFSET 6
379 #define FR_GAIN_OFFSET 8
380 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
381 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
382 #define USE_INT_SETTING (1<<5)
383
384 void workaround5458(struct ata_host *ah)
385 {
386 struct sata_oxnas_host_priv *hd = ah->private_data;
387 void __iomem *phy_base = hd->phy_base;
388 u16 rx_control;
389 unsigned i;
390
391 for (i = 0; i < 2; i++) {
392 rx_control = read_cr(phy_base, 0x201d + (i << 8));
393 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
394 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
395 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
396 write_cr(phy_base, rx_control, 0x201d+(i<<8));
397 }
398 }
399
400 /**
401 * allows access to the link layer registers
402 * @param link_reg the link layer register to access (oxsemi indexing ie
403 * 00 = static config, 04 = phy ctrl)
404 */
405 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
406 {
407 struct sata_oxnas_port_priv *port_priv = ap->private_data;
408 void __iomem *port_base = port_priv->port_base;
409 u32 patience;
410
411 DPRINTK("[0x%02x]->0x%08x\n", link_reg, val);
412
413 iowrite32(val, port_base + LINK_DATA);
414
415 /* accessed twice as a work around for a bug in the SATA abp bridge
416 * hardware (bug 6828) */
417 iowrite32(link_reg , port_base + LINK_WR_ADDR);
418 ioread32(port_base + LINK_WR_ADDR);
419
420 for (patience = 0x100000; patience > 0; --patience) {
421 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
422 break;
423 }
424 }
425
426 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
427 u32 val)
428 {
429 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
430 return 0;
431 }
432
433 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
434 u32 val)
435 {
436 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
437 }
438
439 /* FIXME lock */
440 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
441 {
442 struct sata_oxnas_port_priv *pd = ap->private_data;
443 void __iomem *port_base = pd->port_base;
444 u32 result;
445 u32 patience;
446
447 /* accessed twice as a work around for a bug in the SATA abp bridge
448 * hardware (bug 6828) */
449 iowrite32(link_reg, port_base + LINK_RD_ADDR);
450 ioread32(port_base + LINK_RD_ADDR);
451
452 for (patience = 0x100000; patience > 0; --patience) {
453 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
454 break;
455 }
456 if (patience == 0)
457 DPRINTK("link read timed out\n");
458
459 result = readl(port_base + LINK_DATA);
460
461 return result;
462 }
463
464 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
465 u32 *val)
466 {
467 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
468 return 0;
469 }
470
471 static int sata_oxnas_scr_read(struct ata_link *link,
472 unsigned int sc_reg, u32 *val)
473 {
474
475 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
476 }
477
478 /**
479 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
480 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
481 * in the SATA core.
482 *
483 * @param ap hardware with the registers in
484 */
485 static void sata_oxnas_irq_clear(struct ata_port *ap)
486 {
487 struct sata_oxnas_port_priv *port_priv = ap->private_data;
488
489 /* clear pending interrupts */
490 iowrite32(~0, port_priv->port_base + INT_CLEAR);
491 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
492 }
493
494 /**
495 * qc_issue is used to make a command active, once the hardware and S/G tables
496 * have been prepared. IDE BMDMA drivers use the helper function
497 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
498 * drivers roll their own ->qc_issue implementation, using this as the
499 * "issue new ATA command to hardware" hook.
500 * @param qc the queued command to issue
501 */
502 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
503 {
504 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
505 void __iomem *port_base = pd->port_base;
506 void __iomem *core_base = pd->core_base;
507 int port_no = qc->ap->port_no;
508 u32 reg;
509
510 /* check the core is idle */
511 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
512 int count = 0;
513
514 DPRINTK("core busy for a command on port %d\n",
515 qc->ap->port_no);
516 do {
517 mdelay(1);
518 if (++count > 100) {
519 DPRINTK("core busy for a command on port %d\n",
520 qc->ap->port_no);
521 /* CrazyDumpDebug(); */
522 sata_oxnas_cleanup(qc->ap->host);
523 }
524 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
525 }
526
527 /* enable passing of error signals to DMA sub-core by clearing the
528 * appropriate bit (all transfers are on dma channel 0) */
529 reg = ioread32(core_base + DATA_PLANE_CTRL);
530 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
531 iowrite32(reg, core_base + DATA_PLANE_CTRL);
532
533 /* Disable all interrupts for ports and RAID controller */
534 iowrite32(~0, port_base + INT_DISABLE);
535
536 /* Disable all interrupts for core */
537 iowrite32(~0, core_base + CORE_INT_DISABLE);
538 wmb();
539
540 /* Load the command settings into the orb registers */
541 sata_oxnas_tf_load(qc->ap, &qc->tf);
542
543 /* both pio and dma commands use dma */
544 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
545 /* Start the DMA */
546 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
547 wmb();
548 }
549
550 /* enable End of command interrupt */
551 iowrite32(INT_WANT, port_base + INT_ENABLE);
552 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
553 wmb();
554
555 /* Start the command */
556 reg = ioread32(port_base + SATA_COMMAND);
557 reg &= ~SATA_OPCODE_MASK;
558 reg |= CMD_WRITE_TO_ORB_REGS;
559 iowrite32(reg , port_base + SATA_COMMAND);
560 wmb();
561
562 return 0;
563 }
564
565 /**
566 * Will schedule the libATA error handler on the premise that there has
567 * been a hotplug event on the port specified
568 */
569 void sata_oxnas_checkforhotplug(struct ata_port *ap)
570 {
571 DPRINTK("ENTER\n");
572
573 ata_ehi_hotplugged(&ap->link.eh_info);
574 ata_port_freeze(ap);
575 }
576
577
578 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
579 {
580 struct sata_oxnas_host_priv *hd = ah->private_data;
581
582 smp_rmb();
583 return hd->port_in_eh;
584 }
585
586 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
587 {
588 struct sata_oxnas_port_priv *pd = ap->private_data;
589
590 return ioread32(pd->port_base + SATA_COMMAND) & CMD_CORE_BUSY;
591 }
592
593 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
594 {
595 struct sata_oxnas_port_priv *pd = ap->private_data;
596
597 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
598 }
599
600
601 /**
602 * Turns on the cores clock and resets it
603 */
604 static void sata_oxnas_reset_core(struct ata_host *ah)
605 {
606 struct sata_oxnas_host_priv *host_priv = ah->private_data;
607
608 DPRINTK("ENTER\n");
609 clk_prepare_enable(host_priv->clk);
610
611 reset_control_assert(host_priv->rst_sata);
612 reset_control_assert(host_priv->rst_link);
613 reset_control_assert(host_priv->rst_phy);
614
615 udelay(50);
616
617 /* un-reset the PHY, then Link and Controller */
618 reset_control_deassert(host_priv->rst_phy);
619 udelay(50);
620
621 reset_control_deassert(host_priv->rst_sata);
622 reset_control_deassert(host_priv->rst_link);
623 udelay(50);
624
625 workaround5458(ah);
626 /* tune for sata compatability */
627 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
628
629 /* each port in turn */
630 sata_oxnas_link_write(ah->ports[0], 0x70, 0x55629);
631 udelay(50);
632 }
633
634
635 /**
636 * Called after an identify device command has worked out what kind of device
637 * is on the port
638 *
639 * @param port The port to configure
640 * @param pdev The hardware associated with controlling the port
641 */
642 static void sata_oxnas_dev_config(struct ata_device *pdev)
643 {
644 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
645 void __iomem *port_base = pd->port_base;
646 u32 reg;
647
648 DPRINTK("ENTER\n");
649 /* Set the bits to put the port into 28 or 48-bit node */
650 reg = ioread32(port_base + DRIVE_CONTROL);
651 reg &= ~3;
652 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
653 iowrite32(reg, port_base + DRIVE_CONTROL);
654
655 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
656 if (pdev->flags & ATA_DFLAG_LBA48) {
657 reg = ioread32(port_base + PORT_CONTROL);
658 reg |= 2;
659 iowrite32(reg, port_base + PORT_CONTROL);
660 }
661 }
662 /**
663 * called to write a taskfile into the ORB registers
664 * @param ap hardware with the registers in
665 * @param tf taskfile to write to the registers
666 */
667 static void sata_oxnas_tf_load(struct ata_port *ap,
668 const struct ata_taskfile *tf)
669 {
670 u32 count = 0;
671 u32 Orb1 = 0;
672 u32 Orb2 = 0;
673 u32 Orb3 = 0;
674 u32 Orb4 = 0;
675 u32 Command_Reg;
676
677 struct sata_oxnas_port_priv *port_priv = ap->private_data;
678 void __iomem *port_base = port_priv->port_base;
679 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
680
681 /* wait a maximum of 10ms for the core to be idle */
682 do {
683 Command_Reg = ioread32(port_base + SATA_COMMAND);
684 if (!(Command_Reg & CMD_CORE_BUSY))
685 break;
686 count++;
687 udelay(50);
688 } while (count < 200);
689
690 /* check if the ctl register has interrupts disabled or enabled and
691 * modify the interrupt enable registers on the ata core as required */
692 if (tf->ctl & ATA_NIEN) {
693 /* interrupts disabled */
694 u32 mask = (COREINT_END << ap->port_no);
695
696 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
697 sata_oxnas_irq_clear(ap);
698 } else {
699 sata_oxnas_irq_on(ap);
700 }
701
702 Orb2 |= (tf->command) << 24;
703
704 /* write 48 or 28 bit tf parameters */
705 if (is_addr) {
706 /* set LBA bit as it's an address */
707 Orb1 |= (tf->device & ATA_LBA) << 24;
708
709 if (tf->flags & ATA_TFLAG_LBA48) {
710 Orb1 |= ATA_LBA << 24;
711 Orb2 |= (tf->hob_nsect) << 8;
712 Orb3 |= (tf->hob_lbal) << 24;
713 Orb4 |= (tf->hob_lbam) << 0;
714 Orb4 |= (tf->hob_lbah) << 8;
715 Orb4 |= (tf->hob_feature) << 16;
716 } else {
717 Orb3 |= (tf->device & 0xf) << 24;
718 }
719
720 /* write 28-bit lba */
721 Orb2 |= (tf->nsect) << 0;
722 Orb2 |= (tf->feature) << 16;
723 Orb3 |= (tf->lbal) << 0;
724 Orb3 |= (tf->lbam) << 8;
725 Orb3 |= (tf->lbah) << 16;
726 Orb4 |= (tf->ctl) << 24;
727 }
728
729 if (tf->flags & ATA_TFLAG_DEVICE)
730 Orb1 |= (tf->device) << 24;
731
732 ap->last_ctl = tf->ctl;
733
734 /* write values to registers */
735 iowrite32(Orb1, port_base + ORB1);
736 iowrite32(Orb2, port_base + ORB2);
737 iowrite32(Orb3, port_base + ORB3);
738 iowrite32(Orb4, port_base + ORB4);
739 }
740
741
742 void sata_oxnas_set_mode(struct ata_port *ap, u32 mode, u32 force)
743 {
744 struct sata_oxnas_port_priv *port_priv = ap->private_data;
745 void __iomem *core_base = port_priv->core_base;
746
747 unsigned int *src;
748 void __iomem *dst;
749 unsigned int progmicrocode = 0;
750 unsigned int changeparameters = 0;
751 static u32 previous_mode = UNKNOWN_MODE;
752
753 /* these micro-code programs _should_ include the version word */
754
755 /* JBOD */
756 static const unsigned int jbod[] = {
757 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
758 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
759 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
760 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
761 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
762 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
763 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
764 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
765 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
766 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
767 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
768 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
769 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
770 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
771 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
772 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
773 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
774 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
775 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
776 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
777 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
778 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
779 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
780 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
781 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
782 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
783 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
784 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
785 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
786 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
787 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
788 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
789 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
790 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
791 0x00718908, 0x0208A206, 0x00EE0005, ~0
792 };
793
794 /* Bi-Modal RAID-0/1 */
795 static const unsigned int raid[] = {
796 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
797 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
798 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
799 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
800 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
801 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
802 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
803 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
804 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
805 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
806 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
807 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
808 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
809 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
810 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
811 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
812 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
813 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
814 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
815 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
816 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
817 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
818 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
819 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
820 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
821 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
822 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
823 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
824 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
825 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
826 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
827 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
828 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
829 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
830 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
831 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
832 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
833 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
834 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
835 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
836 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
837 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
838 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
839 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
840 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
841 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
842 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
843 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
844 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
845 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
846 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
847 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
848 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
849 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
850 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
851 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
852 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
853 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
854 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
855 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
856 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
857 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
858 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
859 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
860 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
861 0x02400000, ~0
862 };
863
864 if (force)
865 previous_mode = UNKNOWN_MODE;
866
867 if (mode == previous_mode)
868 return;
869
870 /* decide what needs to be done using the STD in my logbook */
871 switch (previous_mode) {
872 case OXNASSATA_RAID1:
873 switch (mode) {
874 case OXNASSATA_RAID0:
875 changeparameters = 1;
876 break;
877 case OXNASSATA_NOTRAID:
878 changeparameters = 1;
879 progmicrocode = 1;
880 break;
881 }
882 break;
883 case OXNASSATA_RAID0:
884 switch (mode) {
885 case OXNASSATA_RAID1:
886 changeparameters = 1;
887 break;
888 case OXNASSATA_NOTRAID:
889 changeparameters = 1;
890 progmicrocode = 1;
891 break;
892 }
893 break;
894 case OXNASSATA_NOTRAID:
895 case UNKNOWN_MODE:
896 changeparameters = 1;
897 progmicrocode = 1;
898 break;
899 }
900
901 /* no need to reprogram everything if already in the right mode */
902 if (progmicrocode) {
903 /* reset micro-code processor */
904 iowrite32(1, core_base + PROC_RESET);
905 wmb();
906
907 /* select micro-code */
908 switch (mode) {
909 case OXNASSATA_RAID1:
910 case OXNASSATA_RAID0:
911 VPRINTK("Loading RAID micro-code\n");
912 src = (unsigned int *)&raid[1];
913 break;
914 case OXNASSATA_NOTRAID:
915 VPRINTK("Loading JBOD micro-code\n");
916 src = (unsigned int *)&jbod[1];
917 break;
918 default:
919 BUG();
920 break;
921 }
922
923 /* load micro code */
924 dst = core_base + UCODE_STORE;
925 while (*src != ~0) {
926 iowrite32(*src, dst);
927 src++;
928 dst += sizeof(*src);
929 }
930 wmb();
931 }
932
933 if (changeparameters) {
934 u32 reg;
935 /* set other mode dependent flags */
936 switch (mode) {
937 case OXNASSATA_RAID1:
938 /* clear JBOD mode */
939 reg = ioread32(core_base + DATA_PLANE_CTRL);
940 reg |= DPC_JBOD_UCODE;
941 reg &= ~DPC_FIS_SWCH;
942 iowrite32(reg, core_base + DATA_PLANE_CTRL);
943 wmb();
944
945 /* set the hardware up for RAID-1 */
946 iowrite32(0, core_base + RAID_WP_BOT_LOW);
947 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
948 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
949 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
950 iowrite32(0, core_base + RAID_SIZE_LOW);
951 iowrite32(0, core_base + RAID_SIZE_HIGH);
952 wmb();
953 break;
954 case OXNASSATA_RAID0:
955 /* clear JBOD mode */
956 reg = ioread32(core_base + DATA_PLANE_CTRL);
957 reg |= DPC_JBOD_UCODE;
958 reg &= ~DPC_FIS_SWCH;
959 iowrite32(reg, core_base + DATA_PLANE_CTRL);
960 wmb();
961
962 /* set the hardware up for RAID-1 */
963 iowrite32(0, core_base + RAID_WP_BOT_LOW);
964 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
965 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
966 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
967 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
968 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
969 wmb();
970 break;
971 case OXNASSATA_NOTRAID:
972 /* enable jbod mode */
973 reg = ioread32(core_base + DATA_PLANE_CTRL);
974 reg &= ~DPC_JBOD_UCODE;
975 reg |= DPC_FIS_SWCH;
976 iowrite32(reg, core_base + DATA_PLANE_CTRL);
977 wmb();
978
979 /* start micro-code processor*/
980 iowrite32(1, core_base + PROC_START);
981 break;
982 default:
983 break;
984 }
985 }
986
987 previous_mode = mode;
988 }
989
990 /**
991 * sends a sync-escape if there is a link present
992 */
993 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
994 {
995 struct sata_oxnas_port_priv *pd = ap->private_data;
996 u32 reg;
997
998 /* read the SSTATUS register and only send a sync escape if there is a
999 * link active */
1000 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
1001 reg = ioread32(pd->port_base + SATA_COMMAND);
1002 reg &= ~SATA_OPCODE_MASK;
1003 reg |= CMD_SYNC_ESCAPE;
1004 iowrite32(reg, pd->port_base + SATA_COMMAND);
1005 }
1006 }
1007
1008 /* clears errors */
1009 static inline void sata_oxnas_clear_CS_error(u32 *base)
1010 {
1011 u32 reg;
1012
1013 reg = ioread32(base + SATA_CONTROL);
1014 reg &= SATA_CTL_ERR_MASK;
1015 iowrite32(reg, base + SATA_CONTROL);
1016 }
1017
1018 /**
1019 * Clears the error caused by the core's registers being accessed when the
1020 * core is busy.
1021 */
1022 static inline void sata_oxnas_clear_reg_access_error(u32 *base)
1023 {
1024 u32 reg;
1025
1026 reg = ioread32(base + INT_STATUS);
1027
1028 DPRINTK("ENTER\n");
1029 if (reg & INT_REG_ACCESS_ERR) {
1030 printk(KERN_INFO "clearing register access error\n");
1031 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1032 }
1033 if (reg & INT_REG_ACCESS_ERR)
1034 printk(KERN_INFO "register access error didn't clear\n");
1035 }
1036
1037 /**
1038 * Clean up all the state machines in the sata core.
1039 * @return post cleanup action required
1040 */
1041 static int sata_oxnas_cleanup(struct ata_host *ah)
1042 {
1043 int actions_required = 0;
1044
1045 printk(KERN_INFO "ox820sata: reseting SATA core\n");
1046
1047 /* core not recovering, reset it */
1048 mdelay(5);
1049 sata_oxnas_reset_core(ah);
1050 mdelay(5);
1051 actions_required |= OXNAS_SATA_REINIT;
1052 /* Perform any SATA core re-initialisation after reset post reset init
1053 * needs to be called for both ports as there's one reset for both
1054 * ports */
1055
1056 sata_oxnas_post_reset_init(ah->ports[0]);
1057
1058 return actions_required;
1059 }
1060
1061 void sata_oxnas_freeze_host(struct ata_port *ap)
1062 {
1063 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1064
1065 DPRINTK("ENTER\n");
1066 hd->port_in_eh |= BIT(ap->port_no);
1067 smp_wmb();
1068 }
1069
1070 void sata_oxnas_thaw_host(struct ata_port *ap)
1071 {
1072 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1073
1074 DPRINTK("ENTER\n");
1075 hd->port_in_eh &= ~BIT(ap->port_no);
1076 smp_wmb();
1077 }
1078
1079 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1080 {
1081 DPRINTK("ENTER\n");
1082 /* If the core is busy here, make it idle */
1083 if (qc->flags & ATA_QCFLAG_FAILED)
1084 sata_oxnas_cleanup(qc->ap->host);
1085 }
1086
1087
1088 /**
1089 * turn on the interrupts
1090 *
1091 * @param ap Hardware with the registers in
1092 */
1093 static void sata_oxnas_irq_on(struct ata_port *ap)
1094 {
1095 struct sata_oxnas_port_priv *pd = ap->private_data;
1096 u32 mask = (COREINT_END << ap->port_no);
1097
1098 /* Clear pending interrupts */
1099 iowrite32(~0, pd->port_base + INT_CLEAR);
1100 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1101 wmb();
1102
1103 /* enable End of command interrupt */
1104 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1105 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1106 }
1107
1108
1109 /** @return true if the port has a cable connected */
1110 int sata_oxnas_check_link(struct ata_port *ap)
1111 {
1112 int reg;
1113
1114 sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
1115 /* Check for the cable present indicated by SCR status bit-0 set */
1116 return reg & 0x1;
1117 }
1118
1119 /**
1120 * ata_std_postreset - standard postreset callback
1121 * @link: the target ata_link
1122 * @classes: classes of attached devices
1123 *
1124 * This function is invoked after a successful reset. Note that
1125 * the device might have been reset more than once using
1126 * different reset methods before postreset is invoked.
1127 *
1128 * LOCKING:
1129 * Kernel thread context (may sleep)
1130 */
1131 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1132 {
1133 struct ata_port *ap = link->ap;
1134
1135 unsigned int dev;
1136
1137 DPRINTK("ENTER\n");
1138 ata_std_postreset(link, classes);
1139
1140 /* turn on phy error detection by removing the masks */
1141 sata_oxnas_link_write(ap , 0x0c, 0x30003);
1142
1143 /* bail out if no device is present */
1144 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1145 DPRINTK("EXIT, no device\n");
1146 return;
1147 }
1148
1149 /* go through all the devices and configure them */
1150 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1151 if (ap->link.device[dev].class == ATA_DEV_ATA)
1152 sata_oxnas_dev_config(&(ap->link.device[dev]));
1153 }
1154
1155 DPRINTK("EXIT\n");
1156 }
1157
1158 /**
1159 * Called to read the hardware registers / DMA buffers, to
1160 * obtain the current set of taskfile register values.
1161 * @param ap hardware with the registers in
1162 * @param tf taskfile to read the registers into
1163 */
1164 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1165 {
1166 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1167 void __iomem *port_base = port_priv->port_base;
1168 /* read the orb registers */
1169 u32 Orb1 = ioread32(port_base + ORB1);
1170 u32 Orb2 = ioread32(port_base + ORB2);
1171 u32 Orb3 = ioread32(port_base + ORB3);
1172 u32 Orb4 = ioread32(port_base + ORB4);
1173
1174 /* read common 28/48 bit tf parameters */
1175 tf->device = (Orb1 >> 24);
1176 tf->nsect = (Orb2 >> 0);
1177 tf->feature = (Orb2 >> 16);
1178 tf->command = sata_oxnas_check_status(ap);
1179
1180 /* read 48 or 28 bit tf parameters */
1181 if (tf->flags & ATA_TFLAG_LBA48) {
1182 tf->hob_nsect = (Orb2 >> 8);
1183 tf->lbal = (Orb3 >> 0);
1184 tf->lbam = (Orb3 >> 8);
1185 tf->lbah = (Orb3 >> 16);
1186 tf->hob_lbal = (Orb3 >> 24);
1187 tf->hob_lbam = (Orb4 >> 0);
1188 tf->hob_lbah = (Orb4 >> 8);
1189 /* feature ext and control are write only */
1190 } else {
1191 /* read 28-bit lba */
1192 tf->lbal = (Orb3 >> 0);
1193 tf->lbam = (Orb3 >> 8);
1194 tf->lbah = (Orb3 >> 16);
1195 }
1196 }
1197
1198 /**
1199 * Read a result task-file from the sata core registers.
1200 */
1201 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1202 {
1203 /* Read the most recently received FIS from the SATA core ORB registers
1204 and convert to an ATA taskfile */
1205 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1206 return true;
1207 }
1208
1209 /**
1210 * Reads the Status ATA shadow register from hardware.
1211 *
1212 * @return The status register
1213 */
1214 static u8 sata_oxnas_check_status(struct ata_port *ap)
1215 {
1216 u32 Reg;
1217 u8 status;
1218 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1219 void __iomem *port_base = port_priv->port_base;
1220
1221 /* read byte 3 of Orb2 register */
1222 status = ioread32(port_base + ORB2) >> 24;
1223
1224 /* check for the drive going missing indicated by SCR status bits
1225 * 0-3 = 0 */
1226 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1227
1228 if (!(Reg & 0x1)) {
1229 status |= ATA_DF;
1230 status |= ATA_ERR;
1231 }
1232
1233 return status;
1234 }
1235
1236 /**
1237 * Prepare as much as possible for a command without involving anything that is
1238 * shared between ports.
1239 */
1240 static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1241 {
1242 struct sata_oxnas_port_priv *pd;
1243 int port_no = qc->ap->port_no;
1244
1245 /* if the port's not connected, complete now with an error */
1246 /*
1247 if (!sata_oxnas_check_link(qc->ap)) {
1248 printk(KERN_ERR "port %d not connected completing with error\n",
1249 qc->ap->port_no);
1250 qc->err_mask |= AC_ERR_ATA_BUS;
1251 ata_qc_complete(qc);
1252 }
1253 */
1254 /* both pio and dma commands use dma */
1255 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1256 /* program the scatterlist into the prd table */
1257 ata_bmdma_qc_prep(qc);
1258
1259 /* point the sgdma controller at the dma request structure */
1260 pd = qc->ap->private_data;
1261
1262 iowrite32(pd->sgdma_request_pa,
1263 pd->sgdma_base + SGDMA_REQUESTPTR);
1264
1265 /* setup the request table */
1266 if (port_no == 0) {
1267 pd->sgdma_request->control =
1268 (qc->dma_dir == DMA_FROM_DEVICE) ?
1269 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1270 } else {
1271 pd->sgdma_request->control =
1272 (qc->dma_dir == DMA_FROM_DEVICE) ?
1273 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1274 }
1275 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1276 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1277 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1278 smp_wmb();
1279
1280 /* tell it to wait */
1281 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1282 }
1283 }
1284
1285 static int sata_oxnas_port_start(struct ata_port *ap)
1286 {
1287 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1288 struct device *dev = ap->host->dev;
1289 struct sata_oxnas_port_priv *pp;
1290 void *mem;
1291 dma_addr_t mem_dma;
1292
1293 DPRINTK("ENTER\n");
1294
1295 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1296 if (!pp)
1297 return -ENOMEM;
1298
1299 pp->port_base = host_priv->port_base[ap->port_no];
1300 pp->sgdma_base = host_priv->sgdma_base[ap->port_no];
1301 pp->core_base = host_priv->core_base;
1302
1303 /* preallocated */
1304 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * SATA_OXNAS_MAX_PORTS) {
1305 mem_dma = host_priv->dma_base +
1306 ap->port_no * SATA_OXNAS_DMA_SIZE;
1307 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1308
1309 } else {
1310 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1311 GFP_KERNEL);
1312 }
1313 if (!mem)
1314 goto err_ret;
1315
1316 pp->sgdma_request_pa = mem_dma;
1317 pp->sgdma_request = mem;
1318 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1319 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1320
1321 ap->private_data = pp;
1322
1323 sata_oxnas_post_reset_init(ap);
1324
1325 return 0;
1326
1327 err_ret:
1328 kfree(pp);
1329 return -ENOMEM;
1330
1331 }
1332
1333 static void sata_oxnas_port_stop(struct ata_port *ap)
1334 {
1335 struct device *dev = ap->host->dev;
1336 struct sata_oxnas_port_priv *pp = ap->private_data;
1337 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1338
1339 DPRINTK("ENTER\n");
1340 ap->private_data = NULL;
1341 if (host_priv->dma_size) {
1342 iounmap(pp->sgdma_request);
1343 } else {
1344 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1345 pp->sgdma_request, pp->sgdma_request_pa);
1346 }
1347
1348 kfree(pp);
1349 }
1350
1351 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1352 {
1353 struct sata_oxnas_port_priv *pd = ap->private_data;
1354 uint dev;
1355 int no_microcode = 0;
1356
1357 DPRINTK("ENTER\n");
1358 if (no_microcode) {
1359 u32 reg;
1360 sata_oxnas_set_mode(ap, UNKNOWN_MODE, 1);
1361 reg = readl(pd->core_base + DEVICE_CONTROL);
1362 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1363 writel(reg, pd->core_base + DEVICE_CONTROL);
1364 } else {
1365 /* JBOD uCode */
1366 sata_oxnas_set_mode(ap, OXNASSATA_NOTRAID, 1);
1367 /* Turn the work around off as it may have been left on by any
1368 * HW-RAID code that we've been working with */
1369 writel(0x0, pd->core_base + PORT_ERROR_MASK);
1370 }
1371 /* turn on phy error detection by removing the masks */
1372 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1373
1374 /* enable hotplug event detection */
1375 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1376 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1377 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1378
1379 /* enable interrupts for ports */
1380 sata_oxnas_irq_on(ap);
1381
1382 /* go through all the devices and configure them */
1383 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1384 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1385 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1386 sata_oxnas_dev_config(&(ap->link.device[dev]));
1387 }
1388 }
1389
1390 /* clean up any remaining errors */
1391 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1392 VPRINTK("done\n");
1393 }
1394
1395 /**
1396 * host_stop() is called when the rmmod or hot unplug process begins. The
1397 * hook must stop all hardware interrupts, DMA engines, etc.
1398 *
1399 * @param ap hardware with the registers in
1400 */
1401 static void sata_oxnas_host_stop(struct ata_host *host_set)
1402 {
1403 DPRINTK("\n");
1404 }
1405
1406
1407 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1408 static void sata_oxnas_error_handler(struct ata_port *ap)
1409 {
1410 DPRINTK("Enter port_no %d\n", ap->port_no);
1411 sata_oxnas_freeze_host(ap);
1412
1413 /* If the core is busy here, make it idle */
1414 sata_oxnas_cleanup(ap->host);
1415
1416 ata_std_error_handler(ap);
1417
1418 sata_oxnas_thaw_host(ap);
1419 }
1420
1421 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1422 unsigned long deadline)
1423 {
1424 struct ata_port *ap = link->ap;
1425 struct sata_oxnas_port_priv *pd = ap->private_data;
1426 void __iomem *port_base = pd->port_base;
1427 int rc;
1428
1429 struct ata_taskfile tf;
1430 u32 Command_Reg;
1431
1432 DPRINTK("ENTER\n");
1433
1434 port_base = pd->port_base;
1435
1436 if (ata_link_offline(link)) {
1437 DPRINTK("PHY reports no device\n");
1438 *class = ATA_DEV_NONE;
1439 goto out;
1440 }
1441
1442 /* write value to register */
1443 iowrite32((ap->ctl) << 24, port_base + ORB4);
1444
1445 /* command the core to send a control FIS */
1446 Command_Reg = ioread32(port_base + SATA_COMMAND);
1447 Command_Reg &= ~SATA_OPCODE_MASK;
1448 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1449 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1450 udelay(20); /* FIXME: flush */
1451
1452 /* write value to register */
1453 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
1454
1455 /* command the core to send a control FIS */
1456 Command_Reg &= ~SATA_OPCODE_MASK;
1457 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1458 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1459 udelay(20); /* FIXME: flush */
1460
1461 /* write value to register */
1462 iowrite32((ap->ctl) << 24, port_base + ORB4);
1463
1464 /* command the core to send a control FIS */
1465 Command_Reg &= ~SATA_OPCODE_MASK;
1466 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1467 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1468
1469 msleep(150);
1470
1471 rc = ata_sff_wait_ready(link, deadline);
1472
1473 /* if link is occupied, -ENODEV too is an error */
1474 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1475 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1476 return rc;
1477 }
1478
1479 /* determine by signature whether we have ATA or ATAPI devices */
1480 sata_oxnas_tf_read(ap, &tf);
1481 *class = ata_dev_classify(&tf);
1482
1483 if (*class == ATA_DEV_UNKNOWN)
1484 *class = ATA_DEV_NONE;
1485
1486 out:
1487 DPRINTK("EXIT, class=%u\n", *class);
1488 return 0;
1489 }
1490
1491
1492 int sata_oxnas_init_controller(struct ata_host *host)
1493 {
1494 return 0;
1495 }
1496
1497 /**
1498 * Ref bug-6320
1499 *
1500 * This code is a work around for a DMA hardware bug that will repeat the
1501 * penultimate 8-bytes on some reads. This code will check that the amount
1502 * of data transferred is a multiple of 512 bytes, if not the in it will
1503 * fetch the correct data from a buffer in the SATA core and copy it into
1504 * memory.
1505 *
1506 * @param port SATA port to check and if necessary, correct.
1507 */
1508 static int ox820sata_bug_6320_workaround(struct ata_port *ap)
1509 {
1510 struct sata_oxnas_port_priv *pd = ap->private_data;
1511 void __iomem *core_base = pd->core_base;
1512 int is_read;
1513 int quads_transferred;
1514 int remainder;
1515 int sector_quads_remaining;
1516 int bug_present = 0;
1517
1518 /* Only want to apply fix to reads */
1519 is_read = !(readl(core_base + DM_DBG1) & (ap->port_no ?
1520 BIT(CORE_PORT1_DATA_DIR_BIT) :
1521 BIT(CORE_PORT0_DATA_DIR_BIT)));
1522
1523 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
1524 transferred (datacount_port register counts quads transferred) */
1525 quads_transferred =
1526 readl(core_base + (ap->port_no ?
1527 DATACOUNT_PORT1 : DATACOUNT_PORT0));
1528
1529 remainder = quads_transferred & 0x7f;
1530 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
1531
1532 if (is_read && (sector_quads_remaining == 2)) {
1533 bug_present = 1;
1534 } else if (sector_quads_remaining) {
1535 if (is_read) {
1536 printk(KERN_WARNING "SATA read fixup cannot deal with" \
1537 " %d quads remaining\n",
1538 sector_quads_remaining);
1539 } else {
1540 printk(KERN_WARNING "SATA write fixup of %d quads" \
1541 " remaining not supported\n",
1542 sector_quads_remaining);
1543 }
1544 }
1545
1546 return bug_present;
1547 }
1548
1549 /* This port done an interrupt */
1550 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
1551 {
1552 struct ata_queued_cmd *qc;
1553 struct sata_oxnas_port_priv *pd = ap->private_data;
1554 void __iomem *port_base = pd->port_base;
1555
1556 u32 int_status;
1557 unsigned long flags = 0;
1558
1559 /* DPRINTK("ENTER irqstatus %x\n", ioread32(port_base + INT_STATUS)); */
1560 /*
1561 if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
1562 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1563 DPRINTK("completing non-ncq cmd\n");
1564
1565 if (qc) {
1566 ata_qc_complete(qc);
1567 }
1568 return;
1569 }
1570 */
1571
1572 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1573
1574
1575 /* record the port's interrupt */
1576 int_status = ioread32(port_base + INT_STATUS);
1577
1578 /* If there's no command associated with this IRQ, ignore it. We may get
1579 * spurious interrupts when cleaning-up after a failed command, ignore
1580 * these too. */
1581 if (likely(qc)) {
1582 /* get the status before any error cleanup */
1583 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
1584 if (force_error) {
1585 /* Pretend there has been a link error */
1586 qc->err_mask |= AC_ERR_ATA_BUS;
1587 DPRINTK(" ####force error####\n");
1588 }
1589 /* tell libata we're done */
1590 local_irq_save(flags);
1591 sata_oxnas_irq_clear(ap);
1592 local_irq_restore(flags);
1593 ata_qc_complete(qc);
1594 } else {
1595 VPRINTK("Ignoring interrupt, can't find the command tag=" \
1596 "%d %08x\n", ap->link.active_tag, ap->qc_active);
1597 }
1598
1599 /* maybe a hotplug event */
1600 if (unlikely(int_status & INT_LINK_SERROR)) {
1601 u32 serror;
1602
1603 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
1604 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
1605 ata_ehi_hotplugged(&ap->link.eh_info);
1606 ata_port_freeze(ap);
1607 }
1608 }
1609 }
1610
1611 /**
1612 * irq_handler is the interrupt handling routine registered with the system,
1613 * by libata.
1614 */
1615 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
1616 {
1617 struct ata_host *ah = dev_instance;
1618 struct sata_oxnas_host_priv *hd = ah->private_data;
1619 void __iomem *core_base = hd->core_base;
1620
1621 u32 int_status;
1622 irqreturn_t ret = IRQ_NONE;
1623 u32 port_no;
1624 u32 mask;
1625 int bug_present;
1626
1627 /* loop until there are no more interrupts */
1628 while ((int_status = ioread32(core_base + CORE_INT_STATUS)) &
1629 COREINT_END) {
1630
1631 /* clear any interrupt */
1632 iowrite32(int_status, core_base + CORE_INT_CLEAR);
1633
1634 /* Only need this workaround for single disk systems as dual
1635 * disk will use uCode which prevents this read underrun problem
1636 * from occuring.
1637 * All single disk systems will use port 0 */
1638
1639 for (port_no = 0; port_no < SATA_OXNAS_MAX_PORTS; ++port_no) {
1640 /* check the raw end of command interrupt to see if the
1641 * port is done */
1642 mask = (CORERAW_HOST << port_no);
1643 if (int_status & mask) {
1644 /* this port had an interrupt, clear it */
1645 iowrite32(mask, core_base + CORE_INT_CLEAR);
1646 bug_present = ox820sata_bug_6320_workaround(
1647 ah->ports[port_no]);
1648 sata_oxnas_port_irq(ah->ports[port_no],
1649 bug_present);
1650 ret = IRQ_HANDLED;
1651 }
1652 }
1653 }
1654
1655 return ret;
1656 }
1657
1658 /*
1659 * scsi mid-layer and libata interface structures
1660 */
1661 static struct scsi_host_template sata_oxnas_sht = {
1662 ATA_NCQ_SHT("sata_oxnas"),
1663 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
1664 .sg_tablesize = SATA_OXNAS_MAX_PRD,
1665 .dma_boundary = ATA_DMA_BOUNDARY,
1666 .unchecked_isa_dma = 0,
1667 };
1668
1669
1670 static struct ata_port_operations sata_oxnas_ops = {
1671 .inherits = &sata_port_ops,
1672 .qc_prep = sata_oxnas_qc_prep,
1673 .qc_issue = sata_oxnas_qc_issue,
1674 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
1675
1676 .scr_read = sata_oxnas_scr_read,
1677 .scr_write = sata_oxnas_scr_write,
1678
1679 /* .freeze = sata_oxnas_freeze, */
1680 /* .thaw = sata_oxnas_thaw, */
1681 .softreset = sata_oxnas_softreset,
1682 /* .hardreset = sata_oxnas_hardreset, */
1683 .postreset = sata_oxnas_postreset,
1684 .error_handler = sata_oxnas_error_handler,
1685 .post_internal_cmd = sata_oxnas_post_internal_cmd,
1686
1687 .port_start = sata_oxnas_port_start,
1688 .port_stop = sata_oxnas_port_stop,
1689
1690 .host_stop = sata_oxnas_host_stop,
1691 /* .pmp_attach = sata_oxnas_pmp_attach, */
1692 /* .pmp_detach = sata_oxnas_pmp_detach, */
1693 .sff_check_status = sata_oxnas_check_status,
1694 };
1695
1696 static const struct ata_port_info sata_oxnas_port_info = {
1697 .flags = SATA_OXNAS_HOST_FLAGS,
1698 .pio_mask = ATA_PIO4,
1699 .udma_mask = ATA_UDMA6,
1700 .port_ops = &sata_oxnas_ops,
1701 };
1702
1703 static int sata_oxnas_probe(struct platform_device *ofdev)
1704 {
1705 int retval = -ENXIO;
1706 void __iomem *port_base = NULL;
1707 void __iomem *sgdma_base = NULL;
1708 void __iomem *core_base = NULL;
1709 void __iomem *phy_base = NULL;
1710 struct reset_control *rstc;
1711
1712 struct resource res = {};
1713 struct sata_oxnas_host_priv *host_priv = NULL;
1714 int irq = 0;
1715 struct ata_host *host = NULL;
1716 struct clk *clk = NULL;
1717
1718 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
1719
1720 port_base = of_iomap(ofdev->dev.of_node, 0);
1721 if (!port_base)
1722 goto error_exit_with_cleanup;
1723
1724 sgdma_base = of_iomap(ofdev->dev.of_node, 1);
1725 if (!sgdma_base)
1726 goto error_exit_with_cleanup;
1727
1728 core_base = of_iomap(ofdev->dev.of_node, 2);
1729 if (!core_base)
1730 goto error_exit_with_cleanup;
1731
1732 phy_base = of_iomap(ofdev->dev.of_node, 3);
1733 if (!phy_base)
1734 goto error_exit_with_cleanup;
1735
1736 host_priv = devm_kzalloc(&ofdev->dev,
1737 sizeof(struct sata_oxnas_host_priv),
1738 GFP_KERNEL);
1739 if (!host_priv)
1740 goto error_exit_with_cleanup;
1741
1742 host_priv->port_base[0] = port_base;
1743 host_priv->sgdma_base[0] = sgdma_base;
1744 host_priv->core_base = core_base;
1745 host_priv->phy_base = phy_base;
1746
1747 if (!of_address_to_resource(ofdev->dev.of_node, 4, &res)) {
1748 host_priv->dma_base = res.start;
1749 host_priv->dma_size = resource_size(&res);
1750 }
1751
1752 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1753 if (!irq) {
1754 dev_err(&ofdev->dev, "invalid irq from platform\n");
1755 goto error_exit_with_cleanup;
1756 }
1757 host_priv->irq = irq;
1758
1759 clk = of_clk_get(ofdev->dev.of_node, 0);
1760 if (IS_ERR(clk)) {
1761 retval = PTR_ERR(clk);
1762 clk = NULL;
1763 goto error_exit_with_cleanup;
1764 }
1765 host_priv->clk = clk;
1766
1767 rstc = devm_reset_control_get(&ofdev->dev, "sata");
1768 if (IS_ERR(rstc)) {
1769 retval = PTR_ERR(rstc);
1770 goto error_exit_with_cleanup;
1771 }
1772 host_priv->rst_sata = rstc;
1773
1774 rstc = devm_reset_control_get(&ofdev->dev, "link");
1775 if (IS_ERR(rstc)) {
1776 retval = PTR_ERR(rstc);
1777 goto error_exit_with_cleanup;
1778 }
1779 host_priv->rst_link = rstc;
1780
1781 rstc = devm_reset_control_get(&ofdev->dev, "phy");
1782 if (IS_ERR(rstc)) {
1783 retval = PTR_ERR(rstc);
1784 goto error_exit_with_cleanup;
1785 }
1786 host_priv->rst_phy = rstc;
1787
1788 /* allocate host structure */
1789 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_OXNAS_MAX_PORTS);
1790 if (!host) {
1791 retval = -ENOMEM;
1792 goto error_exit_with_cleanup;
1793 }
1794 host->private_data = host_priv;
1795 host->iomap = port_base;
1796
1797 /* initialize host controller */
1798 retval = sata_oxnas_init_controller(host);
1799 if (retval)
1800 goto error_exit_with_cleanup;
1801
1802 /*
1803 * Now, register with libATA core, this will also initiate the
1804 * device discovery process, invoking our port_start() handler &
1805 * error_handler() to execute a dummy softreset EH session
1806 */
1807 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
1808 &sata_oxnas_sht);
1809
1810 return 0;
1811
1812 error_exit_with_cleanup:
1813 if (irq)
1814 irq_dispose_mapping(host_priv->irq);
1815 if (clk)
1816 clk_put(clk);
1817 if (host)
1818 ata_host_detach(host);
1819 if (port_base)
1820 iounmap(port_base);
1821 if (sgdma_base)
1822 iounmap(sgdma_base);
1823 if (core_base)
1824 iounmap(core_base);
1825 if (phy_base)
1826 iounmap(phy_base);
1827 return retval;
1828 }
1829
1830
1831 static int sata_oxnas_remove(struct platform_device *ofdev)
1832 {
1833 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1834 struct sata_oxnas_host_priv *host_priv = host->private_data;
1835
1836 ata_host_detach(host);
1837
1838 irq_dispose_mapping(host_priv->irq);
1839 iounmap(host_priv->port_base);
1840 iounmap(host_priv->sgdma_base);
1841 iounmap(host_priv->core_base);
1842
1843 /* reset Controller, Link and PHY */
1844 reset_control_assert(host_priv->rst_sata);
1845 reset_control_assert(host_priv->rst_link);
1846 reset_control_assert(host_priv->rst_phy);
1847
1848 /* Disable the clock to the SATA block */
1849 clk_disable_unprepare(host_priv->clk);
1850 clk_put(host_priv->clk);
1851
1852 return 0;
1853 }
1854
1855 #ifdef CONFIG_PM
1856 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
1857 {
1858 struct ata_host *host = dev_get_drvdata(&op->dev);
1859
1860 return ata_host_suspend(host, state);
1861 }
1862
1863 static int sata_oxnas_resume(struct platform_device *op)
1864 {
1865 struct ata_host *host = dev_get_drvdata(&op->dev);
1866 int ret;
1867
1868 ret = sata_oxnas_init_controller(host);
1869 if (ret) {
1870 dev_err(&op->dev, "Error initializing hardware\n");
1871 return ret;
1872 }
1873 ata_host_resume(host);
1874 return 0;
1875 }
1876 #endif
1877
1878
1879
1880 static struct of_device_id oxnas_sata_match[] = {
1881 {
1882 .compatible = "plxtech,nas782x-sata",
1883 },
1884 {},
1885 };
1886
1887 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
1888
1889 static struct platform_driver oxnas_sata_driver = {
1890 .driver = {
1891 .name = "oxnas-sata",
1892 .owner = THIS_MODULE,
1893 .of_match_table = oxnas_sata_match,
1894 },
1895 .probe = sata_oxnas_probe,
1896 .remove = sata_oxnas_remove,
1897 #ifdef CONFIG_PM
1898 .suspend = sata_oxnas_suspend,
1899 .resume = sata_oxnas_resume,
1900 #endif
1901 };
1902
1903 module_platform_driver(oxnas_sata_driver);
1904
1905 MODULE_LICENSE("GPL");
1906 MODULE_VERSION("1.0");
1907 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
1908 MODULE_DESCRIPTION("934 SATA core controler");
OpenWrt Source Repository