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[openwrt/openwrt.git] / target / linux / oxnas / files / drivers / pinctrl / pinctrl-oxnas.c
1 /*
2 * oxnas pinctrl driver based on at91 pinctrl driver
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
29
30 #include "core.h"
31
32 #include <mach/utils.h>
33
34 #define MAX_NB_GPIO_PER_BANK 32
35 #define MAX_GPIO_BANKS 2
36
37 struct oxnas_gpio_chip {
38 struct gpio_chip chip;
39 struct pinctrl_gpio_range range;
40 void __iomem *regbase; /* GPIOA/B virtual address */
41 void __iomem *ctrlbase; /* SYS/SEC_CTRL virtual address */
42 struct irq_domain *domain; /* associated irq domain */
43 };
44
45 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
46
47 static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
48
49 static int gpio_banks;
50
51 #define PULL_UP (1 << 0)
52 #define PULL_DOWN (1 << 1)
53 #define DEBOUNCE (1 << 2)
54
55 /**
56 * struct oxnas_pmx_func - describes pinmux functions
57 * @name: the name of this specific function
58 * @groups: corresponding pin groups
59 * @ngroups: the number of groups
60 */
61 struct oxnas_pmx_func {
62 const char *name;
63 const char **groups;
64 unsigned ngroups;
65 };
66
67 enum oxnas_mux {
68 OXNAS_PINMUX_GPIO,
69 OXNAS_PINMUX_FUNC2,
70 OXNAS_PINMUX_FUNC3,
71 OXNAS_PINMUX_FUNC4,
72 OXNAS_PINMUX_DEBUG,
73 OXNAS_PINMUX_ALT,
74 };
75
76 enum {
77 INPUT_VALUE = 0,
78 OUTPUT_ENABLE = 4,
79 IRQ_PENDING = 0xC,
80 OUTPUT_VALUE = 0x10,
81 OUTPUT_SET = 0x14,
82 OUTPUT_CLEAR = 0x18,
83 OUTPUT_EN_SET = 0x1C,
84 OUTPUT_EN_CLEAR = 0x20,
85 DEBOUNCE_ENABLE = 0x24,
86 RE_IRQ_ENABLE = 0x28, /* rising edge */
87 FE_IRQ_ENABLE = 0x2C, /* falling edge */
88 RE_IRQ_PENDING = 0x30, /* rising edge */
89 FE_IRQ_PENDING = 0x34, /* falling edge */
90 CLOCK_DIV = 0x48,
91 PULL_ENABLE = 0x50,
92 PULL_SENSE = 0x54, /* 1 up, 0 down */
93
94
95 DEBOUNCE_MASK = 0x3FFF0000,
96 /* put hw debounce and soft config at same bit position*/
97 DEBOUNCE_SHIFT = 16
98 };
99
100 enum {
101 PINMUX_SECONDARY_SEL = 0x14,
102 PINMUX_TERTIARY_SEL = 0x8c,
103 PINMUX_QUATERNARY_SEL = 0x94,
104 PINMUX_DEBUG_SEL = 0x9c,
105 PINMUX_ALTERNATIVE_SEL = 0xa4,
106 PINMUX_PULLUP_SEL = 0xac,
107 };
108
109 /**
110 * struct oxnas_pmx_pin - describes an pin mux
111 * @bank: the bank of the pin
112 * @pin: the pin number in the @bank
113 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
114 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
115 */
116 struct oxnas_pmx_pin {
117 uint32_t bank;
118 uint32_t pin;
119 enum oxnas_mux mux;
120 unsigned long conf;
121 };
122
123 /**
124 * struct oxnas_pin_group - describes an pin group
125 * @name: the name of this specific pin group
126 * @pins_conf: the mux mode for each pin in this group. The size of this
127 * array is the same as pins.
128 * @pins: an array of discrete physical pins used in this group, taken
129 * from the driver-local pin enumeration space
130 * @npins: the number of pins in this group array, i.e. the number of
131 * elements in .pins so we can iterate over that array
132 */
133 struct oxnas_pin_group {
134 const char *name;
135 struct oxnas_pmx_pin *pins_conf;
136 unsigned int *pins;
137 unsigned npins;
138 };
139
140 struct oxnas_pinctrl {
141 struct device *dev;
142 struct pinctrl_dev *pctl;
143
144 int nbanks;
145
146 uint32_t *mux_mask;
147 int nmux;
148
149 struct oxnas_pmx_func *functions;
150 int nfunctions;
151
152 struct oxnas_pin_group *groups;
153 int ngroups;
154 };
155
156 static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name(
157 const struct oxnas_pinctrl *info,
158 const char *name)
159 {
160 const struct oxnas_pin_group *grp = NULL;
161 int i;
162
163 for (i = 0; i < info->ngroups; i++) {
164 if (strcmp(info->groups[i].name, name))
165 continue;
166
167 grp = &info->groups[i];
168 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins,
169 grp->pins[0]);
170 break;
171 }
172
173 return grp;
174 }
175
176 static int oxnas_get_groups_count(struct pinctrl_dev *pctldev)
177 {
178 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
179
180 return info->ngroups;
181 }
182
183 static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev,
184 unsigned selector)
185 {
186 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
187
188 return info->groups[selector].name;
189 }
190
191 static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
192 const unsigned **pins,
193 unsigned *npins)
194 {
195 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
196
197 if (selector >= info->ngroups)
198 return -EINVAL;
199
200 *pins = info->groups[selector].pins;
201 *npins = info->groups[selector].npins;
202
203 return 0;
204 }
205
206 static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
207 unsigned offset)
208 {
209 seq_printf(s, "%s", dev_name(pctldev->dev));
210 }
211
212 static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev,
213 struct device_node *np,
214 struct pinctrl_map **map, unsigned *num_maps)
215 {
216 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
217 const struct oxnas_pin_group *grp;
218 struct pinctrl_map *new_map;
219 struct device_node *parent;
220 int map_num = 1;
221 int i;
222
223 /*
224 * first find the group of this node and check if we need create
225 * config maps for pins
226 */
227 grp = oxnas_pinctrl_find_group_by_name(info, np->name);
228 if (!grp) {
229 dev_err(info->dev, "unable to find group for node %s\n",
230 np->name);
231 return -EINVAL;
232 }
233
234 map_num += grp->npins;
235 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
236 GFP_KERNEL);
237 if (!new_map)
238 return -ENOMEM;
239
240 *map = new_map;
241 *num_maps = map_num;
242
243 /* create mux map */
244 parent = of_get_parent(np);
245 if (!parent) {
246 devm_kfree(pctldev->dev, new_map);
247 return -EINVAL;
248 }
249 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
250 new_map[0].data.mux.function = parent->name;
251 new_map[0].data.mux.group = np->name;
252 of_node_put(parent);
253
254 /* create config map */
255 new_map++;
256 for (i = 0; i < grp->npins; i++) {
257 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
258 new_map[i].data.configs.group_or_pin =
259 pin_get_name(pctldev, grp->pins[i]);
260 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
261 new_map[i].data.configs.num_configs = 1;
262 }
263
264 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
265 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
266
267 return 0;
268 }
269
270 static void oxnas_dt_free_map(struct pinctrl_dev *pctldev,
271 struct pinctrl_map *map, unsigned num_maps)
272 {
273 }
274
275 static const struct pinctrl_ops oxnas_pctrl_ops = {
276 .get_groups_count = oxnas_get_groups_count,
277 .get_group_name = oxnas_get_group_name,
278 .get_group_pins = oxnas_get_group_pins,
279 .pin_dbg_show = oxnas_pin_dbg_show,
280 .dt_node_to_map = oxnas_dt_node_to_map,
281 .dt_free_map = oxnas_dt_free_map,
282 };
283
284 static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info,
285 unsigned int bank)
286 {
287 return gpio_chips[bank]->regbase;
288 }
289
290 static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info,
291 unsigned int bank)
292 {
293 return gpio_chips[bank]->ctrlbase;
294 }
295
296
297 static inline int pin_to_bank(unsigned pin)
298 {
299 return pin / MAX_NB_GPIO_PER_BANK;
300 }
301
302 static unsigned pin_to_mask(unsigned int pin)
303 {
304 return 1 << pin;
305 }
306
307 static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask)
308 {
309 oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
310 oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
311 }
312
313 static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin)
314 {
315 return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
316 (readl_relaxed(pio + PULL_SENSE) & BIT(pin));
317 }
318
319 static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
320 {
321 if (on) {
322 oxnas_register_set_mask(pio + PULL_SENSE, mask);
323 oxnas_register_set_mask(pio + PULL_ENABLE, mask);
324 } else {
325 oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
326 }
327 }
328
329 static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin)
330 {
331 return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
332 (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin)));
333 }
334
335 static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on)
336 {
337 if (on) {
338 oxnas_register_clear_mask(pio + PULL_SENSE, mask);
339 oxnas_register_set_mask(pio + PULL_ENABLE, mask);
340 } else {
341 oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
342 };
343 }
344
345 /* unfortunately debounce control are shared */
346 static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
347 {
348 *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK;
349 return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin);
350 }
351
352 static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask,
353 bool is_on, u32 div)
354 {
355 if (is_on) {
356 oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div);
357 oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask);
358 } else {
359 oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask);
360 }
361 }
362
363
364 static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask)
365 {
366 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
367 oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask);
368 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
369 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
370 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
371 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
372 }
373
374 static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask)
375 {
376 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
377 oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask);
378 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
379 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
380 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
381 }
382
383 static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask)
384 {
385 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
386 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
387 oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask);
388 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
389 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
390 }
391
392 static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask)
393 {
394 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
395 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
396 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
397 oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask);
398 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
399 }
400
401 static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask)
402 {
403 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
404 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
405 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
406 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
407 oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
408 }
409
410 static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask)
411 {
412 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
413 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
414 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
415 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
416 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
417 }
418
419 static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask)
420 {
421 if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask)
422 return OXNAS_PINMUX_FUNC2;
423 if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask)
424 return OXNAS_PINMUX_FUNC3;
425 if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask)
426 return OXNAS_PINMUX_FUNC4;
427 if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask)
428 return OXNAS_PINMUX_DEBUG;
429 if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask)
430 return OXNAS_PINMUX_ALT;
431 return OXNAS_PINMUX_GPIO;
432 }
433
434
435 static void oxnas_pin_dbg(const struct device *dev,
436 const struct oxnas_pmx_pin *pin)
437 {
438 if (pin->mux) {
439 dev_dbg(dev,
440 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
441 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A',
442 pin->conf);
443 } else {
444 dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n",
445 pin->bank + 'A', pin->pin, pin->conf);
446 }
447 }
448
449 static int pin_check_config(struct oxnas_pinctrl *info, const char *name,
450 int index, const struct oxnas_pmx_pin *pin)
451 {
452 int mux;
453
454 /* check if it's a valid config */
455 if (pin->bank >= info->nbanks) {
456 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
457 name, index, pin->bank, info->nbanks);
458 return -EINVAL;
459 }
460
461 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
462 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
463 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
464 return -EINVAL;
465 }
466 /* gpio always allowed */
467 if (!pin->mux)
468 return 0;
469
470 mux = pin->mux - 1;
471
472 if (mux >= info->nmux) {
473 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
474 name, index, mux, info->nmux);
475 return -EINVAL;
476 }
477
478 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
479 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
480 name, index, mux, pin->bank + 'A', pin->pin);
481 return -EINVAL;
482 }
483
484 return 0;
485 }
486
487 static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio,
488 unsigned mask, bool input)
489 {
490 oxnas_mux_set_gpio(cio, mask);
491 if (input)
492 writel_relaxed(mask, pio + OUTPUT_EN_CLEAR);
493 else
494 writel_relaxed(mask, pio + OUTPUT_EN_SET);
495 }
496
497 static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio,
498 unsigned mask)
499 {
500 /* when switch to other function, gpio is disabled automatically */
501 return;
502 }
503
504 static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
505 unsigned group)
506 {
507 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
508 const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf;
509 const struct oxnas_pmx_pin *pin;
510 uint32_t npins = info->groups[group].npins;
511 int i, ret;
512 unsigned mask;
513 void __iomem *pio;
514 void __iomem *cio;
515
516 dev_dbg(info->dev, "enable function %s group %s\n",
517 info->functions[selector].name, info->groups[group].name);
518
519 /* first check that all the pins of the group are valid with a valid
520 * paramter */
521 for (i = 0; i < npins; i++) {
522 pin = &pins_conf[i];
523 ret = pin_check_config(info, info->groups[group].name, i, pin);
524 if (ret)
525 return ret;
526 }
527
528 for (i = 0; i < npins; i++) {
529 pin = &pins_conf[i];
530 oxnas_pin_dbg(info->dev, pin);
531
532 pio = pin_to_gpioctrl(info, pin->bank);
533 cio = pin_to_muxctrl(info, pin->bank);
534
535 mask = pin_to_mask(pin->pin);
536 oxnas_mux_disable_interrupt(pio, mask);
537
538 switch (pin->mux) {
539 case OXNAS_PINMUX_GPIO:
540 oxnas_mux_gpio_enable(cio, pio, mask, 1);
541 break;
542 case OXNAS_PINMUX_FUNC2:
543 oxnas_mux_set_func2(cio, mask);
544 break;
545 case OXNAS_PINMUX_FUNC3:
546 oxnas_mux_set_func3(cio, mask);
547 break;
548 case OXNAS_PINMUX_FUNC4:
549 oxnas_mux_set_func4(cio, mask);
550 break;
551 case OXNAS_PINMUX_DEBUG:
552 oxnas_mux_set_func_dbg(cio, mask);
553 break;
554 case OXNAS_PINMUX_ALT:
555 oxnas_mux_set_func_alt(cio, mask);
556 break;
557 }
558 if (pin->mux)
559 oxnas_mux_gpio_disable(cio, pio, mask);
560 }
561
562 return 0;
563 }
564
565 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
566 {
567 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
568
569 return info->nfunctions;
570 }
571
572 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev,
573 unsigned selector)
574 {
575 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
576
577 return info->functions[selector].name;
578 }
579
580 static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
581 const char * const **groups,
582 unsigned * const num_groups)
583 {
584 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
585
586 *groups = info->functions[selector].groups;
587 *num_groups = info->functions[selector].ngroups;
588
589 return 0;
590 }
591
592 static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
593 struct pinctrl_gpio_range *range,
594 unsigned offset)
595 {
596 struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
597 struct oxnas_gpio_chip *oxnas_chip;
598 struct gpio_chip *chip;
599 unsigned mask;
600
601 if (!range) {
602 dev_err(npct->dev, "invalid range\n");
603 return -EINVAL;
604 }
605 if (!range->gc) {
606 dev_err(npct->dev, "missing GPIO chip in range\n");
607 return -EINVAL;
608 }
609 chip = range->gc;
610 oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip);
611
612 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
613
614 mask = 1 << (offset - chip->base);
615
616 dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n",
617 offset, 'A' + range->id, offset - chip->base, mask);
618
619 oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask);
620
621 return 0;
622 }
623
624 static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev,
625 struct pinctrl_gpio_range *range,
626 unsigned offset)
627 {
628 struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
629
630 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
631 /* Set the pin to some default state, GPIO is usually default */
632 }
633
634 static const struct pinmux_ops oxnas_pmx_ops = {
635 .get_functions_count = oxnas_pmx_get_funcs_count,
636 .get_function_name = oxnas_pmx_get_func_name,
637 .get_function_groups = oxnas_pmx_get_groups,
638 .set_mux = oxnas_pmx_set_mux,
639 .gpio_request_enable = oxnas_gpio_request_enable,
640 .gpio_disable_free = oxnas_gpio_disable_free,
641 };
642
643 static int oxnas_pinconf_get(struct pinctrl_dev *pctldev,
644 unsigned pin_id, unsigned long *config)
645 {
646 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
647 void __iomem *pio;
648 unsigned pin;
649 int div;
650
651 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__,
652 __LINE__, pin_id, *config);
653 pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
654 pin = pin_id % MAX_NB_GPIO_PER_BANK;
655
656 if (oxnas_mux_get_pullup(pio, pin))
657 *config |= PULL_UP;
658
659 if (oxnas_mux_get_pulldown(pio, pin))
660 *config |= PULL_DOWN;
661
662 if (oxnas_mux_get_debounce(pio, pin, &div))
663 *config |= DEBOUNCE | div;
664 return 0;
665 }
666
667 static int oxnas_pinconf_set(struct pinctrl_dev *pctldev,
668 unsigned pin_id, unsigned long *configs,
669 unsigned num_configs)
670 {
671 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
672 unsigned mask;
673 void __iomem *pio;
674 int i;
675 unsigned long config;
676
677 pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
678 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
679
680 for (i = 0; i < num_configs; i++) {
681 config = configs[i];
682
683 dev_dbg(info->dev,
684 "%s:%d, pin_id=%d, config=0x%lx",
685 __func__, __LINE__, pin_id, config);
686
687 if ((config & PULL_UP) && (config & PULL_DOWN))
688 return -EINVAL;
689
690 oxnas_mux_set_pullup(pio, mask, config & PULL_UP);
691 oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN);
692 oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE,
693 config & DEBOUNCE_MASK);
694
695 } /* for each config */
696
697 return 0;
698 }
699
700 static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev,
701 struct seq_file *s, unsigned pin_id)
702 {
703
704 }
705
706 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
707 struct seq_file *s, unsigned group)
708 {
709 }
710
711 static const struct pinconf_ops oxnas_pinconf_ops = {
712 .pin_config_get = oxnas_pinconf_get,
713 .pin_config_set = oxnas_pinconf_set,
714 .pin_config_dbg_show = oxnas_pinconf_dbg_show,
715 .pin_config_group_dbg_show = oxnas_pinconf_group_dbg_show,
716 };
717
718 static struct pinctrl_desc oxnas_pinctrl_desc = {
719 .pctlops = &oxnas_pctrl_ops,
720 .pmxops = &oxnas_pmx_ops,
721 .confops = &oxnas_pinconf_ops,
722 .owner = THIS_MODULE,
723 };
724
725 static const char *gpio_compat = "plxtech,nas782x-gpio";
726
727 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info,
728 struct device_node *np)
729 {
730 struct device_node *child;
731
732 for_each_child_of_node(np, child) {
733 if (of_device_is_compatible(child, gpio_compat)) {
734 info->nbanks++;
735 } else {
736 info->nfunctions++;
737 info->ngroups += of_get_child_count(child);
738 }
739 }
740 }
741
742 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info,
743 struct device_node *np)
744 {
745 int ret = 0;
746 int size;
747 const __be32 *list;
748
749 list = of_get_property(np, "plxtech,mux-mask", &size);
750 if (!list) {
751 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
752 return -EINVAL;
753 }
754
755 size /= sizeof(*list);
756 if (!size || size % info->nbanks) {
757 dev_err(info->dev, "wrong mux mask array should be by %d\n",
758 info->nbanks);
759 return -EINVAL;
760 }
761 info->nmux = size / info->nbanks;
762
763 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
764 if (!info->mux_mask) {
765 dev_err(info->dev, "could not alloc mux_mask\n");
766 return -ENOMEM;
767 }
768
769 ret = of_property_read_u32_array(np, "plxtech,mux-mask",
770 info->mux_mask, size);
771 if (ret)
772 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
773 return ret;
774 }
775
776 static int oxnas_pinctrl_parse_groups(struct device_node *np,
777 struct oxnas_pin_group *grp,
778 struct oxnas_pinctrl *info, u32 index)
779 {
780 struct oxnas_pmx_pin *pin;
781 int size;
782 const __be32 *list;
783 int i, j;
784
785 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
786
787 /* Initialise group */
788 grp->name = np->name;
789
790 /*
791 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
792 * do sanity check and calculate pins number
793 */
794 list = of_get_property(np, "plxtech,pins", &size);
795 /* we do not check return since it's safe node passed down */
796 size /= sizeof(*list);
797 if (!size || size % 4) {
798 dev_err(info->dev, "wrong pins number or pins and configs"
799 " should be divisible by 4\n");
800 return -EINVAL;
801 }
802
803 grp->npins = size / 4;
804 pin = grp->pins_conf = devm_kzalloc(info->dev,
805 grp->npins * sizeof(struct oxnas_pmx_pin),
806 GFP_KERNEL);
807 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
808 GFP_KERNEL);
809 if (!grp->pins_conf || !grp->pins)
810 return -ENOMEM;
811
812 for (i = 0, j = 0; i < size; i += 4, j++) {
813 pin->bank = be32_to_cpu(*list++);
814 pin->pin = be32_to_cpu(*list++);
815 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
816 pin->mux = be32_to_cpu(*list++);
817 pin->conf = be32_to_cpu(*list++);
818
819 oxnas_pin_dbg(info->dev, pin);
820 pin++;
821 }
822
823 return 0;
824 }
825
826 static int oxnas_pinctrl_parse_functions(struct device_node *np,
827 struct oxnas_pinctrl *info, u32 index)
828 {
829 struct device_node *child;
830 struct oxnas_pmx_func *func;
831 struct oxnas_pin_group *grp;
832 int ret;
833 static u32 grp_index;
834 u32 i = 0;
835
836 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
837
838 func = &info->functions[index];
839
840 /* Initialise function */
841 func->name = np->name;
842 func->ngroups = of_get_child_count(np);
843 if (func->ngroups <= 0) {
844 dev_err(info->dev, "no groups defined\n");
845 return -EINVAL;
846 }
847 func->groups = devm_kzalloc(info->dev,
848 func->ngroups * sizeof(char *), GFP_KERNEL);
849 if (!func->groups)
850 return -ENOMEM;
851
852 for_each_child_of_node(np, child) {
853 func->groups[i] = child->name;
854 grp = &info->groups[grp_index++];
855 ret = oxnas_pinctrl_parse_groups(child, grp, info, i++);
856 if (ret)
857 return ret;
858 }
859
860 return 0;
861 }
862
863 static struct of_device_id oxnas_pinctrl_of_match[] = {
864 { .compatible = "plxtech,nas782x-pinctrl"},
865 { /* sentinel */ }
866 };
867
868 static int oxnas_pinctrl_probe_dt(struct platform_device *pdev,
869 struct oxnas_pinctrl *info)
870 {
871 int ret = 0;
872 int i, j;
873 uint32_t *tmp;
874 struct device_node *np = pdev->dev.of_node;
875 struct device_node *child;
876
877 if (!np)
878 return -ENODEV;
879
880 info->dev = &pdev->dev;
881
882 oxnas_pinctrl_child_count(info, np);
883
884 if (info->nbanks < 1) {
885 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
886 return -EINVAL;
887 }
888
889 ret = oxnas_pinctrl_mux_mask(info, np);
890 if (ret)
891 return ret;
892
893 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
894
895 dev_dbg(&pdev->dev, "mux-mask\n");
896 tmp = info->mux_mask;
897 for (i = 0; i < info->nbanks; i++)
898 for (j = 0; j < info->nmux; j++, tmp++)
899 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
900
901 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
902 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
903 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions *
904 sizeof(struct oxnas_pmx_func),
905 GFP_KERNEL);
906 if (!info->functions)
907 return -ENOMEM;
908
909 info->groups = devm_kzalloc(&pdev->dev, info->ngroups *
910 sizeof(struct oxnas_pin_group),
911 GFP_KERNEL);
912 if (!info->groups)
913 return -ENOMEM;
914
915 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
916 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
917 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
918
919 i = 0;
920
921 for_each_child_of_node(np, child) {
922 if (of_device_is_compatible(child, gpio_compat))
923 continue;
924 ret = oxnas_pinctrl_parse_functions(child, info, i++);
925 if (ret) {
926 dev_err(&pdev->dev, "failed to parse function\n");
927 return ret;
928 }
929 }
930
931 return 0;
932 }
933
934 static int oxnas_pinctrl_probe(struct platform_device *pdev)
935 {
936 struct oxnas_pinctrl *info;
937 struct pinctrl_pin_desc *pdesc;
938 int ret, i, j, k;
939
940 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
941 if (!info)
942 return -ENOMEM;
943
944 ret = oxnas_pinctrl_probe_dt(pdev, info);
945 if (ret)
946 return ret;
947
948 /*
949 * We need all the GPIO drivers to probe FIRST, or we will not be able
950 * to obtain references to the struct gpio_chip * for them, and we
951 * need this to proceed.
952 */
953 for (i = 0; i < info->nbanks; i++) {
954 if (!gpio_chips[i]) {
955 dev_warn(&pdev->dev,
956 "GPIO chip %d not registered yet\n", i);
957 devm_kfree(&pdev->dev, info);
958 return -EPROBE_DEFER;
959 }
960 }
961
962 oxnas_pinctrl_desc.name = dev_name(&pdev->dev);
963 oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
964 oxnas_pinctrl_desc.pins = pdesc =
965 devm_kzalloc(&pdev->dev, sizeof(*pdesc) *
966 oxnas_pinctrl_desc.npins, GFP_KERNEL);
967
968 if (!oxnas_pinctrl_desc.pins)
969 return -ENOMEM;
970
971 for (i = 0 , k = 0; i < info->nbanks; i++) {
972 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
973 pdesc->number = k;
974 pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A',
975 j);
976 pdesc++;
977 }
978 }
979
980 platform_set_drvdata(pdev, info);
981 info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info);
982
983 if (!info->pctl) {
984 dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n");
985 ret = -EINVAL;
986 goto err;
987 }
988
989 /* We will handle a range of GPIO pins */
990 for (i = 0; i < info->nbanks; i++)
991 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
992
993 dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n");
994
995 return 0;
996
997 err:
998 return ret;
999 }
1000
1001 static int oxnas_pinctrl_remove(struct platform_device *pdev)
1002 {
1003 struct oxnas_pinctrl *info = platform_get_drvdata(pdev);
1004
1005 pinctrl_unregister(info->pctl);
1006
1007 return 0;
1008 }
1009
1010 static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset)
1011 {
1012 /*
1013 * Map back to global GPIO space and request muxing, the direction
1014 * parameter does not matter for this controller.
1015 */
1016 int gpio = chip->base + offset;
1017 int bank = chip->base / chip->ngpio;
1018
1019 dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__,
1020 'A' + bank, offset, gpio);
1021
1022 return pinctrl_request_gpio(gpio);
1023 }
1024
1025 static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset)
1026 {
1027 int gpio = chip->base + offset;
1028
1029 pinctrl_free_gpio(gpio);
1030 }
1031
1032 static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1033 {
1034 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1035 void __iomem *pio = oxnas_gpio->regbase;
1036
1037 writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR);
1038 return 0;
1039 }
1040
1041 static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset)
1042 {
1043 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1044 void __iomem *pio = oxnas_gpio->regbase;
1045 unsigned mask = 1 << offset;
1046 u32 pdsr;
1047
1048 pdsr = readl_relaxed(pio + INPUT_VALUE);
1049 return (pdsr & mask) != 0;
1050 }
1051
1052 static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset,
1053 int val)
1054 {
1055 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1056 void __iomem *pio = oxnas_gpio->regbase;
1057
1058 if (val)
1059 writel_relaxed(BIT(offset), pio + OUTPUT_SET);
1060 else
1061 writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
1062
1063 }
1064
1065 static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1066 int val)
1067 {
1068 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1069 void __iomem *pio = oxnas_gpio->regbase;
1070
1071 if (val)
1072 writel_relaxed(BIT(offset), pio + OUTPUT_SET);
1073 else
1074 writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
1075
1076 writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET);
1077
1078 return 0;
1079 }
1080
1081 static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1082 {
1083 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1084 int virq;
1085
1086 if (offset < chip->ngpio)
1087 virq = irq_create_mapping(oxnas_gpio->domain, offset);
1088 else
1089 virq = -ENXIO;
1090
1091 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1092 chip->label, offset + chip->base, virq);
1093 return virq;
1094 }
1095
1096 #ifdef CONFIG_DEBUG_FS
1097 static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1098 {
1099 enum oxnas_mux mode;
1100 int i;
1101 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1102 void __iomem *pio = oxnas_gpio->regbase;
1103 void __iomem *cio = oxnas_gpio->ctrlbase;
1104
1105 for (i = 0; i < chip->ngpio; i++) {
1106 unsigned pin = chip->base + i;
1107 unsigned mask = pin_to_mask(pin);
1108 const char *gpio_label;
1109 u32 pdsr;
1110
1111 gpio_label = gpiochip_is_requested(chip, i);
1112 if (!gpio_label)
1113 continue;
1114 /* FIXME */
1115 mode = oxnas_mux_get_func(cio, mask);
1116 seq_printf(s, "[%s] GPIO%s%d: ",
1117 gpio_label, chip->label, i);
1118 if (mode == OXNAS_PINMUX_GPIO) {
1119 pdsr = readl_relaxed(pio + INPUT_VALUE);
1120
1121 seq_printf(s, "[gpio] %s\n",
1122 pdsr & mask ?
1123 "set" : "clear");
1124 } else {
1125 seq_printf(s, "[periph %c]\n",
1126 mode + 'A' - 1);
1127 }
1128 }
1129 }
1130 #else
1131 #define oxnas_gpio_dbg_show NULL
1132 #endif
1133
1134 /* Several AIC controller irqs are dispatched through this GPIO handler.
1135 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1136 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1137 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1138 * handler.
1139 */
1140
1141 static void gpio_irq_mask(struct irq_data *d)
1142 {
1143 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
1144 void __iomem *pio = oxnas_gpio->regbase;
1145 unsigned mask = 1 << d->hwirq;
1146 unsigned type = irqd_get_trigger_type(d);
1147
1148 /* FIXME: need proper lock */
1149 if (type & IRQ_TYPE_EDGE_RISING)
1150 oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
1151 if (type & IRQ_TYPE_EDGE_FALLING)
1152 oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
1153 }
1154
1155 static void gpio_irq_unmask(struct irq_data *d)
1156 {
1157 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
1158 void __iomem *pio = oxnas_gpio->regbase;
1159 unsigned mask = 1 << d->hwirq;
1160 unsigned type = irqd_get_trigger_type(d);
1161
1162 /* FIXME: need proper lock */
1163 if (type & IRQ_TYPE_EDGE_RISING)
1164 oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask);
1165 if (type & IRQ_TYPE_EDGE_FALLING)
1166 oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask);
1167 }
1168
1169
1170 static int gpio_irq_type(struct irq_data *d, unsigned type)
1171 {
1172 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) {
1173 pr_warn("OX820: Unsupported type for irq %d\n",
1174 gpio_to_irq(d->irq));
1175 return -EINVAL;
1176 }
1177 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1178
1179 return 0;
1180 }
1181
1182 static struct irq_chip gpio_irqchip = {
1183 .name = "GPIO",
1184 .irq_disable = gpio_irq_mask,
1185 .irq_mask = gpio_irq_mask,
1186 .irq_unmask = gpio_irq_unmask,
1187 .irq_set_type = gpio_irq_type,
1188 };
1189
1190 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1191 {
1192 struct irq_chip *chip = irq_desc_get_chip(desc);
1193 struct irq_data *idata = irq_desc_get_irq_data(desc);
1194 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata);
1195 void __iomem *pio = oxnas_gpio->regbase;
1196 unsigned long isr;
1197 int n;
1198
1199 chained_irq_enter(chip, desc);
1200 for (;;) {
1201 /* TODO: see if it works */
1202 isr = readl_relaxed(pio + IRQ_PENDING);
1203 if (!isr)
1204 break;
1205 /* acks pending interrupts */
1206 writel_relaxed(isr, pio + IRQ_PENDING);
1207
1208 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1209 generic_handle_irq(irq_find_mapping(oxnas_gpio->domain,
1210 n));
1211 }
1212 }
1213 chained_irq_exit(chip, desc);
1214 /* now it may re-trigger */
1215 }
1216
1217 /*
1218 * This lock class tells lockdep that GPIO irqs are in a different
1219 * category than their parents, so it won't report false recursion.
1220 */
1221 static struct lock_class_key gpio_lock_class;
1222
1223 static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1224 irq_hw_number_t hw)
1225 {
1226 struct oxnas_gpio_chip *oxnas_gpio = h->host_data;
1227
1228 irq_set_lockdep_class(virq, &gpio_lock_class);
1229
1230 irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq);
1231 set_irq_flags(virq, IRQF_VALID);
1232 irq_set_chip_data(virq, oxnas_gpio);
1233
1234 return 0;
1235 }
1236
1237 static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d,
1238 struct device_node *ctrlr,
1239 const u32 *intspec,
1240 unsigned int intsize,
1241 irq_hw_number_t *out_hwirq,
1242 unsigned int *out_type)
1243 {
1244 struct oxnas_gpio_chip *oxnas_gpio = d->host_data;
1245 int ret;
1246 int pin = oxnas_gpio->chip.base + intspec[0];
1247
1248 if (WARN_ON(intsize < 2))
1249 return -EINVAL;
1250 *out_hwirq = intspec[0];
1251 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1252
1253 ret = gpio_request(pin, ctrlr->full_name);
1254 if (ret)
1255 return ret;
1256
1257 ret = gpio_direction_input(pin);
1258 if (ret)
1259 return ret;
1260
1261 return 0;
1262 }
1263
1264 static struct irq_domain_ops oxnas_gpio_ops = {
1265 .map = oxnas_gpio_irq_map,
1266 .xlate = oxnas_gpio_irq_domain_xlate,
1267 };
1268
1269 static int oxnas_gpio_of_irq_setup(struct device_node *node,
1270 struct oxnas_gpio_chip *oxnas_gpio,
1271 unsigned int irq)
1272 {
1273 /* Disable irqs of this controller */
1274 writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE);
1275 writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE);
1276
1277 /* Setup irq domain */
1278 oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio,
1279 &oxnas_gpio_ops, oxnas_gpio);
1280 if (!oxnas_gpio->domain)
1281 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1282
1283 irq_set_chip_data(irq, oxnas_gpio);
1284 irq_set_chained_handler(irq, gpio_irq_handler);
1285
1286 return 0;
1287 }
1288
1289 /* This structure is replicated for each GPIO block allocated at probe time */
1290 static struct gpio_chip oxnas_gpio_template = {
1291 .request = oxnas_gpio_request,
1292 .free = oxnas_gpio_free,
1293 .direction_input = oxnas_gpio_direction_input,
1294 .get = oxnas_gpio_get,
1295 .direction_output = oxnas_gpio_direction_output,
1296 .set = oxnas_gpio_set,
1297 .to_irq = oxnas_gpio_to_irq,
1298 .dbg_show = oxnas_gpio_dbg_show,
1299 .can_sleep = 0,
1300 .ngpio = MAX_NB_GPIO_PER_BANK,
1301 };
1302
1303 static struct of_device_id oxnas_gpio_of_match[] = {
1304 { .compatible = "plxtech,nas782x-gpio"},
1305 { /* sentinel */ }
1306 };
1307
1308 static int oxnas_gpio_probe(struct platform_device *pdev)
1309 {
1310 struct device_node *np = pdev->dev.of_node;
1311 struct resource *res;
1312 struct oxnas_gpio_chip *oxnas_chip = NULL;
1313 struct gpio_chip *chip;
1314 struct pinctrl_gpio_range *range;
1315 int ret = 0;
1316 int irq, i;
1317 int alias_idx = of_alias_get_id(np, "gpio");
1318 uint32_t ngpio;
1319 char **names;
1320
1321 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1322 if (gpio_chips[alias_idx]) {
1323 ret = -EBUSY;
1324 goto err;
1325 }
1326
1327 irq = platform_get_irq(pdev, 0);
1328 if (irq < 0) {
1329 ret = irq;
1330 goto err;
1331 }
1332
1333 oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL);
1334 if (!oxnas_chip) {
1335 ret = -ENOMEM;
1336 goto err;
1337 }
1338
1339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1340 oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1341 if (IS_ERR(oxnas_chip->regbase)) {
1342 ret = PTR_ERR(oxnas_chip->regbase);
1343 goto err;
1344 }
1345
1346 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1347 oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res);
1348 if (IS_ERR(oxnas_chip->ctrlbase)) {
1349 ret = PTR_ERR(oxnas_chip->ctrlbase);
1350 goto err;
1351 }
1352
1353 oxnas_chip->chip = oxnas_gpio_template;
1354
1355 chip = &oxnas_chip->chip;
1356 chip->of_node = np;
1357 chip->label = dev_name(&pdev->dev);
1358 chip->dev = &pdev->dev;
1359 chip->owner = THIS_MODULE;
1360 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1361
1362 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1363 if (ngpio > MAX_NB_GPIO_PER_BANK)
1364 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1365 alias_idx, MAX_NB_GPIO_PER_BANK,
1366 MAX_NB_GPIO_PER_BANK);
1367 else
1368 chip->ngpio = ngpio;
1369 }
1370
1371 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1372 GFP_KERNEL);
1373
1374 if (!names) {
1375 ret = -ENOMEM;
1376 goto err;
1377 }
1378
1379 for (i = 0; i < chip->ngpio; i++)
1380 names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i);
1381
1382 chip->names = (const char *const *)names;
1383
1384 range = &oxnas_chip->range;
1385 range->name = chip->label;
1386 range->id = alias_idx;
1387 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1388
1389 range->npins = chip->ngpio;
1390 range->gc = chip;
1391
1392 ret = gpiochip_add(chip);
1393 if (ret)
1394 goto err;
1395
1396 gpio_chips[alias_idx] = oxnas_chip;
1397 gpio_banks = max(gpio_banks, alias_idx + 1);
1398
1399 oxnas_gpio_of_irq_setup(np, oxnas_chip, irq);
1400
1401 dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase);
1402
1403 return 0;
1404 err:
1405 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1406
1407 return ret;
1408 }
1409
1410 static struct platform_driver oxnas_gpio_driver = {
1411 .driver = {
1412 .name = "gpio-oxnas",
1413 .owner = THIS_MODULE,
1414 .of_match_table = of_match_ptr(oxnas_gpio_of_match),
1415 },
1416 .probe = oxnas_gpio_probe,
1417 };
1418
1419 static struct platform_driver oxnas_pinctrl_driver = {
1420 .driver = {
1421 .name = "pinctrl-oxnas",
1422 .owner = THIS_MODULE,
1423 .of_match_table = of_match_ptr(oxnas_pinctrl_of_match),
1424 },
1425 .probe = oxnas_pinctrl_probe,
1426 .remove = oxnas_pinctrl_remove,
1427 };
1428
1429 static int __init oxnas_pinctrl_init(void)
1430 {
1431 int ret;
1432
1433 ret = platform_driver_register(&oxnas_gpio_driver);
1434 if (ret)
1435 return ret;
1436 return platform_driver_register(&oxnas_pinctrl_driver);
1437 }
1438 arch_initcall(oxnas_pinctrl_init);
1439
1440 static void __exit oxnas_pinctrl_exit(void)
1441 {
1442 platform_driver_unregister(&oxnas_pinctrl_driver);
1443 }
1444
1445 module_exit(oxnas_pinctrl_exit);
1446 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1447 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1448 MODULE_LICENSE("GPL v2");
OpenWrt Source Repository