projects / openwrt / openwrt.git / blob
? search:


54d7f86f6719d552f020aeccb8118c7121dba26c
[openwrt/openwrt.git] / target / linux / pistachio / patches-4.9 / 001-MIPS-DTS-Add-base-device-tree-for-Pistachio-SoC.patch
1 From 8efda11baddf344cbfab01dc016a8fef9bb64641 Mon Sep 17 00:00:00 2001
2 From: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
3 Date: Fri, 14 Oct 2016 11:25:54 +0530
4 Subject: MIPS: DTS: Add base device tree for Pistachio SoC
5
6 Add support for the base Device Tree for Imagination Technologies'
7 Pistachio SoC.
8
9 This commit supports the following peripherals:
10
11 * Clocks
12 * Pinctrl and GPIO
13 * UART
14 * SPI
15 * I2C
16 * PWM
17 * ADC
18 * Watchdog
19 * Ethernet
20 * MMC
21 * DMA engine
22 * Crypto
23 * I2S
24 * SPDIF
25 * Internal DAC
26 * Timer
27 * USB
28 * IR
29 * Interrupt Controller
30
31 Signed-off-by: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
32 Acked-by: James Hartley <james.hartley@imgtec.com>
33 Cc: Rob Herring <robh+dt@kernel.org>
34 Cc: Mark Rutland <mark.rutland@arm.com>
35 Cc: linux-mips@linux-mips.org
36 Cc: devicetree@vger.kernel.org
37 Cc: linux-kernel@vger.kernel.org
38 Patchwork: https://patchwork.linux-mips.org/patch/14393/
39 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
40 ---
41 MAINTAINERS | 2 +-
42 arch/mips/boot/dts/img/pistachio.dtsi | 924 ++++++++++++++++++++++++++++++++++
43 2 files changed, 925 insertions(+), 1 deletion(-)
44 create mode 100644 arch/mips/boot/dts/img/pistachio.dtsi
45
46 diff --git a/MAINTAINERS b/MAINTAINERS
47 index 63cefa6..f0037c7 100644
48 --- a/MAINTAINERS
49 +++ b/MAINTAINERS
50 @@ -9569,7 +9569,7 @@ L: linux-mips@linux-mips.org
51 S: Maintained
52 F: arch/mips/pistachio/
53 F: arch/mips/include/asm/mach-pistachio/
54 -F: arch/mips/boot/dts/pistachio/
55 +F: arch/mips/boot/dts/img/pistachio*
56 F: arch/mips/configs/pistachio*_defconfig
57
58 PKTCDVD DRIVER
59 diff --git a/arch/mips/boot/dts/img/pistachio.dtsi b/arch/mips/boot/dts/img/pistachio.dtsi
60 new file mode 100644
61 index 0000000..57809f6
62 --- /dev/null
63 +++ b/arch/mips/boot/dts/img/pistachio.dtsi
64 @@ -0,0 +1,924 @@
65 +/*
66 + * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
67 + * Copyright (C) 2015 Google, Inc.
68 + *
69 + * This program is free software; you can redistribute it and/or modify
70 + * it under the terms of the GNU General Public License version 2 as
71 + * published by the Free Software Foundation.
72 + */
73 +
74 +#include <dt-bindings/clock/pistachio-clk.h>
75 +#include <dt-bindings/gpio/gpio.h>
76 +#include <dt-bindings/interrupt-controller/irq.h>
77 +#include <dt-bindings/interrupt-controller/mips-gic.h>
78 +#include <dt-bindings/reset/pistachio-resets.h>
79 +
80 +/ {
81 + compatible = "img,pistachio";
82 +
83 + #address-cells = <1>;
84 + #size-cells = <1>;
85 +
86 + interrupt-parent = <&gic>;
87 +
88 + cpus {
89 + #address-cells = <1>;
90 + #size-cells = <0>;
91 +
92 + cpu0: cpu@0 {
93 + device_type = "cpu";
94 + compatible = "mti,interaptiv";
95 + reg = <0>;
96 + clocks = <&clk_core CLK_MIPS_PLL>;
97 + clock-names = "cpu";
98 + clock-latency = <1000>;
99 + operating-points = <
100 + /* kHz uV(dummy) */
101 + 546000 1150000
102 + 520000 1100000
103 + 494000 1000000
104 + 468000 950000
105 + 442000 900000
106 + 416000 800000
107 + >;
108 + };
109 + };
110 +
111 + i2c0: i2c@18100000 {
112 + compatible = "img,scb-i2c";
113 + reg = <0x18100000 0x200>;
114 + interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
115 + clocks = <&clk_periph PERIPH_CLK_I2C0>,
116 + <&cr_periph SYS_CLK_I2C0>;
117 + clock-names = "scb", "sys";
118 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
119 + <&clk_periph PERIPH_CLK_I2C0_DIV>;
120 + assigned-clock-rates = <100000000>, <33333334>;
121 + status = "disabled";
122 + pinctrl-names = "default";
123 + pinctrl-0 = <&i2c0_pins>;
124 +
125 + #address-cells = <1>;
126 + #size-cells = <0>;
127 + };
128 +
129 + i2c1: i2c@18100200 {
130 + compatible = "img,scb-i2c";
131 + reg = <0x18100200 0x200>;
132 + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
133 + clocks = <&clk_periph PERIPH_CLK_I2C1>,
134 + <&cr_periph SYS_CLK_I2C1>;
135 + clock-names = "scb", "sys";
136 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
137 + <&clk_periph PERIPH_CLK_I2C1_DIV>;
138 + assigned-clock-rates = <100000000>, <33333334>;
139 + status = "disabled";
140 + pinctrl-names = "default";
141 + pinctrl-0 = <&i2c1_pins>;
142 +
143 + #address-cells = <1>;
144 + #size-cells = <0>;
145 + };
146 +
147 + i2c2: i2c@18100400 {
148 + compatible = "img,scb-i2c";
149 + reg = <0x18100400 0x200>;
150 + interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
151 + clocks = <&clk_periph PERIPH_CLK_I2C2>,
152 + <&cr_periph SYS_CLK_I2C2>;
153 + clock-names = "scb", "sys";
154 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
155 + <&clk_periph PERIPH_CLK_I2C2_DIV>;
156 + assigned-clock-rates = <100000000>, <33333334>;
157 + status = "disabled";
158 + pinctrl-names = "default";
159 + pinctrl-0 = <&i2c2_pins>;
160 +
161 + #address-cells = <1>;
162 + #size-cells = <0>;
163 + };
164 +
165 + i2c3: i2c@18100600 {
166 + compatible = "img,scb-i2c";
167 + reg = <0x18100600 0x200>;
168 + interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
169 + clocks = <&clk_periph PERIPH_CLK_I2C3>,
170 + <&cr_periph SYS_CLK_I2C3>;
171 + clock-names = "scb", "sys";
172 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
173 + <&clk_periph PERIPH_CLK_I2C3_DIV>;
174 + assigned-clock-rates = <100000000>, <33333334>;
175 + status = "disabled";
176 + pinctrl-names = "default";
177 + pinctrl-0 = <&i2c3_pins>;
178 +
179 + #address-cells = <1>;
180 + #size-cells = <0>;
181 + };
182 +
183 + i2s_in: i2s-in@18100800 {
184 + compatible = "img,i2s-in";
185 + reg = <0x18100800 0x200>;
186 + interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
187 + dmas = <&mdc 30 0xffffffff 0>;
188 + dma-names = "rx";
189 + clocks = <&cr_periph SYS_CLK_I2S_IN>;
190 + clock-names = "sys";
191 + img,i2s-channels = <6>;
192 + pinctrl-names = "default";
193 + pinctrl-0 = <&i2s_in_pins>;
194 + status = "disabled";
195 +
196 + #sound-dai-cells = <0>;
197 + };
198 +
199 + i2s_out: i2s-out@18100a00 {
200 + compatible = "img,i2s-out";
201 + reg = <0x18100a00 0x200>;
202 + interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
203 + dmas = <&mdc 23 0xffffffff 0>;
204 + dma-names = "tx";
205 + clocks = <&cr_periph SYS_CLK_I2S_OUT>,
206 + <&clk_core CLK_I2S>;
207 + clock-names = "sys", "ref";
208 + assigned-clocks = <&clk_core CLK_I2S_DIV>;
209 + assigned-clock-rates = <12288000>;
210 + img,i2s-channels = <6>;
211 + pinctrl-names = "default";
212 + pinctrl-0 = <&i2s_out_pins>;
213 + status = "disabled";
214 + resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
215 + reset-names = "rst";
216 + #sound-dai-cells = <0>;
217 + };
218 +
219 + parallel_out: parallel-audio-out@18100c00 {
220 + compatible = "img,parallel-out";
221 + reg = <0x18100c00 0x100>;
222 + interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
223 + dmas = <&mdc 16 0xffffffff 0>;
224 + dma-names = "tx";
225 + clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
226 + <&clk_core CLK_AUDIO_DAC>;
227 + clock-names = "sys", "ref";
228 + assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
229 + assigned-clock-rates = <12288000>;
230 + status = "disabled";
231 + resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
232 + reset-names = "rst";
233 + #sound-dai-cells = <0>;
234 + };
235 +
236 + spdif_out: spdif-out@18100d00 {
237 + compatible = "img,spdif-out";
238 + reg = <0x18100d00 0x100>;
239 + interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
240 + dmas = <&mdc 14 0xffffffff 0>;
241 + dma-names = "tx";
242 + clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
243 + <&clk_core CLK_SPDIF>;
244 + clock-names = "sys", "ref";
245 + assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
246 + assigned-clock-rates = <12288000>;
247 + pinctrl-names = "default";
248 + pinctrl-0 = <&spdif_out_pin>;
249 + status = "disabled";
250 + resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
251 + reset-names = "rst";
252 + #sound-dai-cells = <0>;
253 + };
254 +
255 + spdif_in: spdif-in@18100e00 {
256 + compatible = "img,spdif-in";
257 + reg = <0x18100e00 0x100>;
258 + interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
259 + dmas = <&mdc 15 0xffffffff 0>;
260 + dma-names = "rx";
261 + clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
262 + clock-names = "sys";
263 + pinctrl-names = "default";
264 + pinctrl-0 = <&spdif_in_pin>;
265 + status = "disabled";
266 +
267 + #sound-dai-cells = <0>;
268 + };
269 +
270 + internal_dac: internal-dac {
271 + compatible = "img,pistachio-internal-dac";
272 + img,cr-top = <&cr_top>;
273 + img,voltage-select = <1>;
274 +
275 + #sound-dai-cells = <0>;
276 + };
277 +
278 + spfi0: spi@18100f00 {
279 + compatible = "img,spfi";
280 + reg = <0x18100f00 0x100>;
281 + interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
282 + clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
283 + clock-names = "sys", "spfi";
284 + dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
285 + dma-names = "rx", "tx";
286 + spfi-max-frequency = <50000000>;
287 + status = "disabled";
288 +
289 + #address-cells = <1>;
290 + #size-cells = <0>;
291 + };
292 +
293 + spfi1: spi@18101000 {
294 + compatible = "img,spfi";
295 + reg = <0x18101000 0x100>;
296 + interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
297 + clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
298 + clock-names = "sys", "spfi";
299 + dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
300 + dma-names = "rx", "tx";
301 + img,supports-quad-mode;
302 + spfi-max-frequency = <50000000>;
303 + status = "disabled";
304 +
305 + #address-cells = <1>;
306 + #size-cells = <0>;
307 + };
308 +
309 + pwm: pwm@18101300 {
310 + compatible = "img,pistachio-pwm";
311 + reg = <0x18101300 0x100>;
312 + clocks = <&clk_periph PERIPH_CLK_PWM>,
313 + <&cr_periph SYS_CLK_PWM>;
314 + clock-names = "pwm", "sys";
315 + img,cr-periph = <&cr_periph>;
316 + #pwm-cells = <2>;
317 + status = "disabled";
318 + };
319 +
320 + uart0: uart@18101400 {
321 + compatible = "snps,dw-apb-uart";
322 + reg = <0x18101400 0x100>;
323 + interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
324 + clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
325 + clock-names = "baudclk", "apb_pclk";
326 + assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
327 + <&clk_core CLK_UART0_DIV>;
328 + reg-shift = <2>;
329 + reg-io-width = <4>;
330 + pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
331 + pinctrl-names = "default";
332 + status = "disabled";
333 + };
334 +
335 + uart1: uart@18101500 {
336 + compatible = "snps,dw-apb-uart";
337 + reg = <0x18101500 0x100>;
338 + interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
339 + clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
340 + clock-names = "baudclk", "apb_pclk";
341 + assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
342 + <&clk_core CLK_UART1_DIV>;
343 + assigned-clock-rates = <114278400>, <1843200>;
344 + reg-shift = <2>;
345 + reg-io-width = <4>;
346 + pinctrl-0 = <&uart1_pins>;
347 + pinctrl-names = "default";
348 + status = "disabled";
349 + };
350 +
351 + adc: adc@18101600 {
352 + compatible = "cosmic,10001-adc";
353 + reg = <0x18101600 0x24>;
354 + adc-reserved-channels = <0x30>;
355 + clocks = <&clk_core CLK_AUX_ADC>;
356 + clock-names = "adc";
357 + assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
358 + <&clk_core CLK_AUX_ADC_DIV>;
359 + assigned-clock-rates = <100000000>, <1000000>;
360 + status = "disabled";
361 +
362 + #io-channel-cells = <1>;
363 + };
364 +
365 + pinctrl: pinctrl@18101c00 {
366 + compatible = "img,pistachio-system-pinctrl";
367 + reg = <0x18101c00 0x400>;
368 +
369 + gpio0: gpio0 {
370 + interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
371 +
372 + gpio-controller;
373 + #gpio-cells = <2>;
374 + gpio-ranges = <&pinctrl 0 0 16>;
375 +
376 + interrupt-controller;
377 + #interrupt-cells = <2>;
378 + };
379 +
380 + gpio1: gpio1 {
381 + interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
382 +
383 + gpio-controller;
384 + #gpio-cells = <2>;
385 + gpio-ranges = <&pinctrl 0 16 16>;
386 +
387 + interrupt-controller;
388 + #interrupt-cells = <2>;
389 + };
390 +
391 + gpio2: gpio2 {
392 + interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
393 +
394 + gpio-controller;
395 + #gpio-cells = <2>;
396 + gpio-ranges = <&pinctrl 0 32 16>;
397 +
398 + interrupt-controller;
399 + #interrupt-cells = <2>;
400 + };
401 +
402 + gpio3: gpio3 {
403 + interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
404 +
405 + gpio-controller;
406 + #gpio-cells = <2>;
407 + gpio-ranges = <&pinctrl 0 48 16>;
408 +
409 + interrupt-controller;
410 + #interrupt-cells = <2>;
411 + };
412 +
413 + gpio4: gpio4 {
414 + interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
415 +
416 + gpio-controller;
417 + #gpio-cells = <2>;
418 + gpio-ranges = <&pinctrl 0 64 16>;
419 +
420 + interrupt-controller;
421 + #interrupt-cells = <2>;
422 + };
423 +
424 + gpio5: gpio5 {
425 + interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
426 +
427 + gpio-controller;
428 + #gpio-cells = <2>;
429 + gpio-ranges = <&pinctrl 0 80 10>;
430 +
431 + interrupt-controller;
432 + #interrupt-cells = <2>;
433 + };
434 +
435 + i2c0_pins: i2c0-pins {
436 + pin_i2c0: i2c0 {
437 + pins = "mfio28", "mfio29";
438 + function = "i2c0";
439 + drive-strength = <4>;
440 + };
441 + };
442 +
443 + i2c1_pins: i2c1-pins {
444 + pin_i2c1: i2c1 {
445 + pins = "mfio30", "mfio31";
446 + function = "i2c1";
447 + drive-strength = <4>;
448 + };
449 + };
450 +
451 + i2c2_pins: i2c2-pins {
452 + pin_i2c2: i2c2 {
453 + pins = "mfio32", "mfio33";
454 + function = "i2c2";
455 + drive-strength = <4>;
456 + };
457 + };
458 +
459 + i2c3_pins: i2c3-pins {
460 + pin_i2c3: i2c3 {
461 + pins = "mfio34", "mfio35";
462 + function = "i2c3";
463 + drive-strength = <4>;
464 + };
465 + };
466 +
467 + spim0_pins: spim0-pins {
468 + pin_spim0: spim0 {
469 + pins = "mfio9", "mfio10";
470 + function = "spim0";
471 + drive-strength = <4>;
472 + };
473 + spim0_clk: spim0-clk {
474 + pins = "mfio8";
475 + function = "spim0";
476 + drive-strength = <4>;
477 + };
478 + };
479 +
480 + spim0_cs0_alt_pin: spim0-cs0-alt-pin {
481 + spim0-cs0 {
482 + pins = "mfio2";
483 + drive-strength = <2>;
484 + };
485 + };
486 +
487 + spim0_cs1_pin: spim0-cs1-pin {
488 + spim0-cs1 {
489 + pins = "mfio1";
490 + drive-strength = <2>;
491 + };
492 + };
493 +
494 + spim0_cs2_pin: spim0-cs2-pin {
495 + spim0-cs2 {
496 + pins = "mfio55";
497 + drive-strength = <2>;
498 + };
499 + };
500 +
501 + spim0_cs2_alt_pin: spim0-cs2-alt-pin {
502 + spim0-cs2 {
503 + pins = "mfio28";
504 + drive-strength = <2>;
505 + };
506 + };
507 +
508 + spim0_cs3_pin: spim0-cs3-pin {
509 + spim0-cs3 {
510 + pins = "mfio56";
511 + drive-strength = <2>;
512 + };
513 + };
514 +
515 + spim0_cs3_alt_pin: spim0-cs3-alt-pin {
516 + spim0-cs3 {
517 + pins = "mfio29";
518 + drive-strength = <2>;
519 + };
520 + };
521 +
522 + spim0_cs4_pin: spim0-cs4-pin {
523 + spim0-cs4 {
524 + pins = "mfio57";
525 + drive-strength = <2>;
526 + };
527 + };
528 +
529 + spim0_cs4_alt_pin: spim0-cs4-alt-pin {
530 + spim0-cs4 {
531 + pins = "mfio30";
532 + drive-strength = <2>;
533 + };
534 + };
535 +
536 + spim1_pins: spim1-pins {
537 + spim1 {
538 + pins = "mfio3", "mfio4", "mfio5";
539 + function = "spim1";
540 + drive-strength = <2>;
541 + };
542 + };
543 +
544 + spim1_quad_pins: spim1-quad-pins {
545 + spim1-quad {
546 + pins = "mfio6", "mfio7";
547 + function = "spim1";
548 + drive-strength = <2>;
549 + };
550 + };
551 +
552 + spim1_cs0_pin: spim1-cs0-pins {
553 + spim1-cs0 {
554 + pins = "mfio0";
555 + function = "spim1";
556 + drive-strength = <2>;
557 + };
558 + };
559 +
560 + spim1_cs1_pin: spim1-cs1-pin {
561 + spim1-cs1 {
562 + pins = "mfio1";
563 + function = "spim1";
564 + drive-strength = <2>;
565 + };
566 + };
567 +
568 + spim1_cs1_alt_pin: spim1-cs1-alt-pin {
569 + spim1-cs1 {
570 + pins = "mfio58";
571 + function = "spim1";
572 + drive-strength = <2>;
573 + };
574 + };
575 +
576 + spim1_cs2_pin: spim1-cs2-pin {
577 + spim1-cs2 {
578 + pins = "mfio2";
579 + function = "spim1";
580 + drive-strength = <2>;
581 + };
582 + };
583 +
584 + spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
585 + spim1-cs2 {
586 + pins = "mfio31";
587 + function = "spim1";
588 + drive-strength = <2>;
589 + };
590 + };
591 +
592 + spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
593 + spim1-cs2 {
594 + pins = "mfio55";
595 + function = "spim1";
596 + drive-strength = <2>;
597 + };
598 + };
599 +
600 + spim1_cs3_pin: spim1-cs3-pin {
601 + spim1-cs3 {
602 + pins = "mfio56";
603 + function = "spim1";
604 + drive-strength = <2>;
605 + };
606 + };
607 +
608 + spim1_cs4_pin: spim1-cs4-pin {
609 + spim1-cs4 {
610 + pins = "mfio57";
611 + function = "spim1";
612 + drive-strength = <2>;
613 + };
614 + };
615 +
616 + uart0_pins: uart0-pins {
617 + uart0 {
618 + pins = "mfio55", "mfio56";
619 + function = "uart0";
620 + drive-strength = <2>;
621 + };
622 + };
623 +
624 + uart0_rts_cts_pins: uart0-rts-cts-pins {
625 + uart0-rts-cts {
626 + pins = "mfio57", "mfio58";
627 + function = "uart0";
628 + drive-strength = <2>;
629 + };
630 + };
631 +
632 + uart1_pins: uart1-pins {
633 + uart1 {
634 + pins = "mfio59", "mfio60";
635 + function = "uart1";
636 + drive-strength = <2>;
637 + };
638 + };
639 +
640 + uart1_rts_cts_pins: uart1-rts-cts-pins {
641 + uart1-rts-cts {
642 + pins = "mfio1", "mfio2";
643 + function = "uart1";
644 + drive-strength = <2>;
645 + };
646 + };
647 +
648 + enet_pins: enet-pins {
649 + pin_enet: enet {
650 + pins = "mfio63", "mfio64", "mfio65", "mfio66",
651 + "mfio67", "mfio68", "mfio69", "mfio70";
652 + function = "eth";
653 + slew-rate = <1>;
654 + drive-strength = <4>;
655 + };
656 + pin_enet_phy_clk: enet-phy-clk {
657 + pins = "mfio71";
658 + function = "eth";
659 + slew-rate = <1>;
660 + drive-strength = <8>;
661 + };
662 + };
663 +
664 + sdhost_pins: sdhost-pins {
665 + pin_sdhost_clk: sdhost-clk {
666 + pins = "mfio15";
667 + function = "sdhost";
668 + slew-rate = <1>;
669 + drive-strength = <4>;
670 + };
671 + pin_sdhost_cmd: sdhost-cmd {
672 + pins = "mfio16";
673 + function = "sdhost";
674 + slew-rate = <1>;
675 + drive-strength = <4>;
676 + };
677 + pin_sdhost_data: sdhost-data {
678 + pins = "mfio17", "mfio18", "mfio19", "mfio20",
679 + "mfio21", "mfio22", "mfio23", "mfio24";
680 + function = "sdhost";
681 + slew-rate = <1>;
682 + drive-strength = <4>;
683 + };
684 + pin_sdhost_power_select: sdhost-power-select {
685 + pins = "mfio25";
686 + function = "sdhost";
687 + slew-rate = <1>;
688 + drive-strength = <2>;
689 + };
690 + pin_sdhost_card_detect: sdhost-card-detect {
691 + pins = "mfio26";
692 + function = "sdhost";
693 + drive-strength = <2>;
694 + };
695 + pin_sdhost_write_protect: sdhost-write-protect {
696 + pins = "mfio27";
697 + function = "sdhost";
698 + drive-strength = <2>;
699 + };
700 + };
701 +
702 + ir_pin: ir-pin {
703 + ir-data {
704 + pins = "mfio72";
705 + function = "ir";
706 + drive-strength = <2>;
707 + };
708 + };
709 +
710 + pwmpdm0_pin: pwmpdm0-pin {
711 + pwmpdm0 {
712 + pins = "mfio73";
713 + function = "pwmpdm";
714 + drive-strength = <2>;
715 + };
716 + };
717 +
718 + pwmpdm1_pin: pwmpdm1-pin {
719 + pwmpdm1 {
720 + pins = "mfio74";
721 + function = "pwmpdm";
722 + drive-strength = <2>;
723 + };
724 + };
725 +
726 + pwmpdm2_pin: pwmpdm2-pin {
727 + pwmpdm2 {
728 + pins = "mfio75";
729 + function = "pwmpdm";
730 + drive-strength = <2>;
731 + };
732 + };
733 +
734 + pwmpdm3_pin: pwmpdm3-pin {
735 + pwmpdm3 {
736 + pins = "mfio76";
737 + function = "pwmpdm";
738 + drive-strength = <2>;
739 + };
740 + };
741 +
742 + dac_clk_pin: dac-clk-pin {
743 + pin_dac_clk: dac-clk {
744 + pins = "mfio45";
745 + function = "i2s_dac_clk";
746 + drive-strength = <4>;
747 + };
748 + };
749 +
750 + i2s_mclk_pin: i2s-mclk-pin {
751 + pin_i2s_mclk: i2s-mclk {
752 + pins = "mfio36";
753 + function = "i2s_out";
754 + drive-strength = <4>;
755 + };
756 + };
757 +
758 + spdif_out_pin: spdif-out-pin {
759 + spdif-out {
760 + pins = "mfio61";
761 + function = "spdif_out";
762 + slew-rate = <1>;
763 + drive-strength = <2>;
764 + };
765 + };
766 +
767 + spdif_in_pin: spdif-in-pin {
768 + spdif-in {
769 + pins = "mfio62";
770 + function = "spdif_in";
771 + drive-strength = <2>;
772 + };
773 + };
774 +
775 + i2s_out_pins: i2s-out-pins {
776 + pins_i2s_out_clk: i2s-out-clk {
777 + pins = "mfio37", "mfio38";
778 + function = "i2s_out";
779 + drive-strength = <4>;
780 + };
781 + pins_i2s_out: i2s-out {
782 + pins = "mfio39", "mfio40",
783 + "mfio41", "mfio42",
784 + "mfio43", "mfio44";
785 + function = "i2s_out";
786 + drive-strength = <2>;
787 + };
788 + };
789 +
790 + i2s_in_pins: i2s-in-pins {
791 + i2s-in {
792 + pins = "mfio47", "mfio48", "mfio49",
793 + "mfio50", "mfio51", "mfio52",
794 + "mfio53", "mfio54";
795 + function = "i2s_in";
796 + drive-strength = <2>;
797 + };
798 + };
799 + };
800 +
801 + timer: timer@18102000 {
802 + compatible = "img,pistachio-gptimer";
803 + reg = <0x18102000 0x100>;
804 + interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
805 + clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
806 + <&cr_periph SYS_CLK_TIMER>;
807 + clock-names = "fast", "sys";
808 + img,cr-periph = <&cr_periph>;
809 + };
810 +
811 + wdt: watchdog@18102100 {
812 + compatible = "img,pdc-wdt";
813 + reg = <0x18102100 0x100>;
814 + interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
815 + clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
816 + clock-names = "wdt", "sys";
817 + assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
818 + <&clk_periph PERIPH_CLK_WD_DIV>;
819 + assigned-clock-rates = <4000000>, <32768>;
820 + };
821 +
822 + ir: ir@18102200 {
823 + compatible = "img,ir-rev1";
824 + reg = <0x18102200 0x100>;
825 + interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
826 + clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
827 + clock-names = "core", "sys";
828 + assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
829 + <&clk_periph PERIPH_CLK_IR_DIV>;
830 + assigned-clock-rates = <4000000>, <32768>;
831 + pinctrl-0 = <&ir_pin>;
832 + pinctrl-names = "default";
833 + status = "disabled";
834 + };
835 +
836 + usb: usb@18120000 {
837 + compatible = "snps,dwc2";
838 + reg = <0x18120000 0x1c000>;
839 + interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
840 + phys = <&usb_phy>;
841 + phy-names = "usb2-phy";
842 + g-tx-fifo-size = <256 256 256 256>;
843 + status = "disabled";
844 + };
845 +
846 + enet: ethernet@18140000 {
847 + compatible = "snps,dwmac";
848 + reg = <0x18140000 0x2000>;
849 + interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
850 + interrupt-names = "macirq";
851 + clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
852 + clock-names = "stmmaceth", "pclk";
853 + assigned-clocks = <&clk_core CLK_ENET_MUX>,
854 + <&clk_core CLK_ENET_DIV>;
855 + assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
856 + assigned-clock-rates = <0>, <50000000>;
857 + pinctrl-0 = <&enet_pins>;
858 + pinctrl-names = "default";
859 + phy-mode = "rmii";
860 + status = "disabled";
861 + };
862 +
863 + sdhost: mmc@18142000 {
864 + compatible = "img,pistachio-dw-mshc";
865 + reg = <0x18142000 0x400>;
866 + interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
867 + clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
868 + clock-names = "ciu", "biu";
869 + pinctrl-0 = <&sdhost_pins>;
870 + pinctrl-names = "default";
871 + fifo-depth = <0x20>;
872 + num-slots = <1>;
873 + clock-frequency = <50000000>;
874 + bus-width = <8>;
875 + cap-mmc-highspeed;
876 + cap-sd-highspeed;
877 + status = "disabled";
878 + };
879 +
880 + sram: sram@1b000000 {
881 + compatible = "mmio-sram";
882 + reg = <0x1b000000 0x10000>;
883 + };
884 +
885 + mdc: dma-controller@18143000 {
886 + compatible = "img,pistachio-mdc-dma";
887 + reg = <0x18143000 0x1000>;
888 + interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
889 + <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
890 + <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
891 + <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
892 + <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
893 + <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
894 + <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
895 + <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
896 + <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
897 + <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
898 + <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
899 + <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
900 + clocks = <&cr_periph SYS_CLK_MDC>;
901 + clock-names = "sys";
902 +
903 + img,max-burst-multiplier = <16>;
904 + img,cr-periph = <&cr_periph>;
905 +
906 + #dma-cells = <3>;
907 + };
908 +
909 + clk_core: clk@18144000 {
910 + compatible = "img,pistachio-clk", "syscon";
911 + clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
912 + <&cr_top EXT_CLK_ENET_IN>;
913 + clock-names = "xtal", "audio_refclk_ext_gate",
914 + "ext_enet_in_gate";
915 + reg = <0x18144000 0x800>;
916 + #clock-cells = <1>;
917 + };
918 +
919 + clk_periph: clk@18144800 {
920 + compatible = "img,pistachio-clk-periph";
921 + reg = <0x18144800 0x1000>;
922 + clocks = <&clk_core CLK_PERIPH_SYS>;
923 + clock-names = "periph_sys_core";
924 + #clock-cells = <1>;
925 + };
926 +
927 + cr_periph: clk@18148000 {
928 + compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
929 + reg = <0x18148000 0x1000>;
930 + clocks = <&clk_periph PERIPH_CLK_SYS>;
931 + clock-names = "sys";
932 + #clock-cells = <1>;
933 +
934 + pistachio_reset: reset-controller {
935 + compatible = "img,pistachio-reset";
936 + #reset-cells = <1>;
937 + };
938 + };
939 +
940 + cr_top: clk@18149000 {
941 + compatible = "img,pistachio-cr-top", "syscon";
942 + reg = <0x18149000 0x200>;
943 + #clock-cells = <1>;
944 + };
945 +
946 + hash: hash@18149600 {
947 + compatible = "img,hash-accelerator";
948 + reg = <0x18149600 0x100>, <0x18101100 0x4>;
949 + interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
950 + dmas = <&mdc 8 0xffffffff 0>;
951 + dma-names = "tx";
952 + clocks = <&cr_periph SYS_CLK_HASH>,
953 + <&clk_periph PERIPH_CLK_ROM>;
954 + clock-names = "sys", "hash";
955 + };
956 +
957 + gic: interrupt-controller@1bdc0000 {
958 + compatible = "mti,gic";
959 + reg = <0x1bdc0000 0x20000>;
960 +
961 + interrupt-controller;
962 + #interrupt-cells = <3>;
963 +
964 + timer {
965 + compatible = "mti,gic-timer";
966 + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
967 + clocks = <&clk_core CLK_MIPS>;
968 + };
969 + };
970 +
971 + usb_phy: usb-phy {
972 + compatible = "img,pistachio-usb-phy";
973 + clocks = <&clk_core CLK_USB_PHY>;
974 + clock-names = "usb_phy";
975 + assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
976 + assigned-clock-rates = <50000000>;
977 + img,refclk = <0x2>;
978 + img,cr-top = <&cr_top>;
979 + #phy-cells = <0>;
980 + };
981 +
982 + xtal: xtal {
983 + compatible = "fixed-clock";
984 + #clock-cells = <0>;
985 + clock-frequency = <52000000>;
986 + clock-output-names = "xtal";
987 + };
988 +};
989 --
990 2.7.4
991
OpenWrt Source Repository