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[openwrt/openwrt.git] / target / linux / ppc40x / patches-2.6.30 / 006-magicboxv2.patch
1 --- /dev/null
2 +++ b/arch/powerpc/boot/cuboot-magicboxv2.c
3 @@ -0,0 +1,41 @@
4 +/*
5 + * Old U-boot compatibility for Magicbox v2
6 + *
7 + * Author: Imre Kaloz <kaloz@openwrt.org>
8 + *
9 + * This program is free software; you can redistribute it and/or modify it
10 + * under the terms of the GNU General Public License version 2 as published
11 + * by the Free Software Foundation.
12 + */
13 +
14 +#include "ops.h"
15 +#include "io.h"
16 +#include "dcr.h"
17 +#include "stdio.h"
18 +#include "4xx.h"
19 +#include "44x.h"
20 +#include "cuboot.h"
21 +
22 +#define TARGET_4xx
23 +#define TARGET_405EP
24 +#include "ppcboot.h"
25 +
26 +static bd_t bd;
27 +
28 +static void magicboxv2_fixups(void)
29 +{
30 + ibm405ep_fixup_clocks(25000000);
31 + ibm4xx_sdram_fixup_memsize();
32 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
33 +}
34 +
35 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
36 + unsigned long r6, unsigned long r7)
37 +{
38 + CUBOOT_INIT();
39 + platform_ops.fixups = magicboxv2_fixups;
40 + platform_ops.exit = ibm40x_dbcr_reset;
41 + fdt_init(_dtb_start);
42 + serial_console_init();
43 +}
44 +
45 --- /dev/null
46 +++ b/arch/powerpc/boot/dts/magicboxv2.dts
47 @@ -0,0 +1,250 @@
48 +/*
49 + * Device Tree Source for Magicbox v2
50 + *
51 + * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
52 + *
53 + * Based on walnut.dts
54 + *
55 + * This file is licensed under the terms of the GNU General Public
56 + * License version 2. This program is licensed "as is" without
57 + * any warranty of any kind, whether express or implied.
58 + */
59 +
60 +/dts-v1/;
61 +
62 +/ {
63 + #address-cells = <1>;
64 + #size-cells = <1>;
65 + model = "magicboxv2";
66 + compatible = "magicboxv2";
67 + dcr-parent = <&{/cpus/cpu@0}>;
68 +
69 + aliases {
70 + ethernet0 = &EMAC0;
71 + ethernet1 = &EMAC1;
72 + serial0 = &UART0;
73 + serial1 = &UART1;
74 + };
75 +
76 + cpus {
77 + #address-cells = <1>;
78 + #size-cells = <0>;
79 +
80 + cpu@0 {
81 + device_type = "cpu";
82 + model = "PowerPC,405EP";
83 + reg = <0x00000000>;
84 + clock-frequency = <0xbebc200>; /* Filled in by zImage */
85 + timebase-frequency = <0>; /* Filled in by zImage */
86 + i-cache-line-size = <20>;
87 + d-cache-line-size = <20>;
88 + i-cache-size = <4000>;
89 + d-cache-size = <4000>;
90 + dcr-controller;
91 + dcr-access-method = "native";
92 + };
93 + };
94 +
95 + memory {
96 + device_type = "memory";
97 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
98 + };
99 +
100 + UIC0: interrupt-controller {
101 + compatible = "ibm,uic";
102 + interrupt-controller;
103 + cell-index = <0>;
104 + dcr-reg = <0x0c0 0x009>;
105 + #address-cells = <0>;
106 + #size-cells = <0>;
107 + #interrupt-cells = <2>;
108 + };
109 +
110 + plb {
111 + compatible = "ibm,plb3";
112 + #address-cells = <1>;
113 + #size-cells = <1>;
114 + ranges;
115 + clock-frequency = <0>; /* Filled in by zImage */
116 +
117 + SDRAM0: memory-controller {
118 + compatible = "ibm,sdram-405ep";
119 + dcr-reg = <0x010 0x002>;
120 + };
121 +
122 + MAL: mcmal {
123 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
124 + dcr-reg = <0x180 0x062>;
125 + num-tx-chans = <4>;
126 + num-rx-chans = <2>;
127 + interrupt-parent = <&UIC0>;
128 + interrupts = <
129 + 0xb 0x4 /* TXEOB */
130 + 0xc 0x4 /* RXEOB */
131 + 0xa 0x4 /* SERR */
132 + 0xd 0x4 /* TXDE */
133 + 0xe 0x4 /* RXDE */>;
134 + };
135 +
136 + POB0: opb {
137 + compatible = "ibm,opb-405ep", "ibm,opb";
138 + #address-cells = <1>;
139 + #size-cells = <1>;
140 + ranges = <0xef600000 0xef600000 0x00a00000>;
141 + dcr-reg = <0x0a0 0x005>;
142 + clock-frequency = <0>; /* Filled in by zImage */
143 +
144 + UART0: serial@ef600300 {
145 + device_type = "serial";
146 + compatible = "ns16550";
147 + reg = <0xef600300 0x00000008>;
148 + virtual-reg = <0xef600300>;
149 + clock-frequency = <0>; /* Filled in by zImage */
150 + current-speed = <115200>;
151 + interrupt-parent = <&UIC0>;
152 + interrupts = <0x0 0x4>;
153 + };
154 +
155 + UART1: serial@ef600400 {
156 + device_type = "serial";
157 + compatible = "ns16550";
158 + reg = <0xef600400 0x00000008>;
159 + virtual-reg = <0xef600400>;
160 + clock-frequency = <0>; /* Filled in by zImage */
161 + current-speed = <115200>;
162 + interrupt-parent = <&UIC0>;
163 + interrupts = <0x1 0x4>;
164 + };
165 +
166 + IIC: i2c@ef600500 {
167 + compatible = "ibm,iic-405ep", "ibm,iic";
168 + reg = <0xef600500 0x00000011>;
169 + interrupt-parent = <&UIC0>;
170 + interrupts = <0x2 0x4>;
171 + };
172 +
173 + GPIO: gpio@ef600700 {
174 + compatible = "ibm,gpio-405ep";
175 + reg = <0xef600700 0x00000020>;
176 + };
177 +
178 + EMAC0: ethernet@ef600800 {
179 + linux,network-index = <0x0>;
180 + device_type = "network";
181 + compatible = "ibm,emac-405ep", "ibm,emac";
182 + interrupt-parent = <&UIC0>;
183 + interrupts = <
184 + 0xf 0x4 /* Ethernet */
185 + 0x9 0x4 /* Ethernet Wake Up */>;
186 + local-mac-address = [000000000000]; /* Filled in by zImage */
187 + reg = <0xef600800 0x00000070>;
188 + mal-device = <&MAL>;
189 + mal-tx-channel = <0>;
190 + mal-rx-channel = <0>;
191 + cell-index = <0>;
192 + max-frame-size = <0x5dc>;
193 + rx-fifo-size = <0x1000>;
194 + tx-fifo-size = <0x800>;
195 + phy-mode = "mii";
196 + phy-map = <0x00000000>;
197 + };
198 + EMAC1: ethernet@ef600900 {
199 + linux,network-index = <0x1>;
200 + device_type = "network";
201 + compatible = "ibm,emac-405ep", "ibm,emac";
202 + interrupt-parent = <&UIC0>;
203 + interrupts = <
204 + 0x11 0x4 /* Ethernet */
205 + 0x09 0x4 /* Ethernet Wake Up */>;
206 + local-mac-address = [000000000000]; /* Filled in by zImage */
207 + reg = <0xef600900 0x00000070>;
208 + mal-device = <&MAL>;
209 + mal-tx-channel = <2>;
210 + mal-rx-channel = <1>;
211 + cell-index = <1>;
212 + max-frame-size = <0x5dc>;
213 + rx-fifo-size = <0x1000>;
214 + tx-fifo-size = <0x800>;
215 + mdio-device = <&EMAC0>;
216 + phy-mode = "mii";
217 + phy-map = <0x00000001>;
218 + };
219 +
220 + };
221 +
222 + EBC0: ebc {
223 + compatible = "ibm,ebc-405ep", "ibm,ebc";
224 + dcr-reg = <0x012 0x002>;
225 + #address-cells = <2>;
226 + #size-cells = <1>;
227 + /* The ranges property is supplied by the bootwrapper
228 + * and is based on the firmware's configuration of the
229 + * EBC bridge
230 + */
231 + clock-frequency = <0>; /* Filled in by zImage */
232 +
233 + nor_flash@ffc00000 {
234 + compatible = "cfi-flash";
235 + bank-width = <2>;
236 + reg = <0x00000000 0xffc00000 0x00400000>;
237 + #address-cells = <1>;
238 + #size-cells = <1>;
239 + partition@0 {
240 + label = "linux";
241 + reg = <0x0 0x120000>;
242 + };
243 + partition@120000 {
244 + label = "rootfs";
245 + reg = <0x120000 0x2a0000>;
246 + };
247 + partition@3c0000 {
248 + label = "u-boot";
249 + reg = <0x3c0000 0x30000>;
250 + read-only;
251 + };
252 + };
253 + };
254 +
255 + PCI0: pci@ec000000 {
256 + device_type = "pci";
257 + #interrupt-cells = <1>;
258 + #size-cells = <2>;
259 + #address-cells = <3>;
260 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
261 + primary;
262 + reg = <0xeec00000 0x00000008 /* Config space access */
263 + 0xeed80000 0x00000004 /* IACK */
264 + 0xeed80000 0x00000004 /* Special cycle */
265 + 0xef480000 0x00000040>; /* Internal registers */
266 +
267 + /* Outbound ranges, one memory and one IO,
268 + * later cannot be changed. Chip supports a second
269 + * IO range but we don't use it for now
270 + */
271 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
272 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
273 +
274 + /* Inbound 2GB range starting at 0 */
275 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
276 +
277 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
278 + interrupt-map = <
279 + /* IDSEL 1 */
280 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
281 +
282 + /* IDSEL 2 */
283 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
284 +
285 + /* IDSEL 3 */
286 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
287 +
288 + /* IDSEL 4 */
289 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
290 + >;
291 + };
292 + };
293 +
294 + chosen {
295 + linux,stdout-path = "/plb/opb/serial@ef600300";
296 + };
297 +};
298 --- a/arch/powerpc/boot/Makefile
299 +++ b/arch/powerpc/boot/Makefile
300 @@ -75,7 +75,8 @@
301 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
302 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
303 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
304 - cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c
305 + cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c \
306 + cuboot-magicboxv2.c
307 src-boot := $(src-wlib) $(src-plat) empty.c
308
309 src-boot := $(addprefix $(obj)/, $(src-boot))
310 @@ -193,6 +194,7 @@
311 image-$(CONFIG_WALNUT) += treeImage.walnut
312 image-$(CONFIG_ACADIA) += cuImage.acadia
313 image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
314 +image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
315
316 # Board ports in arch/powerpc/platform/44x/Kconfig
317 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
318 --- a/arch/powerpc/platforms/40x/Kconfig
319 +++ b/arch/powerpc/platforms/40x/Kconfig
320 @@ -59,6 +59,16 @@
321 help
322 This option enables support for the Magicbox v1 board.
323
324 +config MAGICBOXV2
325 + bool "Magicbox v2"
326 + depends on 40x
327 + default n
328 + select PPC40x_SIMPLE
329 + select 405EP
330 + select PCI
331 + help
332 + This option enables support for the Magicbox v2 board.
333 +
334 config MAKALU
335 bool "Makalu"
336 depends on 40x
337 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
338 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
339 @@ -53,6 +53,7 @@
340 static char *board[] __initdata = {
341 "amcc,acadia",
342 "magicboxv1",
343 + "magicboxv2",
344 };
345
346 static int __init ppc40x_probe(void)
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