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[openwrt/openwrt.git] / target / linux / ppc40x / patches / 007-openrb-light.patch
1 --- a/arch/powerpc/boot/Makefile
2 +++ b/arch/powerpc/boot/Makefile
3 @@ -70,7 +70,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82
4 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
5 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
6 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
7 - cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c
8 + cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c \
9 + cuboot-openrb-light.c
10 src-boot := $(src-wlib) $(src-plat) empty.c
11
12 src-boot := $(addprefix $(obj)/, $(src-boot))
13 @@ -216,6 +217,7 @@ image-$(CONFIG_WALNUT) += treeImage.wa
14 image-$(CONFIG_ACADIA) += cuImage.acadia
15 image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
16 image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
17 +image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light
18
19 # Board ports in arch/powerpc/platform/44x/Kconfig
20 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
21 --- a/arch/powerpc/platforms/40x/Kconfig
22 +++ b/arch/powerpc/platforms/40x/Kconfig
23 @@ -79,6 +79,16 @@ config MAKALU
24 help
25 This option enables support for the AMCC PPC405EX board.
26
27 +config OPENRB_LIGHT
28 + bool "OpenRB Light"
29 + depends on 40x
30 + default n
31 + select PPC40x_SIMPLE
32 + select 405EP
33 + select PCI
34 + help
35 + This option enables support for the OpenRB Light board.
36 +
37 #config REDWOOD_5
38 # bool "Redwood-5"
39 # depends on 40x
40 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
41 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
42 @@ -54,6 +54,7 @@ static char *board[] __initdata = {
43 "amcc,acadia",
44 "magicboxv1",
45 "magicboxv2",
46 + "openrb,light",
47 };
48
49 static int __init ppc40x_probe(void)
50 --- /dev/null
51 +++ b/arch/powerpc/boot/cuboot-openrb-light.c
52 @@ -0,0 +1,41 @@
53 +/*
54 + * Old U-boot compatibility for OpenRB Light board
55 + *
56 + * Author: Gabor Juhos <juhosg@openwrt.org>
57 + *
58 + * This program is free software; you can redistribute it and/or modify it
59 + * under the terms of the GNU General Public License version 2 as published
60 + * by the Free Software Foundation.
61 + */
62 +
63 +#include "ops.h"
64 +#include "io.h"
65 +#include "dcr.h"
66 +#include "stdio.h"
67 +#include "4xx.h"
68 +#include "44x.h"
69 +#include "cuboot.h"
70 +
71 +#define TARGET_4xx
72 +#define TARGET_405EP
73 +#include "ppcboot.h"
74 +
75 +static bd_t bd;
76 +
77 +static void openrb_light_fixups(void)
78 +{
79 + ibm405ep_fixup_clocks(33333000);
80 + ibm4xx_sdram_fixup_memsize();
81 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
82 +}
83 +
84 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
85 + unsigned long r6, unsigned long r7)
86 +{
87 + CUBOOT_INIT();
88 + platform_ops.fixups = openrb_light_fixups;
89 + platform_ops.exit = ibm40x_dbcr_reset;
90 + fdt_init(_dtb_start);
91 + serial_console_init();
92 +}
93 +
94 --- /dev/null
95 +++ b/arch/powerpc/boot/dts/openrb-light.dts
96 @@ -0,0 +1,244 @@
97 +/*
98 + * Device Tree Source for OpenRB Light board
99 + *
100 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
101 + *
102 + * Based on magicboxv2.dts
103 + *
104 + * This file is licensed under the terms of the GNU General Public
105 + * License version 2. This program is licensed "as is" without
106 + * any warranty of any kind, whether express or implied.
107 + */
108 +
109 +/dts-v1/;
110 +
111 +/ {
112 + #address-cells = <1>;
113 + #size-cells = <1>;
114 + model = "openrb,light";
115 + compatible = "openrb,light";
116 + dcr-parent = <&{/cpus/cpu@0}>;
117 +
118 + aliases {
119 + ethernet0 = &EMAC0;
120 + serial0 = &UART0;
121 + serial1 = &UART1;
122 + };
123 +
124 + cpus {
125 + #address-cells = <1>;
126 + #size-cells = <0>;
127 +
128 + cpu@0 {
129 + device_type = "cpu";
130 + model = "PowerPC,405EP";
131 + reg = <0x00000000>;
132 + clock-frequency = <0xbebc200>; /* Filled in by zImage */
133 + timebase-frequency = <0>; /* Filled in by zImage */
134 + i-cache-line-size = <20>;
135 + d-cache-line-size = <20>;
136 + i-cache-size = <4000>;
137 + d-cache-size = <4000>;
138 + dcr-controller;
139 + dcr-access-method = "native";
140 + };
141 + };
142 +
143 + memory {
144 + device_type = "memory";
145 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
146 + };
147 +
148 + UIC0: interrupt-controller {
149 + compatible = "ibm,uic";
150 + interrupt-controller;
151 + cell-index = <0>;
152 + dcr-reg = <0x0c0 0x009>;
153 + #address-cells = <0>;
154 + #size-cells = <0>;
155 + #interrupt-cells = <2>;
156 + };
157 +
158 + plb {
159 + compatible = "ibm,plb3";
160 + #address-cells = <1>;
161 + #size-cells = <1>;
162 + ranges;
163 + clock-frequency = <0>; /* Filled in by zImage */
164 +
165 + SDRAM0: memory-controller {
166 + compatible = "ibm,sdram-405ep";
167 + dcr-reg = <0x010 0x002>;
168 + };
169 +
170 + MAL: mcmal {
171 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
172 + dcr-reg = <0x180 0x062>;
173 + num-tx-chans = <4>;
174 + num-rx-chans = <2>;
175 + interrupt-parent = <&UIC0>;
176 + interrupts = <
177 + 0xb 0x4 /* TXEOB */
178 + 0xc 0x4 /* RXEOB */
179 + 0xa 0x4 /* SERR */
180 + 0xd 0x4 /* TXDE */
181 + 0xe 0x4 /* RXDE */>;
182 + };
183 +
184 + OPB0: opb {
185 + compatible = "ibm,opb-405ep", "ibm,opb";
186 + #address-cells = <1>;
187 + #size-cells = <1>;
188 + ranges = <0xef600000 0xef600000 0x00a00000>;
189 + dcr-reg = <0x0a0 0x005>;
190 + clock-frequency = <0>; /* Filled in by zImage */
191 +
192 + UART0: serial@ef600300 {
193 + device_type = "serial";
194 + compatible = "ns16550";
195 + reg = <0xef600300 0x00000008>;
196 + virtual-reg = <0xef600300>;
197 + clock-frequency = <0>; /* Filled in by zImage */
198 + current-speed = <115200>;
199 + interrupt-parent = <&UIC0>;
200 + interrupts = <0x0 0x4>;
201 + };
202 +
203 + UART1: serial@ef600400 {
204 + device_type = "serial";
205 + compatible = "ns16550";
206 + reg = <0xef600400 0x00000008>;
207 + virtual-reg = <0xef600400>;
208 + clock-frequency = <0>; /* Filled in by zImage */
209 + current-speed = <115200>;
210 + interrupt-parent = <&UIC0>;
211 + interrupts = <0x1 0x4>;
212 + };
213 +
214 + IIC: i2c@ef600500 {
215 + #address-cells = <1>;
216 + #size-cells = <0>;
217 + compatible = "ibm,iic-405ep", "ibm,iic";
218 + reg = <0xef600500 0x00000011>;
219 + interrupt-parent = <&UIC0>;
220 + interrupts = <0x2 0x4>;
221 +
222 + eeprom@50 {
223 + compatible = "at24,24c16";
224 + reg = <0x50>;
225 + };
226 + };
227 +
228 + GPIO0: gpio-controller@ef600700 {
229 + compatible = "ibm,ppc4xx-gpio";
230 + reg = <0xef600700 0x00000020>;
231 + #gpio-cells = <2>;
232 + gpio-controller;
233 + };
234 +
235 + EMAC0: ethernet@ef600800 {
236 + linux,network-index = <0x0>;
237 + device_type = "network";
238 + compatible = "ibm,emac-405ep", "ibm,emac";
239 + interrupt-parent = <&UIC0>;
240 + interrupts = <
241 + 0xf 0x4 /* Ethernet */
242 + 0x9 0x4 /* Ethernet Wake Up */>;
243 + local-mac-address = [000000000000]; /* Filled in by zImage */
244 + reg = <0xef600800 0x00000070>;
245 + mal-device = <&MAL>;
246 + mal-tx-channel = <0>;
247 + mal-rx-channel = <0>;
248 + cell-index = <0>;
249 + max-frame-size = <0x5dc>;
250 + rx-fifo-size = <0x1000>;
251 + tx-fifo-size = <0x800>;
252 + phy-mode = "mii";
253 + phy-map = <0x00000000>;
254 + };
255 +
256 + leds {
257 + compatible = "gpio-leds";
258 + user {
259 + label = "openrb:green:user";
260 + gpios = <&GPIO0 2 1>;
261 + };
262 + };
263 + };
264 +
265 + EBC0: ebc {
266 + compatible = "ibm,ebc-405ep", "ibm,ebc";
267 + dcr-reg = <0x012 0x002>;
268 + #address-cells = <2>;
269 + #size-cells = <1>;
270 + /* The ranges property is supplied by the bootwrapper
271 + * and is based on the firmware's configuration of the
272 + * EBC bridge
273 + */
274 + clock-frequency = <0>; /* Filled in by zImage */
275 +
276 + nor_flash@ff800000 {
277 + compatible = "cfi-flash";
278 + bank-width = <2>;
279 + reg = <0x00000000 0xff800000 0x00800000>;
280 + #address-cells = <1>;
281 + #size-cells = <1>;
282 + partition@0 {
283 + label = "linux";
284 + reg = <0x0 0x120000>;
285 + };
286 + partition@120000 {
287 + label = "rootfs";
288 + reg = <0x120000 0x6a0000>;
289 + };
290 + partition@7c0000 {
291 + label = "u-boot";
292 + reg = <0x7c0000 0x30000>;
293 + read-only;
294 + };
295 + };
296 + };
297 +
298 + PCI0: pci@ec000000 {
299 + device_type = "pci";
300 + #interrupt-cells = <1>;
301 + #size-cells = <2>;
302 + #address-cells = <3>;
303 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
304 + primary;
305 + reg = <0xeec00000 0x00000008 /* Config space access */
306 + 0xeed80000 0x00000004 /* IACK */
307 + 0xeed80000 0x00000004 /* Special cycle */
308 + 0xef480000 0x00000040>; /* Internal registers */
309 +
310 + /* Outbound ranges, one memory and one IO,
311 + * later cannot be changed. Chip supports a second
312 + * IO range but we don't use it for now
313 + */
314 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
315 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
316 +
317 + /* Inbound 2GB range starting at 0 */
318 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
319 +
320 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
321 + interrupt-map = <
322 + /* IDSEL 1 */
323 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
324 +
325 + /* IDSEL 2 */
326 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
327 +
328 + /* IDSEL 3 */
329 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
330 +
331 + /* IDSEL 4 */
332 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
333 + >;
334 + };
335 + };
336 +
337 + chosen {
338 + linux,stdout-path = "/plb/opb/serial@ef600300";
339 + };
340 +};
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