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ipq807x: rename target to qualcommax
[openwrt/openwrt.git] / target / linux / qualcommax / patches-6.1 / 0007-v6.2-clk-qcom-ipq8074-convert-to-parent-data.patch
1 From e6c5115d6845f25eda7e162dcd783a2044215867 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Sun, 30 Oct 2022 18:57:01 +0100
4 Subject: [PATCH] clk: qcom: ipq8074: convert to parent data
5
6 Convert the IPQ8074 GCC driver to use parent data instead of global
7 name matching.
8
9 Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
10
11 Signed-off-by: Robert Marko <robimarko@gmail.com>
12 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
13 Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
14 ---
15 drivers/clk/qcom/gcc-ipq8074.c | 1781 +++++++++++++++-----------------
16 1 file changed, 813 insertions(+), 968 deletions(-)
17
18 --- a/drivers/clk/qcom/gcc-ipq8074.c
19 +++ b/drivers/clk/qcom/gcc-ipq8074.c
20 @@ -49,349 +49,6 @@ enum {
21 P_UNIPHY2_TX,
22 };
23
24 -static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
25 - "xo",
26 - "gpll0",
27 - "gpll0_out_main_div2",
28 -};
29 -
30 -static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
31 - { P_XO, 0 },
32 - { P_GPLL0, 1 },
33 - { P_GPLL0_DIV2, 4 },
34 -};
35 -
36 -static const struct parent_map gcc_xo_gpll0_map[] = {
37 - { P_XO, 0 },
38 - { P_GPLL0, 1 },
39 -};
40 -
41 -static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
42 - "xo",
43 - "gpll0",
44 - "gpll2",
45 - "gpll0_out_main_div2",
46 -};
47 -
48 -static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
49 - { P_XO, 0 },
50 - { P_GPLL0, 1 },
51 - { P_GPLL2, 2 },
52 - { P_GPLL0_DIV2, 4 },
53 -};
54 -
55 -static const char * const gcc_xo_gpll0_sleep_clk[] = {
56 - "xo",
57 - "gpll0",
58 - "sleep_clk",
59 -};
60 -
61 -static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
62 - { P_XO, 0 },
63 - { P_GPLL0, 2 },
64 - { P_SLEEP_CLK, 6 },
65 -};
66 -
67 -static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
68 - "xo",
69 - "gpll6",
70 - "gpll0",
71 - "gpll0_out_main_div2",
72 -};
73 -
74 -static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
75 - { P_XO, 0 },
76 - { P_GPLL6, 1 },
77 - { P_GPLL0, 3 },
78 - { P_GPLL0_DIV2, 4 },
79 -};
80 -
81 -static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
82 - "xo",
83 - "gpll0_out_main_div2",
84 - "gpll0",
85 -};
86 -
87 -static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
88 - { P_XO, 0 },
89 - { P_GPLL0_DIV2, 2 },
90 - { P_GPLL0, 1 },
91 -};
92 -
93 -static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
94 - "usb3phy_0_cc_pipe_clk",
95 - "xo",
96 -};
97 -
98 -static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
99 - { P_USB3PHY_0_PIPE, 0 },
100 - { P_XO, 2 },
101 -};
102 -
103 -static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
104 - "usb3phy_1_cc_pipe_clk",
105 - "xo",
106 -};
107 -
108 -static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
109 - { P_USB3PHY_1_PIPE, 0 },
110 - { P_XO, 2 },
111 -};
112 -
113 -static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
114 - "pcie20_phy0_pipe_clk",
115 - "xo",
116 -};
117 -
118 -static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
119 - { P_PCIE20_PHY0_PIPE, 0 },
120 - { P_XO, 2 },
121 -};
122 -
123 -static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
124 - "pcie20_phy1_pipe_clk",
125 - "xo",
126 -};
127 -
128 -static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
129 - { P_PCIE20_PHY1_PIPE, 0 },
130 - { P_XO, 2 },
131 -};
132 -
133 -static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
134 - "xo",
135 - "gpll0",
136 - "gpll6",
137 - "gpll0_out_main_div2",
138 -};
139 -
140 -static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
141 - { P_XO, 0 },
142 - { P_GPLL0, 1 },
143 - { P_GPLL6, 2 },
144 - { P_GPLL0_DIV2, 4 },
145 -};
146 -
147 -static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
148 - "xo",
149 - "gpll0",
150 - "gpll6",
151 - "gpll0_out_main_div2",
152 -};
153 -
154 -static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
155 - { P_XO, 0 },
156 - { P_GPLL0, 1 },
157 - { P_GPLL6, 2 },
158 - { P_GPLL0_DIV2, 3 },
159 -};
160 -
161 -static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
162 - "xo",
163 - "bias_pll_nss_noc_clk",
164 - "gpll0",
165 - "gpll2",
166 -};
167 -
168 -static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
169 - { P_XO, 0 },
170 - { P_BIAS_PLL_NSS_NOC, 1 },
171 - { P_GPLL0, 2 },
172 - { P_GPLL2, 3 },
173 -};
174 -
175 -static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
176 - "xo",
177 - "nss_crypto_pll",
178 - "gpll0",
179 -};
180 -
181 -static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
182 - { P_XO, 0 },
183 - { P_NSS_CRYPTO_PLL, 1 },
184 - { P_GPLL0, 2 },
185 -};
186 -
187 -static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
188 - "xo",
189 - "ubi32_pll",
190 - "gpll0",
191 - "gpll2",
192 - "gpll4",
193 - "gpll6",
194 -};
195 -
196 -static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
197 - { P_XO, 0 },
198 - { P_UBI32_PLL, 1 },
199 - { P_GPLL0, 2 },
200 - { P_GPLL2, 3 },
201 - { P_GPLL4, 4 },
202 - { P_GPLL6, 5 },
203 -};
204 -
205 -static const char * const gcc_xo_gpll0_out_main_div2[] = {
206 - "xo",
207 - "gpll0_out_main_div2",
208 -};
209 -
210 -static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
211 - { P_XO, 0 },
212 - { P_GPLL0_DIV2, 1 },
213 -};
214 -
215 -static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
216 - "xo",
217 - "bias_pll_cc_clk",
218 - "gpll0",
219 - "gpll4",
220 - "nss_crypto_pll",
221 - "ubi32_pll",
222 -};
223 -
224 -static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
225 - { P_XO, 0 },
226 - { P_BIAS_PLL, 1 },
227 - { P_GPLL0, 2 },
228 - { P_GPLL4, 3 },
229 - { P_NSS_CRYPTO_PLL, 4 },
230 - { P_UBI32_PLL, 5 },
231 -};
232 -
233 -static const char * const gcc_xo_gpll0_gpll4[] = {
234 - "xo",
235 - "gpll0",
236 - "gpll4",
237 -};
238 -
239 -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
240 - { P_XO, 0 },
241 - { P_GPLL0, 1 },
242 - { P_GPLL4, 2 },
243 -};
244 -
245 -static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
246 - "xo",
247 - "uniphy0_gcc_rx_clk",
248 - "uniphy0_gcc_tx_clk",
249 - "ubi32_pll",
250 - "bias_pll_cc_clk",
251 -};
252 -
253 -static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
254 - { P_XO, 0 },
255 - { P_UNIPHY0_RX, 1 },
256 - { P_UNIPHY0_TX, 2 },
257 - { P_UBI32_PLL, 5 },
258 - { P_BIAS_PLL, 6 },
259 -};
260 -
261 -static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
262 - "xo",
263 - "uniphy0_gcc_tx_clk",
264 - "uniphy0_gcc_rx_clk",
265 - "ubi32_pll",
266 - "bias_pll_cc_clk",
267 -};
268 -
269 -static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
270 - { P_XO, 0 },
271 - { P_UNIPHY0_TX, 1 },
272 - { P_UNIPHY0_RX, 2 },
273 - { P_UBI32_PLL, 5 },
274 - { P_BIAS_PLL, 6 },
275 -};
276 -
277 -static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
278 - "xo",
279 - "uniphy0_gcc_rx_clk",
280 - "uniphy0_gcc_tx_clk",
281 - "uniphy1_gcc_rx_clk",
282 - "uniphy1_gcc_tx_clk",
283 - "ubi32_pll",
284 - "bias_pll_cc_clk",
285 -};
286 -
287 -static const struct parent_map
288 -gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
289 - { P_XO, 0 },
290 - { P_UNIPHY0_RX, 1 },
291 - { P_UNIPHY0_TX, 2 },
292 - { P_UNIPHY1_RX, 3 },
293 - { P_UNIPHY1_TX, 4 },
294 - { P_UBI32_PLL, 5 },
295 - { P_BIAS_PLL, 6 },
296 -};
297 -
298 -static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
299 - "xo",
300 - "uniphy0_gcc_tx_clk",
301 - "uniphy0_gcc_rx_clk",
302 - "uniphy1_gcc_tx_clk",
303 - "uniphy1_gcc_rx_clk",
304 - "ubi32_pll",
305 - "bias_pll_cc_clk",
306 -};
307 -
308 -static const struct parent_map
309 -gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
310 - { P_XO, 0 },
311 - { P_UNIPHY0_TX, 1 },
312 - { P_UNIPHY0_RX, 2 },
313 - { P_UNIPHY1_TX, 3 },
314 - { P_UNIPHY1_RX, 4 },
315 - { P_UBI32_PLL, 5 },
316 - { P_BIAS_PLL, 6 },
317 -};
318 -
319 -static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
320 - "xo",
321 - "uniphy2_gcc_rx_clk",
322 - "uniphy2_gcc_tx_clk",
323 - "ubi32_pll",
324 - "bias_pll_cc_clk",
325 -};
326 -
327 -static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
328 - { P_XO, 0 },
329 - { P_UNIPHY2_RX, 1 },
330 - { P_UNIPHY2_TX, 2 },
331 - { P_UBI32_PLL, 5 },
332 - { P_BIAS_PLL, 6 },
333 -};
334 -
335 -static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
336 - "xo",
337 - "uniphy2_gcc_tx_clk",
338 - "uniphy2_gcc_rx_clk",
339 - "ubi32_pll",
340 - "bias_pll_cc_clk",
341 -};
342 -
343 -static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
344 - { P_XO, 0 },
345 - { P_UNIPHY2_TX, 1 },
346 - { P_UNIPHY2_RX, 2 },
347 - { P_UBI32_PLL, 5 },
348 - { P_BIAS_PLL, 6 },
349 -};
350 -
351 -static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
352 - "xo",
353 - "gpll0",
354 - "gpll6",
355 - "gpll0_out_main_div2",
356 - "sleep_clk",
357 -};
358 -
359 -static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
360 - { P_XO, 0 },
361 - { P_GPLL0, 1 },
362 - { P_GPLL6, 2 },
363 - { P_GPLL0_DIV2, 4 },
364 - { P_SLEEP_CLK, 6 },
365 -};
366 -
367 static struct clk_alpha_pll gpll0_main = {
368 .offset = 0x21000,
369 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
370 @@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main =
371 .enable_mask = BIT(0),
372 .hw.init = &(struct clk_init_data){
373 .name = "gpll0_main",
374 - .parent_names = (const char *[]){
375 - "xo"
376 + .parent_data = &(const struct clk_parent_data){
377 + .fw_name = "xo",
378 + .name = "xo",
379 },
380 .num_parents = 1,
381 .ops = &clk_alpha_pll_ops,
382 @@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out
383 .div = 2,
384 .hw.init = &(struct clk_init_data){
385 .name = "gpll0_out_main_div2",
386 - .parent_names = (const char *[]){
387 - "gpll0_main"
388 - },
389 + .parent_hws = (const struct clk_hw *[]){
390 + &gpll0_main.clkr.hw },
391 .num_parents = 1,
392 .ops = &clk_fixed_factor_ops,
393 .flags = CLK_SET_RATE_PARENT,
394 @@ -429,9 +86,8 @@ static struct clk_alpha_pll_postdiv gpll
395 .width = 4,
396 .clkr.hw.init = &(struct clk_init_data){
397 .name = "gpll0",
398 - .parent_names = (const char *[]){
399 - "gpll0_main"
400 - },
401 + .parent_hws = (const struct clk_hw *[]){
402 + &gpll0_main.clkr.hw },
403 .num_parents = 1,
404 .ops = &clk_alpha_pll_postdiv_ro_ops,
405 },
406 @@ -445,8 +101,9 @@ static struct clk_alpha_pll gpll2_main =
407 .enable_mask = BIT(2),
408 .hw.init = &(struct clk_init_data){
409 .name = "gpll2_main",
410 - .parent_names = (const char *[]){
411 - "xo"
412 + .parent_data = &(const struct clk_parent_data){
413 + .fw_name = "xo",
414 + .name = "xo",
415 },
416 .num_parents = 1,
417 .ops = &clk_alpha_pll_ops,
418 @@ -461,9 +118,8 @@ static struct clk_alpha_pll_postdiv gpll
419 .width = 4,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "gpll2",
422 - .parent_names = (const char *[]){
423 - "gpll2_main"
424 - },
425 + .parent_hws = (const struct clk_hw *[]){
426 + &gpll2_main.clkr.hw },
427 .num_parents = 1,
428 .ops = &clk_alpha_pll_postdiv_ro_ops,
429 .flags = CLK_SET_RATE_PARENT,
430 @@ -478,8 +134,9 @@ static struct clk_alpha_pll gpll4_main =
431 .enable_mask = BIT(5),
432 .hw.init = &(struct clk_init_data){
433 .name = "gpll4_main",
434 - .parent_names = (const char *[]){
435 - "xo"
436 + .parent_data = &(const struct clk_parent_data){
437 + .fw_name = "xo",
438 + .name = "xo",
439 },
440 .num_parents = 1,
441 .ops = &clk_alpha_pll_ops,
442 @@ -494,9 +151,8 @@ static struct clk_alpha_pll_postdiv gpll
443 .width = 4,
444 .clkr.hw.init = &(struct clk_init_data){
445 .name = "gpll4",
446 - .parent_names = (const char *[]){
447 - "gpll4_main"
448 - },
449 + .parent_hws = (const struct clk_hw *[]){
450 + &gpll4_main.clkr.hw },
451 .num_parents = 1,
452 .ops = &clk_alpha_pll_postdiv_ro_ops,
453 .flags = CLK_SET_RATE_PARENT,
454 @@ -512,8 +168,9 @@ static struct clk_alpha_pll gpll6_main =
455 .enable_mask = BIT(7),
456 .hw.init = &(struct clk_init_data){
457 .name = "gpll6_main",
458 - .parent_names = (const char *[]){
459 - "xo"
460 + .parent_data = &(const struct clk_parent_data){
461 + .fw_name = "xo",
462 + .name = "xo",
463 },
464 .num_parents = 1,
465 .ops = &clk_alpha_pll_ops,
466 @@ -528,9 +185,8 @@ static struct clk_alpha_pll_postdiv gpll
467 .width = 2,
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "gpll6",
470 - .parent_names = (const char *[]){
471 - "gpll6_main"
472 - },
473 + .parent_hws = (const struct clk_hw *[]){
474 + &gpll6_main.clkr.hw },
475 .num_parents = 1,
476 .ops = &clk_alpha_pll_postdiv_ro_ops,
477 .flags = CLK_SET_RATE_PARENT,
478 @@ -542,9 +198,8 @@ static struct clk_fixed_factor gpll6_out
479 .div = 2,
480 .hw.init = &(struct clk_init_data){
481 .name = "gpll6_out_main_div2",
482 - .parent_names = (const char *[]){
483 - "gpll6_main"
484 - },
485 + .parent_hws = (const struct clk_hw *[]){
486 + &gpll6_main.clkr.hw },
487 .num_parents = 1,
488 .ops = &clk_fixed_factor_ops,
489 .flags = CLK_SET_RATE_PARENT,
490 @@ -560,8 +215,9 @@ static struct clk_alpha_pll ubi32_pll_ma
491 .enable_mask = BIT(6),
492 .hw.init = &(struct clk_init_data){
493 .name = "ubi32_pll_main",
494 - .parent_names = (const char *[]){
495 - "xo"
496 + .parent_data = &(const struct clk_parent_data){
497 + .fw_name = "xo",
498 + .name = "xo",
499 },
500 .num_parents = 1,
501 .ops = &clk_alpha_pll_huayra_ops,
502 @@ -575,9 +231,8 @@ static struct clk_alpha_pll_postdiv ubi3
503 .width = 2,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "ubi32_pll",
506 - .parent_names = (const char *[]){
507 - "ubi32_pll_main"
508 - },
509 + .parent_hws = (const struct clk_hw *[]){
510 + &ubi32_pll_main.clkr.hw },
511 .num_parents = 1,
512 .ops = &clk_alpha_pll_postdiv_ro_ops,
513 .flags = CLK_SET_RATE_PARENT,
514 @@ -592,8 +247,9 @@ static struct clk_alpha_pll nss_crypto_p
515 .enable_mask = BIT(4),
516 .hw.init = &(struct clk_init_data){
517 .name = "nss_crypto_pll_main",
518 - .parent_names = (const char *[]){
519 - "xo"
520 + .parent_data = &(const struct clk_parent_data){
521 + .fw_name = "xo",
522 + .name = "xo",
523 },
524 .num_parents = 1,
525 .ops = &clk_alpha_pll_ops,
526 @@ -607,9 +263,8 @@ static struct clk_alpha_pll_postdiv nss_
527 .width = 4,
528 .clkr.hw.init = &(struct clk_init_data){
529 .name = "nss_crypto_pll",
530 - .parent_names = (const char *[]){
531 - "nss_crypto_pll_main"
532 - },
533 + .parent_hws = (const struct clk_hw *[]){
534 + &nss_crypto_pll_main.clkr.hw },
535 .num_parents = 1,
536 .ops = &clk_alpha_pll_postdiv_ro_ops,
537 .flags = CLK_SET_RATE_PARENT,
538 @@ -623,6 +278,18 @@ static const struct freq_tbl ftbl_pcnoc_
539 { }
540 };
541
542 +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
543 + { .fw_name = "xo", .name = "xo" },
544 + { .hw = &gpll0.clkr.hw},
545 + { .hw = &gpll0_out_main_div2.hw},
546 +};
547 +
548 +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
549 + { P_XO, 0 },
550 + { P_GPLL0, 1 },
551 + { P_GPLL0_DIV2, 4 },
552 +};
553 +
554 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
555 .cmd_rcgr = 0x27000,
556 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
557 @@ -630,8 +297,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
558 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "pcnoc_bfdcd_clk_src",
561 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
562 - .num_parents = 3,
563 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
564 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
565 .ops = &clk_rcg2_ops,
566 .flags = CLK_IS_CRITICAL,
567 },
568 @@ -642,9 +309,8 @@ static struct clk_fixed_factor pcnoc_clk
569 .div = 1,
570 .hw.init = &(struct clk_init_data){
571 .name = "pcnoc_clk_src",
572 - .parent_names = (const char *[]){
573 - "pcnoc_bfdcd_clk_src"
574 - },
575 + .parent_hws = (const struct clk_hw *[]){
576 + &pcnoc_bfdcd_clk_src.clkr.hw },
577 .num_parents = 1,
578 .ops = &clk_fixed_factor_ops,
579 .flags = CLK_SET_RATE_PARENT,
580 @@ -658,8 +324,9 @@ static struct clk_branch gcc_sleep_clk_s
581 .enable_mask = BIT(1),
582 .hw.init = &(struct clk_init_data){
583 .name = "gcc_sleep_clk_src",
584 - .parent_names = (const char *[]){
585 - "sleep_clk"
586 + .parent_data = &(const struct clk_parent_data){
587 + .fw_name = "sleep_clk",
588 + .name = "sleep_clk",
589 },
590 .num_parents = 1,
591 .ops = &clk_branch2_ops,
592 @@ -682,8 +349,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
593 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "blsp1_qup1_i2c_apps_clk_src",
596 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
597 - .num_parents = 3,
598 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
599 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
600 .ops = &clk_rcg2_ops,
601 },
602 };
603 @@ -708,8 +375,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
604 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
605 .clkr.hw.init = &(struct clk_init_data){
606 .name = "blsp1_qup1_spi_apps_clk_src",
607 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
608 - .num_parents = 3,
609 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
610 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
611 .ops = &clk_rcg2_ops,
612 },
613 };
614 @@ -721,8 +388,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
615 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
616 .clkr.hw.init = &(struct clk_init_data){
617 .name = "blsp1_qup2_i2c_apps_clk_src",
618 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
619 - .num_parents = 3,
620 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
621 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
622 .ops = &clk_rcg2_ops,
623 },
624 };
625 @@ -735,8 +402,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
626 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
627 .clkr.hw.init = &(struct clk_init_data){
628 .name = "blsp1_qup2_spi_apps_clk_src",
629 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
630 - .num_parents = 3,
631 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
632 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
633 .ops = &clk_rcg2_ops,
634 },
635 };
636 @@ -748,8 +415,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
637 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "blsp1_qup3_i2c_apps_clk_src",
640 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
641 - .num_parents = 3,
642 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
643 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
644 .ops = &clk_rcg2_ops,
645 },
646 };
647 @@ -762,8 +429,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
648 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "blsp1_qup3_spi_apps_clk_src",
651 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
652 - .num_parents = 3,
653 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
654 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
655 .ops = &clk_rcg2_ops,
656 },
657 };
658 @@ -775,8 +442,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
659 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "blsp1_qup4_i2c_apps_clk_src",
662 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
663 - .num_parents = 3,
664 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
665 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
666 .ops = &clk_rcg2_ops,
667 },
668 };
669 @@ -789,8 +456,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
670 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "blsp1_qup4_spi_apps_clk_src",
673 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
674 - .num_parents = 3,
675 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
676 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
677 .ops = &clk_rcg2_ops,
678 },
679 };
680 @@ -802,8 +469,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
681 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
682 .clkr.hw.init = &(struct clk_init_data){
683 .name = "blsp1_qup5_i2c_apps_clk_src",
684 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
685 - .num_parents = 3,
686 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
687 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
688 .ops = &clk_rcg2_ops,
689 },
690 };
691 @@ -816,8 +483,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
692 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
693 .clkr.hw.init = &(struct clk_init_data){
694 .name = "blsp1_qup5_spi_apps_clk_src",
695 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
696 - .num_parents = 3,
697 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
698 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
699 .ops = &clk_rcg2_ops,
700 },
701 };
702 @@ -829,8 +496,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
703 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
704 .clkr.hw.init = &(struct clk_init_data){
705 .name = "blsp1_qup6_i2c_apps_clk_src",
706 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
707 - .num_parents = 3,
708 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
709 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
710 .ops = &clk_rcg2_ops,
711 },
712 };
713 @@ -843,8 +510,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
714 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "blsp1_qup6_spi_apps_clk_src",
717 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
718 - .num_parents = 3,
719 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
720 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
721 .ops = &clk_rcg2_ops,
722 },
723 };
724 @@ -877,8 +544,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
725 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
726 .clkr.hw.init = &(struct clk_init_data){
727 .name = "blsp1_uart1_apps_clk_src",
728 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
729 - .num_parents = 3,
730 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
731 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
732 .ops = &clk_rcg2_ops,
733 },
734 };
735 @@ -891,8 +558,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
736 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "blsp1_uart2_apps_clk_src",
739 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
740 - .num_parents = 3,
741 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
742 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
743 .ops = &clk_rcg2_ops,
744 },
745 };
746 @@ -905,8 +572,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
747 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
748 .clkr.hw.init = &(struct clk_init_data){
749 .name = "blsp1_uart3_apps_clk_src",
750 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
751 - .num_parents = 3,
752 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
753 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
754 .ops = &clk_rcg2_ops,
755 },
756 };
757 @@ -919,8 +586,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
758 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
759 .clkr.hw.init = &(struct clk_init_data){
760 .name = "blsp1_uart4_apps_clk_src",
761 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
762 - .num_parents = 3,
763 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
764 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
765 .ops = &clk_rcg2_ops,
766 },
767 };
768 @@ -933,8 +600,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
769 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "blsp1_uart5_apps_clk_src",
772 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
773 - .num_parents = 3,
774 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
775 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
776 .ops = &clk_rcg2_ops,
777 },
778 };
779 @@ -947,8 +614,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
780 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
781 .clkr.hw.init = &(struct clk_init_data){
782 .name = "blsp1_uart6_apps_clk_src",
783 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
784 - .num_parents = 3,
785 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
786 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
787 .ops = &clk_rcg2_ops,
788 },
789 };
790 @@ -958,6 +625,11 @@ static const struct clk_parent_data gcc_
791 { .hw = &gpll0.clkr.hw },
792 };
793
794 +static const struct parent_map gcc_xo_gpll0_map[] = {
795 + { P_XO, 0 },
796 + { P_GPLL0, 1 },
797 +};
798 +
799 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
800 F(19200000, P_XO, 1, 0, 0),
801 F(200000000, P_GPLL0, 4, 0, 0),
802 @@ -972,7 +644,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
803 .clkr.hw.init = &(struct clk_init_data){
804 .name = "pcie0_axi_clk_src",
805 .parent_data = gcc_xo_gpll0,
806 - .num_parents = 2,
807 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
808 .ops = &clk_rcg2_ops,
809 },
810 };
811 @@ -981,6 +653,18 @@ static const struct freq_tbl ftbl_pcie_a
812 F(19200000, P_XO, 1, 0, 0),
813 };
814
815 +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
816 + { .fw_name = "xo", .name = "xo" },
817 + { .hw = &gpll0.clkr.hw },
818 + { .fw_name = "sleep_clk", .name = "sleep_clk" },
819 +};
820 +
821 +static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
822 + { P_XO, 0 },
823 + { P_GPLL0, 2 },
824 + { P_SLEEP_CLK, 6 },
825 +};
826 +
827 static struct clk_rcg2 pcie0_aux_clk_src = {
828 .cmd_rcgr = 0x75024,
829 .freq_tbl = ftbl_pcie_aux_clk_src,
830 @@ -989,12 +673,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
831 .parent_map = gcc_xo_gpll0_sleep_clk_map,
832 .clkr.hw.init = &(struct clk_init_data){
833 .name = "pcie0_aux_clk_src",
834 - .parent_names = gcc_xo_gpll0_sleep_clk,
835 - .num_parents = 3,
836 + .parent_data = gcc_xo_gpll0_sleep_clk,
837 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
838 .ops = &clk_rcg2_ops,
839 },
840 };
841
842 +static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
843 + { .name = "pcie20_phy0_pipe_clk" },
844 + { .fw_name = "xo", .name = "xo" },
845 +};
846 +
847 +static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
848 + { P_PCIE20_PHY0_PIPE, 0 },
849 + { P_XO, 2 },
850 +};
851 +
852 static struct clk_regmap_mux pcie0_pipe_clk_src = {
853 .reg = 0x7501c,
854 .shift = 8,
855 @@ -1003,8 +697,8 @@ static struct clk_regmap_mux pcie0_pipe_
856 .clkr = {
857 .hw.init = &(struct clk_init_data){
858 .name = "pcie0_pipe_clk_src",
859 - .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
860 - .num_parents = 2,
861 + .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
862 + .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
863 .ops = &clk_regmap_mux_closest_ops,
864 .flags = CLK_SET_RATE_PARENT,
865 },
866 @@ -1019,7 +713,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
867 .clkr.hw.init = &(struct clk_init_data){
868 .name = "pcie1_axi_clk_src",
869 .parent_data = gcc_xo_gpll0,
870 - .num_parents = 2,
871 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
872 .ops = &clk_rcg2_ops,
873 },
874 };
875 @@ -1032,12 +726,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
876 .parent_map = gcc_xo_gpll0_sleep_clk_map,
877 .clkr.hw.init = &(struct clk_init_data){
878 .name = "pcie1_aux_clk_src",
879 - .parent_names = gcc_xo_gpll0_sleep_clk,
880 - .num_parents = 3,
881 + .parent_data = gcc_xo_gpll0_sleep_clk,
882 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
883 .ops = &clk_rcg2_ops,
884 },
885 };
886
887 +static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
888 + { .name = "pcie20_phy1_pipe_clk" },
889 + { .fw_name = "xo", .name = "xo" },
890 +};
891 +
892 +static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
893 + { P_PCIE20_PHY1_PIPE, 0 },
894 + { P_XO, 2 },
895 +};
896 +
897 static struct clk_regmap_mux pcie1_pipe_clk_src = {
898 .reg = 0x7601c,
899 .shift = 8,
900 @@ -1046,8 +750,8 @@ static struct clk_regmap_mux pcie1_pipe_
901 .clkr = {
902 .hw.init = &(struct clk_init_data){
903 .name = "pcie1_pipe_clk_src",
904 - .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
905 - .num_parents = 2,
906 + .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
907 + .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
908 .ops = &clk_regmap_mux_closest_ops,
909 .flags = CLK_SET_RATE_PARENT,
910 },
911 @@ -1066,6 +770,20 @@ static const struct freq_tbl ftbl_sdcc_a
912 { }
913 };
914
915 +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
916 + { .fw_name = "xo", .name = "xo" },
917 + { .hw = &gpll0.clkr.hw },
918 + { .hw = &gpll2.clkr.hw },
919 + { .hw = &gpll0_out_main_div2.hw },
920 +};
921 +
922 +static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
923 + { P_XO, 0 },
924 + { P_GPLL0, 1 },
925 + { P_GPLL2, 2 },
926 + { P_GPLL0_DIV2, 4 },
927 +};
928 +
929 static struct clk_rcg2 sdcc1_apps_clk_src = {
930 .cmd_rcgr = 0x42004,
931 .freq_tbl = ftbl_sdcc_apps_clk_src,
932 @@ -1074,8 +792,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
933 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "sdcc1_apps_clk_src",
936 - .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
937 - .num_parents = 4,
938 + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
939 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
940 .ops = &clk_rcg2_floor_ops,
941 },
942 };
943 @@ -1086,6 +804,20 @@ static const struct freq_tbl ftbl_sdcc_i
944 F(308570000, P_GPLL6, 3.5, 0, 0),
945 };
946
947 +static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
948 + { .fw_name = "xo", .name = "xo" },
949 + { .hw = &gpll0.clkr.hw },
950 + { .hw = &gpll6.clkr.hw },
951 + { .hw = &gpll0_out_main_div2.hw },
952 +};
953 +
954 +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
955 + { P_XO, 0 },
956 + { P_GPLL0, 1 },
957 + { P_GPLL6, 2 },
958 + { P_GPLL0_DIV2, 4 },
959 +};
960 +
961 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
962 .cmd_rcgr = 0x5d000,
963 .freq_tbl = ftbl_sdcc_ice_core_clk_src,
964 @@ -1094,8 +826,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
965 .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
966 .clkr.hw.init = &(struct clk_init_data){
967 .name = "sdcc1_ice_core_clk_src",
968 - .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
969 - .num_parents = 4,
970 + .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
971 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
972 .ops = &clk_rcg2_ops,
973 },
974 };
975 @@ -1108,8 +840,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
976 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
977 .clkr.hw.init = &(struct clk_init_data){
978 .name = "sdcc2_apps_clk_src",
979 - .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
980 - .num_parents = 4,
981 + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
982 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
983 .ops = &clk_rcg2_floor_ops,
984 },
985 };
986 @@ -1121,6 +853,18 @@ static const struct freq_tbl ftbl_usb_ma
987 { }
988 };
989
990 +static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
991 + { .fw_name = "xo", .name = "xo" },
992 + { .hw = &gpll0_out_main_div2.hw },
993 + { .hw = &gpll0.clkr.hw },
994 +};
995 +
996 +static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
997 + { P_XO, 0 },
998 + { P_GPLL0_DIV2, 2 },
999 + { P_GPLL0, 1 },
1000 +};
1001 +
1002 static struct clk_rcg2 usb0_master_clk_src = {
1003 .cmd_rcgr = 0x3e00c,
1004 .freq_tbl = ftbl_usb_master_clk_src,
1005 @@ -1129,8 +873,8 @@ static struct clk_rcg2 usb0_master_clk_s
1006 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1007 .clkr.hw.init = &(struct clk_init_data){
1008 .name = "usb0_master_clk_src",
1009 - .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1010 - .num_parents = 3,
1011 + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1012 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1013 .ops = &clk_rcg2_ops,
1014 },
1015 };
1016 @@ -1148,8 +892,8 @@ static struct clk_rcg2 usb0_aux_clk_src
1017 .parent_map = gcc_xo_gpll0_sleep_clk_map,
1018 .clkr.hw.init = &(struct clk_init_data){
1019 .name = "usb0_aux_clk_src",
1020 - .parent_names = gcc_xo_gpll0_sleep_clk,
1021 - .num_parents = 3,
1022 + .parent_data = gcc_xo_gpll0_sleep_clk,
1023 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
1024 .ops = &clk_rcg2_ops,
1025 },
1026 };
1027 @@ -1161,6 +905,20 @@ static const struct freq_tbl ftbl_usb_mo
1028 { }
1029 };
1030
1031 +static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1032 + { .fw_name = "xo", .name = "xo" },
1033 + { .hw = &gpll6.clkr.hw },
1034 + { .hw = &gpll0.clkr.hw },
1035 + { .hw = &gpll0_out_main_div2.hw },
1036 +};
1037 +
1038 +static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1039 + { P_XO, 0 },
1040 + { P_GPLL6, 1 },
1041 + { P_GPLL0, 3 },
1042 + { P_GPLL0_DIV2, 4 },
1043 +};
1044 +
1045 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1046 .cmd_rcgr = 0x3e020,
1047 .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1048 @@ -1169,12 +927,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
1049 .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1050 .clkr.hw.init = &(struct clk_init_data){
1051 .name = "usb0_mock_utmi_clk_src",
1052 - .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1053 - .num_parents = 4,
1054 + .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1055 + .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
1056 .ops = &clk_rcg2_ops,
1057 },
1058 };
1059
1060 +static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1061 + { .name = "usb3phy_0_cc_pipe_clk" },
1062 + { .fw_name = "xo", .name = "xo" },
1063 +};
1064 +
1065 +static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1066 + { P_USB3PHY_0_PIPE, 0 },
1067 + { P_XO, 2 },
1068 +};
1069 +
1070 static struct clk_regmap_mux usb0_pipe_clk_src = {
1071 .reg = 0x3e048,
1072 .shift = 8,
1073 @@ -1183,8 +951,8 @@ static struct clk_regmap_mux usb0_pipe_c
1074 .clkr = {
1075 .hw.init = &(struct clk_init_data){
1076 .name = "usb0_pipe_clk_src",
1077 - .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1078 - .num_parents = 2,
1079 + .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1080 + .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1081 .ops = &clk_regmap_mux_closest_ops,
1082 .flags = CLK_SET_RATE_PARENT,
1083 },
1084 @@ -1199,8 +967,8 @@ static struct clk_rcg2 usb1_master_clk_s
1085 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1086 .clkr.hw.init = &(struct clk_init_data){
1087 .name = "usb1_master_clk_src",
1088 - .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1089 - .num_parents = 3,
1090 + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1091 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1092 .ops = &clk_rcg2_ops,
1093 },
1094 };
1095 @@ -1213,8 +981,8 @@ static struct clk_rcg2 usb1_aux_clk_src
1096 .parent_map = gcc_xo_gpll0_sleep_clk_map,
1097 .clkr.hw.init = &(struct clk_init_data){
1098 .name = "usb1_aux_clk_src",
1099 - .parent_names = gcc_xo_gpll0_sleep_clk,
1100 - .num_parents = 3,
1101 + .parent_data = gcc_xo_gpll0_sleep_clk,
1102 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
1103 .ops = &clk_rcg2_ops,
1104 },
1105 };
1106 @@ -1227,12 +995,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
1107 .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1108 .clkr.hw.init = &(struct clk_init_data){
1109 .name = "usb1_mock_utmi_clk_src",
1110 - .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1111 - .num_parents = 4,
1112 + .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1113 + .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
1114 .ops = &clk_rcg2_ops,
1115 },
1116 };
1117
1118 +static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
1119 + { .name = "usb3phy_1_cc_pipe_clk" },
1120 + { .fw_name = "xo", .name = "xo" },
1121 +};
1122 +
1123 +static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
1124 + { P_USB3PHY_1_PIPE, 0 },
1125 + { P_XO, 2 },
1126 +};
1127 +
1128 static struct clk_regmap_mux usb1_pipe_clk_src = {
1129 .reg = 0x3f048,
1130 .shift = 8,
1131 @@ -1241,8 +1019,8 @@ static struct clk_regmap_mux usb1_pipe_c
1132 .clkr = {
1133 .hw.init = &(struct clk_init_data){
1134 .name = "usb1_pipe_clk_src",
1135 - .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1136 - .num_parents = 2,
1137 + .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
1138 + .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
1139 .ops = &clk_regmap_mux_closest_ops,
1140 .flags = CLK_SET_RATE_PARENT,
1141 },
1142 @@ -1256,8 +1034,9 @@ static struct clk_branch gcc_xo_clk_src
1143 .enable_mask = BIT(1),
1144 .hw.init = &(struct clk_init_data){
1145 .name = "gcc_xo_clk_src",
1146 - .parent_names = (const char *[]){
1147 - "xo"
1148 + .parent_data = &(const struct clk_parent_data){
1149 + .fw_name = "xo",
1150 + .name = "xo",
1151 },
1152 .num_parents = 1,
1153 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1154 @@ -1271,9 +1050,8 @@ static struct clk_fixed_factor gcc_xo_di
1155 .div = 4,
1156 .hw.init = &(struct clk_init_data){
1157 .name = "gcc_xo_div4_clk_src",
1158 - .parent_names = (const char *[]){
1159 - "gcc_xo_clk_src"
1160 - },
1161 + .parent_hws = (const struct clk_hw *[]){
1162 + &gcc_xo_clk_src.clkr.hw },
1163 .num_parents = 1,
1164 .ops = &clk_fixed_factor_ops,
1165 .flags = CLK_SET_RATE_PARENT,
1166 @@ -1291,6 +1069,20 @@ static const struct freq_tbl ftbl_system
1167 { }
1168 };
1169
1170 +static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
1171 + { .fw_name = "xo", .name = "xo" },
1172 + { .hw = &gpll0.clkr.hw },
1173 + { .hw = &gpll6.clkr.hw },
1174 + { .hw = &gpll0_out_main_div2.hw },
1175 +};
1176 +
1177 +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
1178 + { P_XO, 0 },
1179 + { P_GPLL0, 1 },
1180 + { P_GPLL6, 2 },
1181 + { P_GPLL0_DIV2, 3 },
1182 +};
1183 +
1184 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1185 .cmd_rcgr = 0x26004,
1186 .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1187 @@ -1298,8 +1090,8 @@ static struct clk_rcg2 system_noc_bfdcd_
1188 .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1189 .clkr.hw.init = &(struct clk_init_data){
1190 .name = "system_noc_bfdcd_clk_src",
1191 - .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1192 - .num_parents = 4,
1193 + .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1194 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
1195 .ops = &clk_rcg2_ops,
1196 .flags = CLK_IS_CRITICAL,
1197 },
1198 @@ -1310,9 +1102,8 @@ static struct clk_fixed_factor system_no
1199 .div = 1,
1200 .hw.init = &(struct clk_init_data){
1201 .name = "system_noc_clk_src",
1202 - .parent_names = (const char *[]){
1203 - "system_noc_bfdcd_clk_src"
1204 - },
1205 + .parent_hws = (const struct clk_hw *[]){
1206 + &system_noc_bfdcd_clk_src.clkr.hw },
1207 .num_parents = 1,
1208 .ops = &clk_fixed_factor_ops,
1209 .flags = CLK_SET_RATE_PARENT,
1210 @@ -1333,7 +1124,7 @@ static struct clk_rcg2 nss_ce_clk_src =
1211 .clkr.hw.init = &(struct clk_init_data){
1212 .name = "nss_ce_clk_src",
1213 .parent_data = gcc_xo_gpll0,
1214 - .num_parents = 2,
1215 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1216 .ops = &clk_rcg2_ops,
1217 },
1218 };
1219 @@ -1344,6 +1135,20 @@ static const struct freq_tbl ftbl_nss_no
1220 { }
1221 };
1222
1223 +static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
1224 + { .fw_name = "xo", .name = "xo" },
1225 + { .name = "bias_pll_nss_noc_clk" },
1226 + { .hw = &gpll0.clkr.hw },
1227 + { .hw = &gpll2.clkr.hw },
1228 +};
1229 +
1230 +static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
1231 + { P_XO, 0 },
1232 + { P_BIAS_PLL_NSS_NOC, 1 },
1233 + { P_GPLL0, 2 },
1234 + { P_GPLL2, 3 },
1235 +};
1236 +
1237 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1238 .cmd_rcgr = 0x68088,
1239 .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1240 @@ -1351,8 +1156,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
1241 .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1242 .clkr.hw.init = &(struct clk_init_data){
1243 .name = "nss_noc_bfdcd_clk_src",
1244 - .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1245 - .num_parents = 4,
1246 + .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1247 + .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
1248 .ops = &clk_rcg2_ops,
1249 },
1250 };
1251 @@ -1362,9 +1167,8 @@ static struct clk_fixed_factor nss_noc_c
1252 .div = 1,
1253 .hw.init = &(struct clk_init_data){
1254 .name = "nss_noc_clk_src",
1255 - .parent_names = (const char *[]){
1256 - "nss_noc_bfdcd_clk_src"
1257 - },
1258 + .parent_hws = (const struct clk_hw *[]){
1259 + &nss_noc_bfdcd_clk_src.clkr.hw },
1260 .num_parents = 1,
1261 .ops = &clk_fixed_factor_ops,
1262 .flags = CLK_SET_RATE_PARENT,
1263 @@ -1377,6 +1181,18 @@ static const struct freq_tbl ftbl_nss_cr
1264 { }
1265 };
1266
1267 +static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
1268 + { .fw_name = "xo", .name = "xo" },
1269 + { .hw = &nss_crypto_pll.clkr.hw },
1270 + { .hw = &gpll0.clkr.hw },
1271 +};
1272 +
1273 +static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
1274 + { P_XO, 0 },
1275 + { P_NSS_CRYPTO_PLL, 1 },
1276 + { P_GPLL0, 2 },
1277 +};
1278 +
1279 static struct clk_rcg2 nss_crypto_clk_src = {
1280 .cmd_rcgr = 0x68144,
1281 .freq_tbl = ftbl_nss_crypto_clk_src,
1282 @@ -1385,8 +1201,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
1283 .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1284 .clkr.hw.init = &(struct clk_init_data){
1285 .name = "nss_crypto_clk_src",
1286 - .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1287 - .num_parents = 3,
1288 + .parent_data = gcc_xo_nss_crypto_pll_gpll0,
1289 + .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
1290 .ops = &clk_rcg2_ops,
1291 },
1292 };
1293 @@ -1400,6 +1216,24 @@ static const struct freq_tbl ftbl_nss_ub
1294 { }
1295 };
1296
1297 +static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1298 + { .fw_name = "xo", .name = "xo" },
1299 + { .hw = &ubi32_pll.clkr.hw },
1300 + { .hw = &gpll0.clkr.hw },
1301 + { .hw = &gpll2.clkr.hw },
1302 + { .hw = &gpll4.clkr.hw },
1303 + { .hw = &gpll6.clkr.hw },
1304 +};
1305 +
1306 +static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1307 + { P_XO, 0 },
1308 + { P_UBI32_PLL, 1 },
1309 + { P_GPLL0, 2 },
1310 + { P_GPLL2, 3 },
1311 + { P_GPLL4, 4 },
1312 + { P_GPLL6, 5 },
1313 +};
1314 +
1315 static struct clk_rcg2 nss_ubi0_clk_src = {
1316 .cmd_rcgr = 0x68104,
1317 .freq_tbl = ftbl_nss_ubi_clk_src,
1318 @@ -1407,8 +1241,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
1319 .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1320 .clkr.hw.init = &(struct clk_init_data){
1321 .name = "nss_ubi0_clk_src",
1322 - .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1323 - .num_parents = 6,
1324 + .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1325 + .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1326 .ops = &clk_rcg2_ops,
1327 .flags = CLK_SET_RATE_PARENT,
1328 },
1329 @@ -1421,9 +1255,8 @@ static struct clk_regmap_div nss_ubi0_di
1330 .clkr = {
1331 .hw.init = &(struct clk_init_data){
1332 .name = "nss_ubi0_div_clk_src",
1333 - .parent_names = (const char *[]){
1334 - "nss_ubi0_clk_src"
1335 - },
1336 + .parent_hws = (const struct clk_hw *[]){
1337 + &nss_ubi0_clk_src.clkr.hw },
1338 .num_parents = 1,
1339 .ops = &clk_regmap_div_ro_ops,
1340 .flags = CLK_SET_RATE_PARENT,
1341 @@ -1438,8 +1271,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
1342 .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1343 .clkr.hw.init = &(struct clk_init_data){
1344 .name = "nss_ubi1_clk_src",
1345 - .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1346 - .num_parents = 6,
1347 + .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1348 + .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1349 .ops = &clk_rcg2_ops,
1350 .flags = CLK_SET_RATE_PARENT,
1351 },
1352 @@ -1452,9 +1285,8 @@ static struct clk_regmap_div nss_ubi1_di
1353 .clkr = {
1354 .hw.init = &(struct clk_init_data){
1355 .name = "nss_ubi1_div_clk_src",
1356 - .parent_names = (const char *[]){
1357 - "nss_ubi1_clk_src"
1358 - },
1359 + .parent_hws = (const struct clk_hw *[]){
1360 + &nss_ubi1_clk_src.clkr.hw },
1361 .num_parents = 1,
1362 .ops = &clk_regmap_div_ro_ops,
1363 .flags = CLK_SET_RATE_PARENT,
1364 @@ -1468,6 +1300,16 @@ static const struct freq_tbl ftbl_ubi_mp
1365 { }
1366 };
1367
1368 +static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
1369 + { .fw_name = "xo", .name = "xo" },
1370 + { .hw = &gpll0_out_main_div2.hw },
1371 +};
1372 +
1373 +static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
1374 + { P_XO, 0 },
1375 + { P_GPLL0_DIV2, 1 },
1376 +};
1377 +
1378 static struct clk_rcg2 ubi_mpt_clk_src = {
1379 .cmd_rcgr = 0x68090,
1380 .freq_tbl = ftbl_ubi_mpt_clk_src,
1381 @@ -1475,8 +1317,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
1382 .parent_map = gcc_xo_gpll0_out_main_div2_map,
1383 .clkr.hw.init = &(struct clk_init_data){
1384 .name = "ubi_mpt_clk_src",
1385 - .parent_names = gcc_xo_gpll0_out_main_div2,
1386 - .num_parents = 2,
1387 + .parent_data = gcc_xo_gpll0_out_main_div2,
1388 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
1389 .ops = &clk_rcg2_ops,
1390 },
1391 };
1392 @@ -1487,6 +1329,18 @@ static const struct freq_tbl ftbl_nss_im
1393 { }
1394 };
1395
1396 +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
1397 + { .fw_name = "xo", .name = "xo" },
1398 + { .hw = &gpll0.clkr.hw },
1399 + { .hw = &gpll4.clkr.hw },
1400 +};
1401 +
1402 +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
1403 + { P_XO, 0 },
1404 + { P_GPLL0, 1 },
1405 + { P_GPLL4, 2 },
1406 +};
1407 +
1408 static struct clk_rcg2 nss_imem_clk_src = {
1409 .cmd_rcgr = 0x68158,
1410 .freq_tbl = ftbl_nss_imem_clk_src,
1411 @@ -1494,8 +1348,8 @@ static struct clk_rcg2 nss_imem_clk_src
1412 .parent_map = gcc_xo_gpll0_gpll4_map,
1413 .clkr.hw.init = &(struct clk_init_data){
1414 .name = "nss_imem_clk_src",
1415 - .parent_names = gcc_xo_gpll0_gpll4,
1416 - .num_parents = 3,
1417 + .parent_data = gcc_xo_gpll0_gpll4,
1418 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1419 .ops = &clk_rcg2_ops,
1420 },
1421 };
1422 @@ -1506,6 +1360,24 @@ static const struct freq_tbl ftbl_nss_pp
1423 { }
1424 };
1425
1426 +static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
1427 + { .fw_name = "xo", .name = "xo" },
1428 + { .name = "bias_pll_cc_clk" },
1429 + { .hw = &gpll0.clkr.hw },
1430 + { .hw = &gpll4.clkr.hw },
1431 + { .hw = &nss_crypto_pll.clkr.hw },
1432 + { .hw = &ubi32_pll.clkr.hw },
1433 +};
1434 +
1435 +static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
1436 + { P_XO, 0 },
1437 + { P_BIAS_PLL, 1 },
1438 + { P_GPLL0, 2 },
1439 + { P_GPLL4, 3 },
1440 + { P_NSS_CRYPTO_PLL, 4 },
1441 + { P_UBI32_PLL, 5 },
1442 +};
1443 +
1444 static struct clk_rcg2 nss_ppe_clk_src = {
1445 .cmd_rcgr = 0x68080,
1446 .freq_tbl = ftbl_nss_ppe_clk_src,
1447 @@ -1513,8 +1385,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
1448 .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1449 .clkr.hw.init = &(struct clk_init_data){
1450 .name = "nss_ppe_clk_src",
1451 - .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1452 - .num_parents = 6,
1453 + .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1454 + .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
1455 .ops = &clk_rcg2_ops,
1456 },
1457 };
1458 @@ -1524,9 +1396,8 @@ static struct clk_fixed_factor nss_ppe_c
1459 .div = 4,
1460 .hw.init = &(struct clk_init_data){
1461 .name = "nss_ppe_cdiv_clk_src",
1462 - .parent_names = (const char *[]){
1463 - "nss_ppe_clk_src"
1464 - },
1465 + .parent_hws = (const struct clk_hw *[]){
1466 + &nss_ppe_clk_src.clkr.hw },
1467 .num_parents = 1,
1468 .ops = &clk_fixed_factor_ops,
1469 .flags = CLK_SET_RATE_PARENT,
1470 @@ -1540,6 +1411,22 @@ static const struct freq_tbl ftbl_nss_po
1471 { }
1472 };
1473
1474 +static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
1475 + { .fw_name = "xo", .name = "xo" },
1476 + { .name = "uniphy0_gcc_rx_clk" },
1477 + { .name = "uniphy0_gcc_tx_clk" },
1478 + { .hw = &ubi32_pll.clkr.hw },
1479 + { .name = "bias_pll_cc_clk" },
1480 +};
1481 +
1482 +static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
1483 + { P_XO, 0 },
1484 + { P_UNIPHY0_RX, 1 },
1485 + { P_UNIPHY0_TX, 2 },
1486 + { P_UBI32_PLL, 5 },
1487 + { P_BIAS_PLL, 6 },
1488 +};
1489 +
1490 static struct clk_rcg2 nss_port1_rx_clk_src = {
1491 .cmd_rcgr = 0x68020,
1492 .freq_tbl = ftbl_nss_port1_rx_clk_src,
1493 @@ -1547,8 +1434,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
1494 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1495 .clkr.hw.init = &(struct clk_init_data){
1496 .name = "nss_port1_rx_clk_src",
1497 - .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1498 - .num_parents = 5,
1499 + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1500 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1501 .ops = &clk_rcg2_ops,
1502 },
1503 };
1504 @@ -1560,9 +1447,8 @@ static struct clk_regmap_div nss_port1_r
1505 .clkr = {
1506 .hw.init = &(struct clk_init_data){
1507 .name = "nss_port1_rx_div_clk_src",
1508 - .parent_names = (const char *[]){
1509 - "nss_port1_rx_clk_src"
1510 - },
1511 + .parent_hws = (const struct clk_hw *[]){
1512 + &nss_port1_rx_clk_src.clkr.hw },
1513 .num_parents = 1,
1514 .ops = &clk_regmap_div_ops,
1515 .flags = CLK_SET_RATE_PARENT,
1516 @@ -1577,6 +1463,22 @@ static const struct freq_tbl ftbl_nss_po
1517 { }
1518 };
1519
1520 +static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
1521 + { .fw_name = "xo", .name = "xo" },
1522 + { .name = "uniphy0_gcc_tx_clk" },
1523 + { .name = "uniphy0_gcc_rx_clk" },
1524 + { .hw = &ubi32_pll.clkr.hw },
1525 + { .name = "bias_pll_cc_clk" },
1526 +};
1527 +
1528 +static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
1529 + { P_XO, 0 },
1530 + { P_UNIPHY0_TX, 1 },
1531 + { P_UNIPHY0_RX, 2 },
1532 + { P_UBI32_PLL, 5 },
1533 + { P_BIAS_PLL, 6 },
1534 +};
1535 +
1536 static struct clk_rcg2 nss_port1_tx_clk_src = {
1537 .cmd_rcgr = 0x68028,
1538 .freq_tbl = ftbl_nss_port1_tx_clk_src,
1539 @@ -1584,8 +1486,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
1540 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1541 .clkr.hw.init = &(struct clk_init_data){
1542 .name = "nss_port1_tx_clk_src",
1543 - .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1544 - .num_parents = 5,
1545 + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1546 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1547 .ops = &clk_rcg2_ops,
1548 },
1549 };
1550 @@ -1597,9 +1499,8 @@ static struct clk_regmap_div nss_port1_t
1551 .clkr = {
1552 .hw.init = &(struct clk_init_data){
1553 .name = "nss_port1_tx_div_clk_src",
1554 - .parent_names = (const char *[]){
1555 - "nss_port1_tx_clk_src"
1556 - },
1557 + .parent_hws = (const struct clk_hw *[]){
1558 + &nss_port1_tx_clk_src.clkr.hw },
1559 .num_parents = 1,
1560 .ops = &clk_regmap_div_ops,
1561 .flags = CLK_SET_RATE_PARENT,
1562 @@ -1614,8 +1515,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
1563 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1564 .clkr.hw.init = &(struct clk_init_data){
1565 .name = "nss_port2_rx_clk_src",
1566 - .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1567 - .num_parents = 5,
1568 + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1569 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1570 .ops = &clk_rcg2_ops,
1571 },
1572 };
1573 @@ -1627,9 +1528,8 @@ static struct clk_regmap_div nss_port2_r
1574 .clkr = {
1575 .hw.init = &(struct clk_init_data){
1576 .name = "nss_port2_rx_div_clk_src",
1577 - .parent_names = (const char *[]){
1578 - "nss_port2_rx_clk_src"
1579 - },
1580 + .parent_hws = (const struct clk_hw *[]){
1581 + &nss_port2_rx_clk_src.clkr.hw },
1582 .num_parents = 1,
1583 .ops = &clk_regmap_div_ops,
1584 .flags = CLK_SET_RATE_PARENT,
1585 @@ -1644,8 +1544,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
1586 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1587 .clkr.hw.init = &(struct clk_init_data){
1588 .name = "nss_port2_tx_clk_src",
1589 - .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1590 - .num_parents = 5,
1591 + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1592 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1593 .ops = &clk_rcg2_ops,
1594 },
1595 };
1596 @@ -1657,9 +1557,8 @@ static struct clk_regmap_div nss_port2_t
1597 .clkr = {
1598 .hw.init = &(struct clk_init_data){
1599 .name = "nss_port2_tx_div_clk_src",
1600 - .parent_names = (const char *[]){
1601 - "nss_port2_tx_clk_src"
1602 - },
1603 + .parent_hws = (const struct clk_hw *[]){
1604 + &nss_port2_tx_clk_src.clkr.hw },
1605 .num_parents = 1,
1606 .ops = &clk_regmap_div_ops,
1607 .flags = CLK_SET_RATE_PARENT,
1608 @@ -1674,8 +1573,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
1609 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1610 .clkr.hw.init = &(struct clk_init_data){
1611 .name = "nss_port3_rx_clk_src",
1612 - .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1613 - .num_parents = 5,
1614 + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1615 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1616 .ops = &clk_rcg2_ops,
1617 },
1618 };
1619 @@ -1687,9 +1586,8 @@ static struct clk_regmap_div nss_port3_r
1620 .clkr = {
1621 .hw.init = &(struct clk_init_data){
1622 .name = "nss_port3_rx_div_clk_src",
1623 - .parent_names = (const char *[]){
1624 - "nss_port3_rx_clk_src"
1625 - },
1626 + .parent_hws = (const struct clk_hw *[]){
1627 + &nss_port3_rx_clk_src.clkr.hw },
1628 .num_parents = 1,
1629 .ops = &clk_regmap_div_ops,
1630 .flags = CLK_SET_RATE_PARENT,
1631 @@ -1704,8 +1602,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
1632 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1633 .clkr.hw.init = &(struct clk_init_data){
1634 .name = "nss_port3_tx_clk_src",
1635 - .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1636 - .num_parents = 5,
1637 + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1638 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1639 .ops = &clk_rcg2_ops,
1640 },
1641 };
1642 @@ -1717,9 +1615,8 @@ static struct clk_regmap_div nss_port3_t
1643 .clkr = {
1644 .hw.init = &(struct clk_init_data){
1645 .name = "nss_port3_tx_div_clk_src",
1646 - .parent_names = (const char *[]){
1647 - "nss_port3_tx_clk_src"
1648 - },
1649 + .parent_hws = (const struct clk_hw *[]){
1650 + &nss_port3_tx_clk_src.clkr.hw },
1651 .num_parents = 1,
1652 .ops = &clk_regmap_div_ops,
1653 .flags = CLK_SET_RATE_PARENT,
1654 @@ -1734,8 +1631,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
1655 .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1656 .clkr.hw.init = &(struct clk_init_data){
1657 .name = "nss_port4_rx_clk_src",
1658 - .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1659 - .num_parents = 5,
1660 + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1661 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1662 .ops = &clk_rcg2_ops,
1663 },
1664 };
1665 @@ -1747,9 +1644,8 @@ static struct clk_regmap_div nss_port4_r
1666 .clkr = {
1667 .hw.init = &(struct clk_init_data){
1668 .name = "nss_port4_rx_div_clk_src",
1669 - .parent_names = (const char *[]){
1670 - "nss_port4_rx_clk_src"
1671 - },
1672 + .parent_hws = (const struct clk_hw *[]){
1673 + &nss_port4_rx_clk_src.clkr.hw },
1674 .num_parents = 1,
1675 .ops = &clk_regmap_div_ops,
1676 .flags = CLK_SET_RATE_PARENT,
1677 @@ -1764,8 +1660,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
1678 .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1679 .clkr.hw.init = &(struct clk_init_data){
1680 .name = "nss_port4_tx_clk_src",
1681 - .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1682 - .num_parents = 5,
1683 + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1684 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1685 .ops = &clk_rcg2_ops,
1686 },
1687 };
1688 @@ -1777,9 +1673,8 @@ static struct clk_regmap_div nss_port4_t
1689 .clkr = {
1690 .hw.init = &(struct clk_init_data){
1691 .name = "nss_port4_tx_div_clk_src",
1692 - .parent_names = (const char *[]){
1693 - "nss_port4_tx_clk_src"
1694 - },
1695 + .parent_hws = (const struct clk_hw *[]){
1696 + &nss_port4_tx_clk_src.clkr.hw },
1697 .num_parents = 1,
1698 .ops = &clk_regmap_div_ops,
1699 .flags = CLK_SET_RATE_PARENT,
1700 @@ -1799,6 +1694,27 @@ static const struct freq_tbl ftbl_nss_po
1701 { }
1702 };
1703
1704 +static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
1705 + { .fw_name = "xo", .name = "xo" },
1706 + { .name = "uniphy0_gcc_rx_clk" },
1707 + { .name = "uniphy0_gcc_tx_clk" },
1708 + { .name = "uniphy1_gcc_rx_clk" },
1709 + { .name = "uniphy1_gcc_tx_clk" },
1710 + { .hw = &ubi32_pll.clkr.hw },
1711 + { .name = "bias_pll_cc_clk" },
1712 +};
1713 +
1714 +static const struct parent_map
1715 +gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
1716 + { P_XO, 0 },
1717 + { P_UNIPHY0_RX, 1 },
1718 + { P_UNIPHY0_TX, 2 },
1719 + { P_UNIPHY1_RX, 3 },
1720 + { P_UNIPHY1_TX, 4 },
1721 + { P_UBI32_PLL, 5 },
1722 + { P_BIAS_PLL, 6 },
1723 +};
1724 +
1725 static struct clk_rcg2 nss_port5_rx_clk_src = {
1726 .cmd_rcgr = 0x68060,
1727 .freq_tbl = ftbl_nss_port5_rx_clk_src,
1728 @@ -1806,8 +1722,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
1729 .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1730 .clkr.hw.init = &(struct clk_init_data){
1731 .name = "nss_port5_rx_clk_src",
1732 - .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1733 - .num_parents = 7,
1734 + .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1735 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1736 .ops = &clk_rcg2_ops,
1737 },
1738 };
1739 @@ -1819,9 +1735,8 @@ static struct clk_regmap_div nss_port5_r
1740 .clkr = {
1741 .hw.init = &(struct clk_init_data){
1742 .name = "nss_port5_rx_div_clk_src",
1743 - .parent_names = (const char *[]){
1744 - "nss_port5_rx_clk_src"
1745 - },
1746 + .parent_hws = (const struct clk_hw *[]){
1747 + &nss_port5_rx_clk_src.clkr.hw },
1748 .num_parents = 1,
1749 .ops = &clk_regmap_div_ops,
1750 .flags = CLK_SET_RATE_PARENT,
1751 @@ -1841,6 +1756,27 @@ static const struct freq_tbl ftbl_nss_po
1752 { }
1753 };
1754
1755 +static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
1756 + { .fw_name = "xo", .name = "xo" },
1757 + { .name = "uniphy0_gcc_tx_clk" },
1758 + { .name = "uniphy0_gcc_rx_clk" },
1759 + { .name = "uniphy1_gcc_tx_clk" },
1760 + { .name = "uniphy1_gcc_rx_clk" },
1761 + { .hw = &ubi32_pll.clkr.hw },
1762 + { .name = "bias_pll_cc_clk" },
1763 +};
1764 +
1765 +static const struct parent_map
1766 +gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
1767 + { P_XO, 0 },
1768 + { P_UNIPHY0_TX, 1 },
1769 + { P_UNIPHY0_RX, 2 },
1770 + { P_UNIPHY1_TX, 3 },
1771 + { P_UNIPHY1_RX, 4 },
1772 + { P_UBI32_PLL, 5 },
1773 + { P_BIAS_PLL, 6 },
1774 +};
1775 +
1776 static struct clk_rcg2 nss_port5_tx_clk_src = {
1777 .cmd_rcgr = 0x68068,
1778 .freq_tbl = ftbl_nss_port5_tx_clk_src,
1779 @@ -1848,8 +1784,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
1780 .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1781 .clkr.hw.init = &(struct clk_init_data){
1782 .name = "nss_port5_tx_clk_src",
1783 - .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1784 - .num_parents = 7,
1785 + .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1786 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1787 .ops = &clk_rcg2_ops,
1788 },
1789 };
1790 @@ -1861,9 +1797,8 @@ static struct clk_regmap_div nss_port5_t
1791 .clkr = {
1792 .hw.init = &(struct clk_init_data){
1793 .name = "nss_port5_tx_div_clk_src",
1794 - .parent_names = (const char *[]){
1795 - "nss_port5_tx_clk_src"
1796 - },
1797 + .parent_hws = (const struct clk_hw *[]){
1798 + &nss_port5_tx_clk_src.clkr.hw },
1799 .num_parents = 1,
1800 .ops = &clk_regmap_div_ops,
1801 .flags = CLK_SET_RATE_PARENT,
1802 @@ -1883,6 +1818,22 @@ static const struct freq_tbl ftbl_nss_po
1803 { }
1804 };
1805
1806 +static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
1807 + { .fw_name = "xo", .name = "xo" },
1808 + { .name = "uniphy2_gcc_rx_clk" },
1809 + { .name = "uniphy2_gcc_tx_clk" },
1810 + { .hw = &ubi32_pll.clkr.hw },
1811 + { .name = "bias_pll_cc_clk" },
1812 +};
1813 +
1814 +static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
1815 + { P_XO, 0 },
1816 + { P_UNIPHY2_RX, 1 },
1817 + { P_UNIPHY2_TX, 2 },
1818 + { P_UBI32_PLL, 5 },
1819 + { P_BIAS_PLL, 6 },
1820 +};
1821 +
1822 static struct clk_rcg2 nss_port6_rx_clk_src = {
1823 .cmd_rcgr = 0x68070,
1824 .freq_tbl = ftbl_nss_port6_rx_clk_src,
1825 @@ -1890,8 +1841,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
1826 .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1827 .clkr.hw.init = &(struct clk_init_data){
1828 .name = "nss_port6_rx_clk_src",
1829 - .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1830 - .num_parents = 5,
1831 + .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1832 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1833 .ops = &clk_rcg2_ops,
1834 },
1835 };
1836 @@ -1903,9 +1854,8 @@ static struct clk_regmap_div nss_port6_r
1837 .clkr = {
1838 .hw.init = &(struct clk_init_data){
1839 .name = "nss_port6_rx_div_clk_src",
1840 - .parent_names = (const char *[]){
1841 - "nss_port6_rx_clk_src"
1842 - },
1843 + .parent_hws = (const struct clk_hw *[]){
1844 + &nss_port6_rx_clk_src.clkr.hw },
1845 .num_parents = 1,
1846 .ops = &clk_regmap_div_ops,
1847 .flags = CLK_SET_RATE_PARENT,
1848 @@ -1925,6 +1875,22 @@ static const struct freq_tbl ftbl_nss_po
1849 { }
1850 };
1851
1852 +static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
1853 + { .fw_name = "xo", .name = "xo" },
1854 + { .name = "uniphy2_gcc_tx_clk" },
1855 + { .name = "uniphy2_gcc_rx_clk" },
1856 + { .hw = &ubi32_pll.clkr.hw },
1857 + { .name = "bias_pll_cc_clk" },
1858 +};
1859 +
1860 +static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
1861 + { P_XO, 0 },
1862 + { P_UNIPHY2_TX, 1 },
1863 + { P_UNIPHY2_RX, 2 },
1864 + { P_UBI32_PLL, 5 },
1865 + { P_BIAS_PLL, 6 },
1866 +};
1867 +
1868 static struct clk_rcg2 nss_port6_tx_clk_src = {
1869 .cmd_rcgr = 0x68078,
1870 .freq_tbl = ftbl_nss_port6_tx_clk_src,
1871 @@ -1932,8 +1898,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
1872 .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1873 .clkr.hw.init = &(struct clk_init_data){
1874 .name = "nss_port6_tx_clk_src",
1875 - .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1876 - .num_parents = 5,
1877 + .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1878 + .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1879 .ops = &clk_rcg2_ops,
1880 },
1881 };
1882 @@ -1945,9 +1911,8 @@ static struct clk_regmap_div nss_port6_t
1883 .clkr = {
1884 .hw.init = &(struct clk_init_data){
1885 .name = "nss_port6_tx_div_clk_src",
1886 - .parent_names = (const char *[]){
1887 - "nss_port6_tx_clk_src"
1888 - },
1889 + .parent_hws = (const struct clk_hw *[]){
1890 + &nss_port6_tx_clk_src.clkr.hw },
1891 .num_parents = 1,
1892 .ops = &clk_regmap_div_ops,
1893 .flags = CLK_SET_RATE_PARENT,
1894 @@ -1970,8 +1935,8 @@ static struct clk_rcg2 crypto_clk_src =
1895 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1896 .clkr.hw.init = &(struct clk_init_data){
1897 .name = "crypto_clk_src",
1898 - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1899 - .num_parents = 3,
1900 + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1901 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1902 .ops = &clk_rcg2_ops,
1903 },
1904 };
1905 @@ -1981,6 +1946,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
1906 { }
1907 };
1908
1909 +static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1910 + { .fw_name = "xo", .name = "xo" },
1911 + { .hw = &gpll0.clkr.hw },
1912 + { .hw = &gpll6.clkr.hw },
1913 + { .hw = &gpll0_out_main_div2.hw },
1914 + { .fw_name = "sleep_clk", .name = "sleep_clk" },
1915 +};
1916 +
1917 +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1918 + { P_XO, 0 },
1919 + { P_GPLL0, 1 },
1920 + { P_GPLL6, 2 },
1921 + { P_GPLL0_DIV2, 4 },
1922 + { P_SLEEP_CLK, 6 },
1923 +};
1924 +
1925 static struct clk_rcg2 gp1_clk_src = {
1926 .cmd_rcgr = 0x08004,
1927 .freq_tbl = ftbl_gp_clk_src,
1928 @@ -1989,8 +1970,8 @@ static struct clk_rcg2 gp1_clk_src = {
1929 .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1930 .clkr.hw.init = &(struct clk_init_data){
1931 .name = "gp1_clk_src",
1932 - .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1933 - .num_parents = 5,
1934 + .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1935 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1936 .ops = &clk_rcg2_ops,
1937 },
1938 };
1939 @@ -2003,8 +1984,8 @@ static struct clk_rcg2 gp2_clk_src = {
1940 .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1941 .clkr.hw.init = &(struct clk_init_data){
1942 .name = "gp2_clk_src",
1943 - .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1944 - .num_parents = 5,
1945 + .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1946 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1947 .ops = &clk_rcg2_ops,
1948 },
1949 };
1950 @@ -2017,8 +1998,8 @@ static struct clk_rcg2 gp3_clk_src = {
1951 .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1952 .clkr.hw.init = &(struct clk_init_data){
1953 .name = "gp3_clk_src",
1954 - .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1955 - .num_parents = 5,
1956 + .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1957 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1958 .ops = &clk_rcg2_ops,
1959 },
1960 };
1961 @@ -2030,9 +2011,8 @@ static struct clk_branch gcc_blsp1_ahb_c
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "gcc_blsp1_ahb_clk",
1965 - .parent_names = (const char *[]){
1966 - "pcnoc_clk_src"
1967 - },
1968 + .parent_hws = (const struct clk_hw *[]){
1969 + &pcnoc_clk_src.hw },
1970 .num_parents = 1,
1971 .flags = CLK_SET_RATE_PARENT,
1972 .ops = &clk_branch2_ops,
1973 @@ -2047,9 +2027,8 @@ static struct clk_branch gcc_blsp1_qup1_
1974 .enable_mask = BIT(0),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1977 - .parent_names = (const char *[]){
1978 - "blsp1_qup1_i2c_apps_clk_src"
1979 - },
1980 + .parent_hws = (const struct clk_hw *[]){
1981 + &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1982 .num_parents = 1,
1983 .flags = CLK_SET_RATE_PARENT,
1984 .ops = &clk_branch2_ops,
1985 @@ -2064,9 +2043,8 @@ static struct clk_branch gcc_blsp1_qup1_
1986 .enable_mask = BIT(0),
1987 .hw.init = &(struct clk_init_data){
1988 .name = "gcc_blsp1_qup1_spi_apps_clk",
1989 - .parent_names = (const char *[]){
1990 - "blsp1_qup1_spi_apps_clk_src"
1991 - },
1992 + .parent_hws = (const struct clk_hw *[]){
1993 + &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1994 .num_parents = 1,
1995 .flags = CLK_SET_RATE_PARENT,
1996 .ops = &clk_branch2_ops,
1997 @@ -2081,9 +2059,8 @@ static struct clk_branch gcc_blsp1_qup2_
1998 .enable_mask = BIT(0),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "gcc_blsp1_qup2_i2c_apps_clk",
2001 - .parent_names = (const char *[]){
2002 - "blsp1_qup2_i2c_apps_clk_src"
2003 - },
2004 + .parent_hws = (const struct clk_hw *[]){
2005 + &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2006 .num_parents = 1,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2009 @@ -2098,9 +2075,8 @@ static struct clk_branch gcc_blsp1_qup2_
2010 .enable_mask = BIT(0),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_blsp1_qup2_spi_apps_clk",
2013 - .parent_names = (const char *[]){
2014 - "blsp1_qup2_spi_apps_clk_src"
2015 - },
2016 + .parent_hws = (const struct clk_hw *[]){
2017 + &blsp1_qup2_spi_apps_clk_src.clkr.hw },
2018 .num_parents = 1,
2019 .flags = CLK_SET_RATE_PARENT,
2020 .ops = &clk_branch2_ops,
2021 @@ -2115,9 +2091,8 @@ static struct clk_branch gcc_blsp1_qup3_
2022 .enable_mask = BIT(0),
2023 .hw.init = &(struct clk_init_data){
2024 .name = "gcc_blsp1_qup3_i2c_apps_clk",
2025 - .parent_names = (const char *[]){
2026 - "blsp1_qup3_i2c_apps_clk_src"
2027 - },
2028 + .parent_hws = (const struct clk_hw *[]){
2029 + &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2030 .num_parents = 1,
2031 .flags = CLK_SET_RATE_PARENT,
2032 .ops = &clk_branch2_ops,
2033 @@ -2132,9 +2107,8 @@ static struct clk_branch gcc_blsp1_qup3_
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gcc_blsp1_qup3_spi_apps_clk",
2037 - .parent_names = (const char *[]){
2038 - "blsp1_qup3_spi_apps_clk_src"
2039 - },
2040 + .parent_hws = (const struct clk_hw *[]){
2041 + &blsp1_qup3_spi_apps_clk_src.clkr.hw },
2042 .num_parents = 1,
2043 .flags = CLK_SET_RATE_PARENT,
2044 .ops = &clk_branch2_ops,
2045 @@ -2149,9 +2123,8 @@ static struct clk_branch gcc_blsp1_qup4_
2046 .enable_mask = BIT(0),
2047 .hw.init = &(struct clk_init_data){
2048 .name = "gcc_blsp1_qup4_i2c_apps_clk",
2049 - .parent_names = (const char *[]){
2050 - "blsp1_qup4_i2c_apps_clk_src"
2051 - },
2052 + .parent_hws = (const struct clk_hw *[]){
2053 + &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2054 .num_parents = 1,
2055 .flags = CLK_SET_RATE_PARENT,
2056 .ops = &clk_branch2_ops,
2057 @@ -2166,9 +2139,8 @@ static struct clk_branch gcc_blsp1_qup4_
2058 .enable_mask = BIT(0),
2059 .hw.init = &(struct clk_init_data){
2060 .name = "gcc_blsp1_qup4_spi_apps_clk",
2061 - .parent_names = (const char *[]){
2062 - "blsp1_qup4_spi_apps_clk_src"
2063 - },
2064 + .parent_hws = (const struct clk_hw *[]){
2065 + &blsp1_qup4_spi_apps_clk_src.clkr.hw },
2066 .num_parents = 1,
2067 .flags = CLK_SET_RATE_PARENT,
2068 .ops = &clk_branch2_ops,
2069 @@ -2183,9 +2155,8 @@ static struct clk_branch gcc_blsp1_qup5_
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "gcc_blsp1_qup5_i2c_apps_clk",
2073 - .parent_names = (const char *[]){
2074 - "blsp1_qup5_i2c_apps_clk_src"
2075 - },
2076 + .parent_hws = (const struct clk_hw *[]){
2077 + &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2078 .num_parents = 1,
2079 .flags = CLK_SET_RATE_PARENT,
2080 .ops = &clk_branch2_ops,
2081 @@ -2200,9 +2171,8 @@ static struct clk_branch gcc_blsp1_qup5_
2082 .enable_mask = BIT(0),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gcc_blsp1_qup5_spi_apps_clk",
2085 - .parent_names = (const char *[]){
2086 - "blsp1_qup5_spi_apps_clk_src"
2087 - },
2088 + .parent_hws = (const struct clk_hw *[]){
2089 + &blsp1_qup5_spi_apps_clk_src.clkr.hw },
2090 .num_parents = 1,
2091 .flags = CLK_SET_RATE_PARENT,
2092 .ops = &clk_branch2_ops,
2093 @@ -2217,9 +2187,8 @@ static struct clk_branch gcc_blsp1_qup6_
2094 .enable_mask = BIT(0),
2095 .hw.init = &(struct clk_init_data){
2096 .name = "gcc_blsp1_qup6_i2c_apps_clk",
2097 - .parent_names = (const char *[]){
2098 - "blsp1_qup6_i2c_apps_clk_src"
2099 - },
2100 + .parent_hws = (const struct clk_hw *[]){
2101 + &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2102 .num_parents = 1,
2103 .flags = CLK_SET_RATE_PARENT,
2104 .ops = &clk_branch2_ops,
2105 @@ -2234,9 +2203,8 @@ static struct clk_branch gcc_blsp1_qup6_
2106 .enable_mask = BIT(0),
2107 .hw.init = &(struct clk_init_data){
2108 .name = "gcc_blsp1_qup6_spi_apps_clk",
2109 - .parent_names = (const char *[]){
2110 - "blsp1_qup6_spi_apps_clk_src"
2111 - },
2112 + .parent_hws = (const struct clk_hw *[]){
2113 + &blsp1_qup6_spi_apps_clk_src.clkr.hw },
2114 .num_parents = 1,
2115 .flags = CLK_SET_RATE_PARENT,
2116 .ops = &clk_branch2_ops,
2117 @@ -2251,9 +2219,8 @@ static struct clk_branch gcc_blsp1_uart1
2118 .enable_mask = BIT(0),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "gcc_blsp1_uart1_apps_clk",
2121 - .parent_names = (const char *[]){
2122 - "blsp1_uart1_apps_clk_src"
2123 - },
2124 + .parent_hws = (const struct clk_hw *[]){
2125 + &blsp1_uart1_apps_clk_src.clkr.hw },
2126 .num_parents = 1,
2127 .flags = CLK_SET_RATE_PARENT,
2128 .ops = &clk_branch2_ops,
2129 @@ -2268,9 +2235,8 @@ static struct clk_branch gcc_blsp1_uart2
2130 .enable_mask = BIT(0),
2131 .hw.init = &(struct clk_init_data){
2132 .name = "gcc_blsp1_uart2_apps_clk",
2133 - .parent_names = (const char *[]){
2134 - "blsp1_uart2_apps_clk_src"
2135 - },
2136 + .parent_hws = (const struct clk_hw *[]){
2137 + &blsp1_uart2_apps_clk_src.clkr.hw },
2138 .num_parents = 1,
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2141 @@ -2285,9 +2251,8 @@ static struct clk_branch gcc_blsp1_uart3
2142 .enable_mask = BIT(0),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gcc_blsp1_uart3_apps_clk",
2145 - .parent_names = (const char *[]){
2146 - "blsp1_uart3_apps_clk_src"
2147 - },
2148 + .parent_hws = (const struct clk_hw *[]){
2149 + &blsp1_uart3_apps_clk_src.clkr.hw },
2150 .num_parents = 1,
2151 .flags = CLK_SET_RATE_PARENT,
2152 .ops = &clk_branch2_ops,
2153 @@ -2302,9 +2267,8 @@ static struct clk_branch gcc_blsp1_uart4
2154 .enable_mask = BIT(0),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "gcc_blsp1_uart4_apps_clk",
2157 - .parent_names = (const char *[]){
2158 - "blsp1_uart4_apps_clk_src"
2159 - },
2160 + .parent_hws = (const struct clk_hw *[]){
2161 + &blsp1_uart4_apps_clk_src.clkr.hw },
2162 .num_parents = 1,
2163 .flags = CLK_SET_RATE_PARENT,
2164 .ops = &clk_branch2_ops,
2165 @@ -2319,9 +2283,8 @@ static struct clk_branch gcc_blsp1_uart5
2166 .enable_mask = BIT(0),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "gcc_blsp1_uart5_apps_clk",
2169 - .parent_names = (const char *[]){
2170 - "blsp1_uart5_apps_clk_src"
2171 - },
2172 + .parent_hws = (const struct clk_hw *[]){
2173 + &blsp1_uart5_apps_clk_src.clkr.hw },
2174 .num_parents = 1,
2175 .flags = CLK_SET_RATE_PARENT,
2176 .ops = &clk_branch2_ops,
2177 @@ -2336,9 +2299,8 @@ static struct clk_branch gcc_blsp1_uart6
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_blsp1_uart6_apps_clk",
2181 - .parent_names = (const char *[]){
2182 - "blsp1_uart6_apps_clk_src"
2183 - },
2184 + .parent_hws = (const struct clk_hw *[]){
2185 + &blsp1_uart6_apps_clk_src.clkr.hw },
2186 .num_parents = 1,
2187 .flags = CLK_SET_RATE_PARENT,
2188 .ops = &clk_branch2_ops,
2189 @@ -2354,9 +2316,8 @@ static struct clk_branch gcc_prng_ahb_cl
2190 .enable_mask = BIT(8),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_prng_ahb_clk",
2193 - .parent_names = (const char *[]){
2194 - "pcnoc_clk_src"
2195 - },
2196 + .parent_hws = (const struct clk_hw *[]){
2197 + &pcnoc_clk_src.hw },
2198 .num_parents = 1,
2199 .flags = CLK_SET_RATE_PARENT,
2200 .ops = &clk_branch2_ops,
2201 @@ -2371,9 +2332,8 @@ static struct clk_branch gcc_qpic_ahb_cl
2202 .enable_mask = BIT(0),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "gcc_qpic_ahb_clk",
2205 - .parent_names = (const char *[]){
2206 - "pcnoc_clk_src"
2207 - },
2208 + .parent_hws = (const struct clk_hw *[]){
2209 + &pcnoc_clk_src.hw },
2210 .num_parents = 1,
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2213 @@ -2388,9 +2348,8 @@ static struct clk_branch gcc_qpic_clk =
2214 .enable_mask = BIT(0),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "gcc_qpic_clk",
2217 - .parent_names = (const char *[]){
2218 - "pcnoc_clk_src"
2219 - },
2220 + .parent_hws = (const struct clk_hw *[]){
2221 + &pcnoc_clk_src.hw },
2222 .num_parents = 1,
2223 .flags = CLK_SET_RATE_PARENT,
2224 .ops = &clk_branch2_ops,
2225 @@ -2405,9 +2364,8 @@ static struct clk_branch gcc_pcie0_ahb_c
2226 .enable_mask = BIT(0),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_pcie0_ahb_clk",
2229 - .parent_names = (const char *[]){
2230 - "pcnoc_clk_src"
2231 - },
2232 + .parent_hws = (const struct clk_hw *[]){
2233 + &pcnoc_clk_src.hw },
2234 .num_parents = 1,
2235 .flags = CLK_SET_RATE_PARENT,
2236 .ops = &clk_branch2_ops,
2237 @@ -2422,9 +2380,8 @@ static struct clk_branch gcc_pcie0_aux_c
2238 .enable_mask = BIT(0),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "gcc_pcie0_aux_clk",
2241 - .parent_names = (const char *[]){
2242 - "pcie0_aux_clk_src"
2243 - },
2244 + .parent_hws = (const struct clk_hw *[]){
2245 + &pcie0_aux_clk_src.clkr.hw },
2246 .num_parents = 1,
2247 .flags = CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2249 @@ -2439,9 +2396,8 @@ static struct clk_branch gcc_pcie0_axi_m
2250 .enable_mask = BIT(0),
2251 .hw.init = &(struct clk_init_data){
2252 .name = "gcc_pcie0_axi_m_clk",
2253 - .parent_names = (const char *[]){
2254 - "pcie0_axi_clk_src"
2255 - },
2256 + .parent_hws = (const struct clk_hw *[]){
2257 + &pcie0_axi_clk_src.clkr.hw },
2258 .num_parents = 1,
2259 .flags = CLK_SET_RATE_PARENT,
2260 .ops = &clk_branch2_ops,
2261 @@ -2456,9 +2412,8 @@ static struct clk_branch gcc_pcie0_axi_s
2262 .enable_mask = BIT(0),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "gcc_pcie0_axi_s_clk",
2265 - .parent_names = (const char *[]){
2266 - "pcie0_axi_clk_src"
2267 - },
2268 + .parent_hws = (const struct clk_hw *[]){
2269 + &pcie0_axi_clk_src.clkr.hw },
2270 .num_parents = 1,
2271 .flags = CLK_SET_RATE_PARENT,
2272 .ops = &clk_branch2_ops,
2273 @@ -2474,9 +2429,8 @@ static struct clk_branch gcc_pcie0_pipe_
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "gcc_pcie0_pipe_clk",
2277 - .parent_names = (const char *[]){
2278 - "pcie0_pipe_clk_src"
2279 - },
2280 + .parent_hws = (const struct clk_hw *[]){
2281 + &pcie0_pipe_clk_src.clkr.hw },
2282 .num_parents = 1,
2283 .flags = CLK_SET_RATE_PARENT,
2284 .ops = &clk_branch2_ops,
2285 @@ -2491,9 +2445,8 @@ static struct clk_branch gcc_sys_noc_pci
2286 .enable_mask = BIT(0),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_sys_noc_pcie0_axi_clk",
2289 - .parent_names = (const char *[]){
2290 - "pcie0_axi_clk_src"
2291 - },
2292 + .parent_hws = (const struct clk_hw *[]){
2293 + &pcie0_axi_clk_src.clkr.hw },
2294 .num_parents = 1,
2295 .flags = CLK_SET_RATE_PARENT,
2296 .ops = &clk_branch2_ops,
2297 @@ -2508,9 +2461,8 @@ static struct clk_branch gcc_pcie1_ahb_c
2298 .enable_mask = BIT(0),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_pcie1_ahb_clk",
2301 - .parent_names = (const char *[]){
2302 - "pcnoc_clk_src"
2303 - },
2304 + .parent_hws = (const struct clk_hw *[]){
2305 + &pcnoc_clk_src.hw },
2306 .num_parents = 1,
2307 .flags = CLK_SET_RATE_PARENT,
2308 .ops = &clk_branch2_ops,
2309 @@ -2525,9 +2477,8 @@ static struct clk_branch gcc_pcie1_aux_c
2310 .enable_mask = BIT(0),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gcc_pcie1_aux_clk",
2313 - .parent_names = (const char *[]){
2314 - "pcie1_aux_clk_src"
2315 - },
2316 + .parent_hws = (const struct clk_hw *[]){
2317 + &pcie1_aux_clk_src.clkr.hw },
2318 .num_parents = 1,
2319 .flags = CLK_SET_RATE_PARENT,
2320 .ops = &clk_branch2_ops,
2321 @@ -2542,9 +2493,8 @@ static struct clk_branch gcc_pcie1_axi_m
2322 .enable_mask = BIT(0),
2323 .hw.init = &(struct clk_init_data){
2324 .name = "gcc_pcie1_axi_m_clk",
2325 - .parent_names = (const char *[]){
2326 - "pcie1_axi_clk_src"
2327 - },
2328 + .parent_hws = (const struct clk_hw *[]){
2329 + &pcie1_axi_clk_src.clkr.hw },
2330 .num_parents = 1,
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2333 @@ -2559,9 +2509,8 @@ static struct clk_branch gcc_pcie1_axi_s
2334 .enable_mask = BIT(0),
2335 .hw.init = &(struct clk_init_data){
2336 .name = "gcc_pcie1_axi_s_clk",
2337 - .parent_names = (const char *[]){
2338 - "pcie1_axi_clk_src"
2339 - },
2340 + .parent_hws = (const struct clk_hw *[]){
2341 + &pcie1_axi_clk_src.clkr.hw },
2342 .num_parents = 1,
2343 .flags = CLK_SET_RATE_PARENT,
2344 .ops = &clk_branch2_ops,
2345 @@ -2577,9 +2526,8 @@ static struct clk_branch gcc_pcie1_pipe_
2346 .enable_mask = BIT(0),
2347 .hw.init = &(struct clk_init_data){
2348 .name = "gcc_pcie1_pipe_clk",
2349 - .parent_names = (const char *[]){
2350 - "pcie1_pipe_clk_src"
2351 - },
2352 + .parent_hws = (const struct clk_hw *[]){
2353 + &pcie1_pipe_clk_src.clkr.hw },
2354 .num_parents = 1,
2355 .flags = CLK_SET_RATE_PARENT,
2356 .ops = &clk_branch2_ops,
2357 @@ -2594,9 +2542,8 @@ static struct clk_branch gcc_sys_noc_pci
2358 .enable_mask = BIT(0),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "gcc_sys_noc_pcie1_axi_clk",
2361 - .parent_names = (const char *[]){
2362 - "pcie1_axi_clk_src"
2363 - },
2364 + .parent_hws = (const struct clk_hw *[]){
2365 + &pcie1_axi_clk_src.clkr.hw },
2366 .num_parents = 1,
2367 .flags = CLK_SET_RATE_PARENT,
2368 .ops = &clk_branch2_ops,
2369 @@ -2611,9 +2558,8 @@ static struct clk_branch gcc_usb0_aux_cl
2370 .enable_mask = BIT(0),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "gcc_usb0_aux_clk",
2373 - .parent_names = (const char *[]){
2374 - "usb0_aux_clk_src"
2375 - },
2376 + .parent_hws = (const struct clk_hw *[]){
2377 + &usb0_aux_clk_src.clkr.hw },
2378 .num_parents = 1,
2379 .flags = CLK_SET_RATE_PARENT,
2380 .ops = &clk_branch2_ops,
2381 @@ -2628,9 +2574,8 @@ static struct clk_branch gcc_sys_noc_usb
2382 .enable_mask = BIT(0),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "gcc_sys_noc_usb0_axi_clk",
2385 - .parent_names = (const char *[]){
2386 - "usb0_master_clk_src"
2387 - },
2388 + .parent_hws = (const struct clk_hw *[]){
2389 + &usb0_master_clk_src.clkr.hw },
2390 .num_parents = 1,
2391 .flags = CLK_SET_RATE_PARENT,
2392 .ops = &clk_branch2_ops,
2393 @@ -2645,9 +2590,8 @@ static struct clk_branch gcc_usb0_master
2394 .enable_mask = BIT(0),
2395 .hw.init = &(struct clk_init_data){
2396 .name = "gcc_usb0_master_clk",
2397 - .parent_names = (const char *[]){
2398 - "usb0_master_clk_src"
2399 - },
2400 + .parent_hws = (const struct clk_hw *[]){
2401 + &usb0_master_clk_src.clkr.hw },
2402 .num_parents = 1,
2403 .flags = CLK_SET_RATE_PARENT,
2404 .ops = &clk_branch2_ops,
2405 @@ -2662,9 +2606,8 @@ static struct clk_branch gcc_usb0_mock_u
2406 .enable_mask = BIT(0),
2407 .hw.init = &(struct clk_init_data){
2408 .name = "gcc_usb0_mock_utmi_clk",
2409 - .parent_names = (const char *[]){
2410 - "usb0_mock_utmi_clk_src"
2411 - },
2412 + .parent_hws = (const struct clk_hw *[]){
2413 + &usb0_mock_utmi_clk_src.clkr.hw },
2414 .num_parents = 1,
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2417 @@ -2679,9 +2622,8 @@ static struct clk_branch gcc_usb0_phy_cf
2418 .enable_mask = BIT(0),
2419 .hw.init = &(struct clk_init_data){
2420 .name = "gcc_usb0_phy_cfg_ahb_clk",
2421 - .parent_names = (const char *[]){
2422 - "pcnoc_clk_src"
2423 - },
2424 + .parent_hws = (const struct clk_hw *[]){
2425 + &pcnoc_clk_src.hw },
2426 .num_parents = 1,
2427 .flags = CLK_SET_RATE_PARENT,
2428 .ops = &clk_branch2_ops,
2429 @@ -2697,9 +2639,8 @@ static struct clk_branch gcc_usb0_pipe_c
2430 .enable_mask = BIT(0),
2431 .hw.init = &(struct clk_init_data){
2432 .name = "gcc_usb0_pipe_clk",
2433 - .parent_names = (const char *[]){
2434 - "usb0_pipe_clk_src"
2435 - },
2436 + .parent_hws = (const struct clk_hw *[]){
2437 + &usb0_pipe_clk_src.clkr.hw },
2438 .num_parents = 1,
2439 .flags = CLK_SET_RATE_PARENT,
2440 .ops = &clk_branch2_ops,
2441 @@ -2714,9 +2655,8 @@ static struct clk_branch gcc_usb0_sleep_
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "gcc_usb0_sleep_clk",
2445 - .parent_names = (const char *[]){
2446 - "gcc_sleep_clk_src"
2447 - },
2448 + .parent_hws = (const struct clk_hw *[]){
2449 + &gcc_sleep_clk_src.clkr.hw },
2450 .num_parents = 1,
2451 .flags = CLK_SET_RATE_PARENT,
2452 .ops = &clk_branch2_ops,
2453 @@ -2731,9 +2671,8 @@ static struct clk_branch gcc_usb1_aux_cl
2454 .enable_mask = BIT(0),
2455 .hw.init = &(struct clk_init_data){
2456 .name = "gcc_usb1_aux_clk",
2457 - .parent_names = (const char *[]){
2458 - "usb1_aux_clk_src"
2459 - },
2460 + .parent_hws = (const struct clk_hw *[]){
2461 + &usb1_aux_clk_src.clkr.hw },
2462 .num_parents = 1,
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2465 @@ -2748,9 +2687,8 @@ static struct clk_branch gcc_sys_noc_usb
2466 .enable_mask = BIT(0),
2467 .hw.init = &(struct clk_init_data){
2468 .name = "gcc_sys_noc_usb1_axi_clk",
2469 - .parent_names = (const char *[]){
2470 - "usb1_master_clk_src"
2471 - },
2472 + .parent_hws = (const struct clk_hw *[]){
2473 + &usb1_master_clk_src.clkr.hw },
2474 .num_parents = 1,
2475 .flags = CLK_SET_RATE_PARENT,
2476 .ops = &clk_branch2_ops,
2477 @@ -2765,9 +2703,8 @@ static struct clk_branch gcc_usb1_master
2478 .enable_mask = BIT(0),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "gcc_usb1_master_clk",
2481 - .parent_names = (const char *[]){
2482 - "usb1_master_clk_src"
2483 - },
2484 + .parent_hws = (const struct clk_hw *[]){
2485 + &usb1_master_clk_src.clkr.hw },
2486 .num_parents = 1,
2487 .flags = CLK_SET_RATE_PARENT,
2488 .ops = &clk_branch2_ops,
2489 @@ -2782,9 +2719,8 @@ static struct clk_branch gcc_usb1_mock_u
2490 .enable_mask = BIT(0),
2491 .hw.init = &(struct clk_init_data){
2492 .name = "gcc_usb1_mock_utmi_clk",
2493 - .parent_names = (const char *[]){
2494 - "usb1_mock_utmi_clk_src"
2495 - },
2496 + .parent_hws = (const struct clk_hw *[]){
2497 + &usb1_mock_utmi_clk_src.clkr.hw },
2498 .num_parents = 1,
2499 .flags = CLK_SET_RATE_PARENT,
2500 .ops = &clk_branch2_ops,
2501 @@ -2799,9 +2735,8 @@ static struct clk_branch gcc_usb1_phy_cf
2502 .enable_mask = BIT(0),
2503 .hw.init = &(struct clk_init_data){
2504 .name = "gcc_usb1_phy_cfg_ahb_clk",
2505 - .parent_names = (const char *[]){
2506 - "pcnoc_clk_src"
2507 - },
2508 + .parent_hws = (const struct clk_hw *[]){
2509 + &pcnoc_clk_src.hw },
2510 .num_parents = 1,
2511 .flags = CLK_SET_RATE_PARENT,
2512 .ops = &clk_branch2_ops,
2513 @@ -2817,9 +2752,8 @@ static struct clk_branch gcc_usb1_pipe_c
2514 .enable_mask = BIT(0),
2515 .hw.init = &(struct clk_init_data){
2516 .name = "gcc_usb1_pipe_clk",
2517 - .parent_names = (const char *[]){
2518 - "usb1_pipe_clk_src"
2519 - },
2520 + .parent_hws = (const struct clk_hw *[]){
2521 + &usb1_pipe_clk_src.clkr.hw },
2522 .num_parents = 1,
2523 .flags = CLK_SET_RATE_PARENT,
2524 .ops = &clk_branch2_ops,
2525 @@ -2834,9 +2768,8 @@ static struct clk_branch gcc_usb1_sleep_
2526 .enable_mask = BIT(0),
2527 .hw.init = &(struct clk_init_data){
2528 .name = "gcc_usb1_sleep_clk",
2529 - .parent_names = (const char *[]){
2530 - "gcc_sleep_clk_src"
2531 - },
2532 + .parent_hws = (const struct clk_hw *[]){
2533 + &gcc_sleep_clk_src.clkr.hw },
2534 .num_parents = 1,
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_branch2_ops,
2537 @@ -2851,9 +2784,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
2538 .enable_mask = BIT(0),
2539 .hw.init = &(struct clk_init_data){
2540 .name = "gcc_sdcc1_ahb_clk",
2541 - .parent_names = (const char *[]){
2542 - "pcnoc_clk_src"
2543 - },
2544 + .parent_hws = (const struct clk_hw *[]){
2545 + &pcnoc_clk_src.hw },
2546 .num_parents = 1,
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2549 @@ -2868,9 +2800,8 @@ static struct clk_branch gcc_sdcc1_apps_
2550 .enable_mask = BIT(0),
2551 .hw.init = &(struct clk_init_data){
2552 .name = "gcc_sdcc1_apps_clk",
2553 - .parent_names = (const char *[]){
2554 - "sdcc1_apps_clk_src"
2555 - },
2556 + .parent_hws = (const struct clk_hw *[]){
2557 + &sdcc1_apps_clk_src.clkr.hw },
2558 .num_parents = 1,
2559 .flags = CLK_SET_RATE_PARENT,
2560 .ops = &clk_branch2_ops,
2561 @@ -2885,9 +2816,8 @@ static struct clk_branch gcc_sdcc1_ice_c
2562 .enable_mask = BIT(0),
2563 .hw.init = &(struct clk_init_data){
2564 .name = "gcc_sdcc1_ice_core_clk",
2565 - .parent_names = (const char *[]){
2566 - "sdcc1_ice_core_clk_src"
2567 - },
2568 + .parent_hws = (const struct clk_hw *[]){
2569 + &sdcc1_ice_core_clk_src.clkr.hw },
2570 .num_parents = 1,
2571 .flags = CLK_SET_RATE_PARENT,
2572 .ops = &clk_branch2_ops,
2573 @@ -2902,9 +2832,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "gcc_sdcc2_ahb_clk",
2577 - .parent_names = (const char *[]){
2578 - "pcnoc_clk_src"
2579 - },
2580 + .parent_hws = (const struct clk_hw *[]){
2581 + &pcnoc_clk_src.hw },
2582 .num_parents = 1,
2583 .flags = CLK_SET_RATE_PARENT,
2584 .ops = &clk_branch2_ops,
2585 @@ -2919,9 +2848,8 @@ static struct clk_branch gcc_sdcc2_apps_
2586 .enable_mask = BIT(0),
2587 .hw.init = &(struct clk_init_data){
2588 .name = "gcc_sdcc2_apps_clk",
2589 - .parent_names = (const char *[]){
2590 - "sdcc2_apps_clk_src"
2591 - },
2592 + .parent_hws = (const struct clk_hw *[]){
2593 + &sdcc2_apps_clk_src.clkr.hw },
2594 .num_parents = 1,
2595 .flags = CLK_SET_RATE_PARENT,
2596 .ops = &clk_branch2_ops,
2597 @@ -2936,9 +2864,8 @@ static struct clk_branch gcc_mem_noc_nss
2598 .enable_mask = BIT(0),
2599 .hw.init = &(struct clk_init_data){
2600 .name = "gcc_mem_noc_nss_axi_clk",
2601 - .parent_names = (const char *[]){
2602 - "nss_noc_clk_src"
2603 - },
2604 + .parent_hws = (const struct clk_hw *[]){
2605 + &nss_noc_clk_src.hw },
2606 .num_parents = 1,
2607 .flags = CLK_SET_RATE_PARENT,
2608 .ops = &clk_branch2_ops,
2609 @@ -2953,9 +2880,8 @@ static struct clk_branch gcc_nss_ce_apb_
2610 .enable_mask = BIT(0),
2611 .hw.init = &(struct clk_init_data){
2612 .name = "gcc_nss_ce_apb_clk",
2613 - .parent_names = (const char *[]){
2614 - "nss_ce_clk_src"
2615 - },
2616 + .parent_hws = (const struct clk_hw *[]){
2617 + &nss_ce_clk_src.clkr.hw },
2618 .num_parents = 1,
2619 .flags = CLK_SET_RATE_PARENT,
2620 .ops = &clk_branch2_ops,
2621 @@ -2970,9 +2896,8 @@ static struct clk_branch gcc_nss_ce_axi_
2622 .enable_mask = BIT(0),
2623 .hw.init = &(struct clk_init_data){
2624 .name = "gcc_nss_ce_axi_clk",
2625 - .parent_names = (const char *[]){
2626 - "nss_ce_clk_src"
2627 - },
2628 + .parent_hws = (const struct clk_hw *[]){
2629 + &nss_ce_clk_src.clkr.hw },
2630 .num_parents = 1,
2631 .flags = CLK_SET_RATE_PARENT,
2632 .ops = &clk_branch2_ops,
2633 @@ -2987,9 +2912,8 @@ static struct clk_branch gcc_nss_cfg_clk
2634 .enable_mask = BIT(0),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "gcc_nss_cfg_clk",
2637 - .parent_names = (const char *[]){
2638 - "pcnoc_clk_src"
2639 - },
2640 + .parent_hws = (const struct clk_hw *[]){
2641 + &pcnoc_clk_src.hw },
2642 .num_parents = 1,
2643 .flags = CLK_SET_RATE_PARENT,
2644 .ops = &clk_branch2_ops,
2645 @@ -3004,9 +2928,8 @@ static struct clk_branch gcc_nss_crypto_
2646 .enable_mask = BIT(0),
2647 .hw.init = &(struct clk_init_data){
2648 .name = "gcc_nss_crypto_clk",
2649 - .parent_names = (const char *[]){
2650 - "nss_crypto_clk_src"
2651 - },
2652 + .parent_hws = (const struct clk_hw *[]){
2653 + &nss_crypto_clk_src.clkr.hw },
2654 .num_parents = 1,
2655 .flags = CLK_SET_RATE_PARENT,
2656 .ops = &clk_branch2_ops,
2657 @@ -3021,9 +2944,8 @@ static struct clk_branch gcc_nss_csr_clk
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data){
2660 .name = "gcc_nss_csr_clk",
2661 - .parent_names = (const char *[]){
2662 - "nss_ce_clk_src"
2663 - },
2664 + .parent_hws = (const struct clk_hw *[]){
2665 + &nss_ce_clk_src.clkr.hw },
2666 .num_parents = 1,
2667 .flags = CLK_SET_RATE_PARENT,
2668 .ops = &clk_branch2_ops,
2669 @@ -3038,9 +2960,8 @@ static struct clk_branch gcc_nss_edma_cf
2670 .enable_mask = BIT(0),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "gcc_nss_edma_cfg_clk",
2673 - .parent_names = (const char *[]){
2674 - "nss_ppe_clk_src"
2675 - },
2676 + .parent_hws = (const struct clk_hw *[]){
2677 + &nss_ppe_clk_src.clkr.hw },
2678 .num_parents = 1,
2679 .flags = CLK_SET_RATE_PARENT,
2680 .ops = &clk_branch2_ops,
2681 @@ -3055,9 +2976,8 @@ static struct clk_branch gcc_nss_edma_cl
2682 .enable_mask = BIT(0),
2683 .hw.init = &(struct clk_init_data){
2684 .name = "gcc_nss_edma_clk",
2685 - .parent_names = (const char *[]){
2686 - "nss_ppe_clk_src"
2687 - },
2688 + .parent_hws = (const struct clk_hw *[]){
2689 + &nss_ppe_clk_src.clkr.hw },
2690 .num_parents = 1,
2691 .flags = CLK_SET_RATE_PARENT,
2692 .ops = &clk_branch2_ops,
2693 @@ -3072,9 +2992,8 @@ static struct clk_branch gcc_nss_imem_cl
2694 .enable_mask = BIT(0),
2695 .hw.init = &(struct clk_init_data){
2696 .name = "gcc_nss_imem_clk",
2697 - .parent_names = (const char *[]){
2698 - "nss_imem_clk_src"
2699 - },
2700 + .parent_hws = (const struct clk_hw *[]){
2701 + &nss_imem_clk_src.clkr.hw },
2702 .num_parents = 1,
2703 .flags = CLK_SET_RATE_PARENT,
2704 .ops = &clk_branch2_ops,
2705 @@ -3089,9 +3008,8 @@ static struct clk_branch gcc_nss_noc_clk
2706 .enable_mask = BIT(0),
2707 .hw.init = &(struct clk_init_data){
2708 .name = "gcc_nss_noc_clk",
2709 - .parent_names = (const char *[]){
2710 - "nss_noc_clk_src"
2711 - },
2712 + .parent_hws = (const struct clk_hw *[]){
2713 + &nss_noc_clk_src.hw },
2714 .num_parents = 1,
2715 .flags = CLK_SET_RATE_PARENT,
2716 .ops = &clk_branch2_ops,
2717 @@ -3106,9 +3024,8 @@ static struct clk_branch gcc_nss_ppe_btq
2718 .enable_mask = BIT(0),
2719 .hw.init = &(struct clk_init_data){
2720 .name = "gcc_nss_ppe_btq_clk",
2721 - .parent_names = (const char *[]){
2722 - "nss_ppe_clk_src"
2723 - },
2724 + .parent_hws = (const struct clk_hw *[]){
2725 + &nss_ppe_clk_src.clkr.hw },
2726 .num_parents = 1,
2727 .flags = CLK_SET_RATE_PARENT,
2728 .ops = &clk_branch2_ops,
2729 @@ -3123,9 +3040,8 @@ static struct clk_branch gcc_nss_ppe_cfg
2730 .enable_mask = BIT(0),
2731 .hw.init = &(struct clk_init_data){
2732 .name = "gcc_nss_ppe_cfg_clk",
2733 - .parent_names = (const char *[]){
2734 - "nss_ppe_clk_src"
2735 - },
2736 + .parent_hws = (const struct clk_hw *[]){
2737 + &nss_ppe_clk_src.clkr.hw },
2738 .num_parents = 1,
2739 .flags = CLK_SET_RATE_PARENT,
2740 .ops = &clk_branch2_ops,
2741 @@ -3140,9 +3056,8 @@ static struct clk_branch gcc_nss_ppe_clk
2742 .enable_mask = BIT(0),
2743 .hw.init = &(struct clk_init_data){
2744 .name = "gcc_nss_ppe_clk",
2745 - .parent_names = (const char *[]){
2746 - "nss_ppe_clk_src"
2747 - },
2748 + .parent_hws = (const struct clk_hw *[]){
2749 + &nss_ppe_clk_src.clkr.hw },
2750 .num_parents = 1,
2751 .flags = CLK_SET_RATE_PARENT,
2752 .ops = &clk_branch2_ops,
2753 @@ -3157,9 +3072,8 @@ static struct clk_branch gcc_nss_ppe_ipe
2754 .enable_mask = BIT(0),
2755 .hw.init = &(struct clk_init_data){
2756 .name = "gcc_nss_ppe_ipe_clk",
2757 - .parent_names = (const char *[]){
2758 - "nss_ppe_clk_src"
2759 - },
2760 + .parent_hws = (const struct clk_hw *[]){
2761 + &nss_ppe_clk_src.clkr.hw },
2762 .num_parents = 1,
2763 .flags = CLK_SET_RATE_PARENT,
2764 .ops = &clk_branch2_ops,
2765 @@ -3174,9 +3088,8 @@ static struct clk_branch gcc_nss_ptp_ref
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data){
2768 .name = "gcc_nss_ptp_ref_clk",
2769 - .parent_names = (const char *[]){
2770 - "nss_ppe_cdiv_clk_src"
2771 - },
2772 + .parent_hws = (const struct clk_hw *[]){
2773 + &nss_ppe_cdiv_clk_src.hw },
2774 .num_parents = 1,
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2777 @@ -3192,9 +3105,8 @@ static struct clk_branch gcc_crypto_ppe_
2778 .enable_mask = BIT(0),
2779 .hw.init = &(struct clk_init_data){
2780 .name = "gcc_crypto_ppe_clk",
2781 - .parent_names = (const char *[]){
2782 - "nss_ppe_clk_src"
2783 - },
2784 + .parent_hws = (const struct clk_hw *[]){
2785 + &nss_ppe_clk_src.clkr.hw },
2786 .num_parents = 1,
2787 .flags = CLK_SET_RATE_PARENT,
2788 .ops = &clk_branch2_ops,
2789 @@ -3209,9 +3121,8 @@ static struct clk_branch gcc_nssnoc_ce_a
2790 .enable_mask = BIT(0),
2791 .hw.init = &(struct clk_init_data){
2792 .name = "gcc_nssnoc_ce_apb_clk",
2793 - .parent_names = (const char *[]){
2794 - "nss_ce_clk_src"
2795 - },
2796 + .parent_hws = (const struct clk_hw *[]){
2797 + &nss_ce_clk_src.clkr.hw },
2798 .num_parents = 1,
2799 .flags = CLK_SET_RATE_PARENT,
2800 .ops = &clk_branch2_ops,
2801 @@ -3226,9 +3137,8 @@ static struct clk_branch gcc_nssnoc_ce_a
2802 .enable_mask = BIT(0),
2803 .hw.init = &(struct clk_init_data){
2804 .name = "gcc_nssnoc_ce_axi_clk",
2805 - .parent_names = (const char *[]){
2806 - "nss_ce_clk_src"
2807 - },
2808 + .parent_hws = (const struct clk_hw *[]){
2809 + &nss_ce_clk_src.clkr.hw },
2810 .num_parents = 1,
2811 .flags = CLK_SET_RATE_PARENT,
2812 .ops = &clk_branch2_ops,
2813 @@ -3243,9 +3153,8 @@ static struct clk_branch gcc_nssnoc_cryp
2814 .enable_mask = BIT(0),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "gcc_nssnoc_crypto_clk",
2817 - .parent_names = (const char *[]){
2818 - "nss_crypto_clk_src"
2819 - },
2820 + .parent_hws = (const struct clk_hw *[]){
2821 + &nss_crypto_clk_src.clkr.hw },
2822 .num_parents = 1,
2823 .flags = CLK_SET_RATE_PARENT,
2824 .ops = &clk_branch2_ops,
2825 @@ -3260,9 +3169,8 @@ static struct clk_branch gcc_nssnoc_ppe_
2826 .enable_mask = BIT(0),
2827 .hw.init = &(struct clk_init_data){
2828 .name = "gcc_nssnoc_ppe_cfg_clk",
2829 - .parent_names = (const char *[]){
2830 - "nss_ppe_clk_src"
2831 - },
2832 + .parent_hws = (const struct clk_hw *[]){
2833 + &nss_ppe_clk_src.clkr.hw },
2834 .num_parents = 1,
2835 .flags = CLK_SET_RATE_PARENT,
2836 .ops = &clk_branch2_ops,
2837 @@ -3277,9 +3185,8 @@ static struct clk_branch gcc_nssnoc_ppe_
2838 .enable_mask = BIT(0),
2839 .hw.init = &(struct clk_init_data){
2840 .name = "gcc_nssnoc_ppe_clk",
2841 - .parent_names = (const char *[]){
2842 - "nss_ppe_clk_src"
2843 - },
2844 + .parent_hws = (const struct clk_hw *[]){
2845 + &nss_ppe_clk_src.clkr.hw },
2846 .num_parents = 1,
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_branch2_ops,
2849 @@ -3294,9 +3201,8 @@ static struct clk_branch gcc_nssnoc_qosg
2850 .enable_mask = BIT(0),
2851 .hw.init = &(struct clk_init_data){
2852 .name = "gcc_nssnoc_qosgen_ref_clk",
2853 - .parent_names = (const char *[]){
2854 - "gcc_xo_clk_src"
2855 - },
2856 + .parent_hws = (const struct clk_hw *[]){
2857 + &gcc_xo_clk_src.clkr.hw },
2858 .num_parents = 1,
2859 .flags = CLK_SET_RATE_PARENT,
2860 .ops = &clk_branch2_ops,
2861 @@ -3311,9 +3217,8 @@ static struct clk_branch gcc_nssnoc_snoc
2862 .enable_mask = BIT(0),
2863 .hw.init = &(struct clk_init_data){
2864 .name = "gcc_nssnoc_snoc_clk",
2865 - .parent_names = (const char *[]){
2866 - "system_noc_clk_src"
2867 - },
2868 + .parent_hws = (const struct clk_hw *[]){
2869 + &system_noc_clk_src.hw },
2870 .num_parents = 1,
2871 .flags = CLK_SET_RATE_PARENT,
2872 .ops = &clk_branch2_ops,
2873 @@ -3328,9 +3233,8 @@ static struct clk_branch gcc_nssnoc_time
2874 .enable_mask = BIT(0),
2875 .hw.init = &(struct clk_init_data){
2876 .name = "gcc_nssnoc_timeout_ref_clk",
2877 - .parent_names = (const char *[]){
2878 - "gcc_xo_div4_clk_src"
2879 - },
2880 + .parent_hws = (const struct clk_hw *[]){
2881 + &gcc_xo_div4_clk_src.hw },
2882 .num_parents = 1,
2883 .flags = CLK_SET_RATE_PARENT,
2884 .ops = &clk_branch2_ops,
2885 @@ -3345,9 +3249,8 @@ static struct clk_branch gcc_nssnoc_ubi0
2886 .enable_mask = BIT(0),
2887 .hw.init = &(struct clk_init_data){
2888 .name = "gcc_nssnoc_ubi0_ahb_clk",
2889 - .parent_names = (const char *[]){
2890 - "nss_ce_clk_src"
2891 - },
2892 + .parent_hws = (const struct clk_hw *[]){
2893 + &nss_ce_clk_src.clkr.hw },
2894 .num_parents = 1,
2895 .flags = CLK_SET_RATE_PARENT,
2896 .ops = &clk_branch2_ops,
2897 @@ -3362,9 +3265,8 @@ static struct clk_branch gcc_nssnoc_ubi1
2898 .enable_mask = BIT(0),
2899 .hw.init = &(struct clk_init_data){
2900 .name = "gcc_nssnoc_ubi1_ahb_clk",
2901 - .parent_names = (const char *[]){
2902 - "nss_ce_clk_src"
2903 - },
2904 + .parent_hws = (const struct clk_hw *[]){
2905 + &nss_ce_clk_src.clkr.hw },
2906 .num_parents = 1,
2907 .flags = CLK_SET_RATE_PARENT,
2908 .ops = &clk_branch2_ops,
2909 @@ -3380,9 +3282,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
2910 .enable_mask = BIT(0),
2911 .hw.init = &(struct clk_init_data){
2912 .name = "gcc_ubi0_ahb_clk",
2913 - .parent_names = (const char *[]){
2914 - "nss_ce_clk_src"
2915 - },
2916 + .parent_hws = (const struct clk_hw *[]){
2917 + &nss_ce_clk_src.clkr.hw },
2918 .num_parents = 1,
2919 .flags = CLK_SET_RATE_PARENT,
2920 .ops = &clk_branch2_ops,
2921 @@ -3398,9 +3299,8 @@ static struct clk_branch gcc_ubi0_axi_cl
2922 .enable_mask = BIT(0),
2923 .hw.init = &(struct clk_init_data){
2924 .name = "gcc_ubi0_axi_clk",
2925 - .parent_names = (const char *[]){
2926 - "nss_noc_clk_src"
2927 - },
2928 + .parent_hws = (const struct clk_hw *[]){
2929 + &nss_noc_clk_src.hw },
2930 .num_parents = 1,
2931 .flags = CLK_SET_RATE_PARENT,
2932 .ops = &clk_branch2_ops,
2933 @@ -3416,9 +3316,8 @@ static struct clk_branch gcc_ubi0_nc_axi
2934 .enable_mask = BIT(0),
2935 .hw.init = &(struct clk_init_data){
2936 .name = "gcc_ubi0_nc_axi_clk",
2937 - .parent_names = (const char *[]){
2938 - "nss_noc_clk_src"
2939 - },
2940 + .parent_hws = (const struct clk_hw *[]){
2941 + &nss_noc_clk_src.hw },
2942 .num_parents = 1,
2943 .flags = CLK_SET_RATE_PARENT,
2944 .ops = &clk_branch2_ops,
2945 @@ -3434,9 +3333,8 @@ static struct clk_branch gcc_ubi0_core_c
2946 .enable_mask = BIT(0),
2947 .hw.init = &(struct clk_init_data){
2948 .name = "gcc_ubi0_core_clk",
2949 - .parent_names = (const char *[]){
2950 - "nss_ubi0_div_clk_src"
2951 - },
2952 + .parent_hws = (const struct clk_hw *[]){
2953 + &nss_ubi0_div_clk_src.clkr.hw },
2954 .num_parents = 1,
2955 .flags = CLK_SET_RATE_PARENT,
2956 .ops = &clk_branch2_ops,
2957 @@ -3452,9 +3350,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
2958 .enable_mask = BIT(0),
2959 .hw.init = &(struct clk_init_data){
2960 .name = "gcc_ubi0_mpt_clk",
2961 - .parent_names = (const char *[]){
2962 - "ubi_mpt_clk_src"
2963 - },
2964 + .parent_hws = (const struct clk_hw *[]){
2965 + &ubi_mpt_clk_src.clkr.hw },
2966 .num_parents = 1,
2967 .flags = CLK_SET_RATE_PARENT,
2968 .ops = &clk_branch2_ops,
2969 @@ -3470,9 +3367,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
2970 .enable_mask = BIT(0),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "gcc_ubi1_ahb_clk",
2973 - .parent_names = (const char *[]){
2974 - "nss_ce_clk_src"
2975 - },
2976 + .parent_hws = (const struct clk_hw *[]){
2977 + &nss_ce_clk_src.clkr.hw },
2978 .num_parents = 1,
2979 .flags = CLK_SET_RATE_PARENT,
2980 .ops = &clk_branch2_ops,
2981 @@ -3488,9 +3384,8 @@ static struct clk_branch gcc_ubi1_axi_cl
2982 .enable_mask = BIT(0),
2983 .hw.init = &(struct clk_init_data){
2984 .name = "gcc_ubi1_axi_clk",
2985 - .parent_names = (const char *[]){
2986 - "nss_noc_clk_src"
2987 - },
2988 + .parent_hws = (const struct clk_hw *[]){
2989 + &nss_noc_clk_src.hw },
2990 .num_parents = 1,
2991 .flags = CLK_SET_RATE_PARENT,
2992 .ops = &clk_branch2_ops,
2993 @@ -3506,9 +3401,8 @@ static struct clk_branch gcc_ubi1_nc_axi
2994 .enable_mask = BIT(0),
2995 .hw.init = &(struct clk_init_data){
2996 .name = "gcc_ubi1_nc_axi_clk",
2997 - .parent_names = (const char *[]){
2998 - "nss_noc_clk_src"
2999 - },
3000 + .parent_hws = (const struct clk_hw *[]){
3001 + &nss_noc_clk_src.hw },
3002 .num_parents = 1,
3003 .flags = CLK_SET_RATE_PARENT,
3004 .ops = &clk_branch2_ops,
3005 @@ -3524,9 +3418,8 @@ static struct clk_branch gcc_ubi1_core_c
3006 .enable_mask = BIT(0),
3007 .hw.init = &(struct clk_init_data){
3008 .name = "gcc_ubi1_core_clk",
3009 - .parent_names = (const char *[]){
3010 - "nss_ubi1_div_clk_src"
3011 - },
3012 + .parent_hws = (const struct clk_hw *[]){
3013 + &nss_ubi1_div_clk_src.clkr.hw },
3014 .num_parents = 1,
3015 .flags = CLK_SET_RATE_PARENT,
3016 .ops = &clk_branch2_ops,
3017 @@ -3542,9 +3435,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
3018 .enable_mask = BIT(0),
3019 .hw.init = &(struct clk_init_data){
3020 .name = "gcc_ubi1_mpt_clk",
3021 - .parent_names = (const char *[]){
3022 - "ubi_mpt_clk_src"
3023 - },
3024 + .parent_hws = (const struct clk_hw *[]){
3025 + &ubi_mpt_clk_src.clkr.hw },
3026 .num_parents = 1,
3027 .flags = CLK_SET_RATE_PARENT,
3028 .ops = &clk_branch2_ops,
3029 @@ -3559,9 +3451,8 @@ static struct clk_branch gcc_cmn_12gpll_
3030 .enable_mask = BIT(0),
3031 .hw.init = &(struct clk_init_data){
3032 .name = "gcc_cmn_12gpll_ahb_clk",
3033 - .parent_names = (const char *[]){
3034 - "pcnoc_clk_src"
3035 - },
3036 + .parent_hws = (const struct clk_hw *[]){
3037 + &pcnoc_clk_src.hw },
3038 .num_parents = 1,
3039 .flags = CLK_SET_RATE_PARENT,
3040 .ops = &clk_branch2_ops,
3041 @@ -3576,9 +3467,8 @@ static struct clk_branch gcc_cmn_12gpll_
3042 .enable_mask = BIT(0),
3043 .hw.init = &(struct clk_init_data){
3044 .name = "gcc_cmn_12gpll_sys_clk",
3045 - .parent_names = (const char *[]){
3046 - "gcc_xo_clk_src"
3047 - },
3048 + .parent_hws = (const struct clk_hw *[]){
3049 + &gcc_xo_clk_src.clkr.hw },
3050 .num_parents = 1,
3051 .flags = CLK_SET_RATE_PARENT,
3052 .ops = &clk_branch2_ops,
3053 @@ -3593,9 +3483,8 @@ static struct clk_branch gcc_mdio_ahb_cl
3054 .enable_mask = BIT(0),
3055 .hw.init = &(struct clk_init_data){
3056 .name = "gcc_mdio_ahb_clk",
3057 - .parent_names = (const char *[]){
3058 - "pcnoc_clk_src"
3059 - },
3060 + .parent_hws = (const struct clk_hw *[]){
3061 + &pcnoc_clk_src.hw },
3062 .num_parents = 1,
3063 .flags = CLK_SET_RATE_PARENT,
3064 .ops = &clk_branch2_ops,
3065 @@ -3610,9 +3499,8 @@ static struct clk_branch gcc_uniphy0_ahb
3066 .enable_mask = BIT(0),
3067 .hw.init = &(struct clk_init_data){
3068 .name = "gcc_uniphy0_ahb_clk",
3069 - .parent_names = (const char *[]){
3070 - "pcnoc_clk_src"
3071 - },
3072 + .parent_hws = (const struct clk_hw *[]){
3073 + &pcnoc_clk_src.hw },
3074 .num_parents = 1,
3075 .flags = CLK_SET_RATE_PARENT,
3076 .ops = &clk_branch2_ops,
3077 @@ -3627,9 +3515,8 @@ static struct clk_branch gcc_uniphy0_sys
3078 .enable_mask = BIT(0),
3079 .hw.init = &(struct clk_init_data){
3080 .name = "gcc_uniphy0_sys_clk",
3081 - .parent_names = (const char *[]){
3082 - "gcc_xo_clk_src"
3083 - },
3084 + .parent_hws = (const struct clk_hw *[]){
3085 + &gcc_xo_clk_src.clkr.hw },
3086 .num_parents = 1,
3087 .flags = CLK_SET_RATE_PARENT,
3088 .ops = &clk_branch2_ops,
3089 @@ -3644,9 +3531,8 @@ static struct clk_branch gcc_uniphy1_ahb
3090 .enable_mask = BIT(0),
3091 .hw.init = &(struct clk_init_data){
3092 .name = "gcc_uniphy1_ahb_clk",
3093 - .parent_names = (const char *[]){
3094 - "pcnoc_clk_src"
3095 - },
3096 + .parent_hws = (const struct clk_hw *[]){
3097 + &pcnoc_clk_src.hw },
3098 .num_parents = 1,
3099 .flags = CLK_SET_RATE_PARENT,
3100 .ops = &clk_branch2_ops,
3101 @@ -3661,9 +3547,8 @@ static struct clk_branch gcc_uniphy1_sys
3102 .enable_mask = BIT(0),
3103 .hw.init = &(struct clk_init_data){
3104 .name = "gcc_uniphy1_sys_clk",
3105 - .parent_names = (const char *[]){
3106 - "gcc_xo_clk_src"
3107 - },
3108 + .parent_hws = (const struct clk_hw *[]){
3109 + &gcc_xo_clk_src.clkr.hw },
3110 .num_parents = 1,
3111 .flags = CLK_SET_RATE_PARENT,
3112 .ops = &clk_branch2_ops,
3113 @@ -3678,9 +3563,8 @@ static struct clk_branch gcc_uniphy2_ahb
3114 .enable_mask = BIT(0),
3115 .hw.init = &(struct clk_init_data){
3116 .name = "gcc_uniphy2_ahb_clk",
3117 - .parent_names = (const char *[]){
3118 - "pcnoc_clk_src"
3119 - },
3120 + .parent_hws = (const struct clk_hw *[]){
3121 + &pcnoc_clk_src.hw },
3122 .num_parents = 1,
3123 .flags = CLK_SET_RATE_PARENT,
3124 .ops = &clk_branch2_ops,
3125 @@ -3695,9 +3579,8 @@ static struct clk_branch gcc_uniphy2_sys
3126 .enable_mask = BIT(0),
3127 .hw.init = &(struct clk_init_data){
3128 .name = "gcc_uniphy2_sys_clk",
3129 - .parent_names = (const char *[]){
3130 - "gcc_xo_clk_src"
3131 - },
3132 + .parent_hws = (const struct clk_hw *[]){
3133 + &gcc_xo_clk_src.clkr.hw },
3134 .num_parents = 1,
3135 .flags = CLK_SET_RATE_PARENT,
3136 .ops = &clk_branch2_ops,
3137 @@ -3712,9 +3595,8 @@ static struct clk_branch gcc_nss_port1_r
3138 .enable_mask = BIT(0),
3139 .hw.init = &(struct clk_init_data){
3140 .name = "gcc_nss_port1_rx_clk",
3141 - .parent_names = (const char *[]){
3142 - "nss_port1_rx_div_clk_src"
3143 - },
3144 + .parent_hws = (const struct clk_hw *[]){
3145 + &nss_port1_rx_div_clk_src.clkr.hw },
3146 .num_parents = 1,
3147 .flags = CLK_SET_RATE_PARENT,
3148 .ops = &clk_branch2_ops,
3149 @@ -3729,9 +3611,8 @@ static struct clk_branch gcc_nss_port1_t
3150 .enable_mask = BIT(0),
3151 .hw.init = &(struct clk_init_data){
3152 .name = "gcc_nss_port1_tx_clk",
3153 - .parent_names = (const char *[]){
3154 - "nss_port1_tx_div_clk_src"
3155 - },
3156 + .parent_hws = (const struct clk_hw *[]){
3157 + &nss_port1_tx_div_clk_src.clkr.hw },
3158 .num_parents = 1,
3159 .flags = CLK_SET_RATE_PARENT,
3160 .ops = &clk_branch2_ops,
3161 @@ -3746,9 +3627,8 @@ static struct clk_branch gcc_nss_port2_r
3162 .enable_mask = BIT(0),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "gcc_nss_port2_rx_clk",
3165 - .parent_names = (const char *[]){
3166 - "nss_port2_rx_div_clk_src"
3167 - },
3168 + .parent_hws = (const struct clk_hw *[]){
3169 + &nss_port2_rx_div_clk_src.clkr.hw },
3170 .num_parents = 1,
3171 .flags = CLK_SET_RATE_PARENT,
3172 .ops = &clk_branch2_ops,
3173 @@ -3763,9 +3643,8 @@ static struct clk_branch gcc_nss_port2_t
3174 .enable_mask = BIT(0),
3175 .hw.init = &(struct clk_init_data){
3176 .name = "gcc_nss_port2_tx_clk",
3177 - .parent_names = (const char *[]){
3178 - "nss_port2_tx_div_clk_src"
3179 - },
3180 + .parent_hws = (const struct clk_hw *[]){
3181 + &nss_port2_tx_div_clk_src.clkr.hw },
3182 .num_parents = 1,
3183 .flags = CLK_SET_RATE_PARENT,
3184 .ops = &clk_branch2_ops,
3185 @@ -3780,9 +3659,8 @@ static struct clk_branch gcc_nss_port3_r
3186 .enable_mask = BIT(0),
3187 .hw.init = &(struct clk_init_data){
3188 .name = "gcc_nss_port3_rx_clk",
3189 - .parent_names = (const char *[]){
3190 - "nss_port3_rx_div_clk_src"
3191 - },
3192 + .parent_hws = (const struct clk_hw *[]){
3193 + &nss_port3_rx_div_clk_src.clkr.hw },
3194 .num_parents = 1,
3195 .flags = CLK_SET_RATE_PARENT,
3196 .ops = &clk_branch2_ops,
3197 @@ -3797,9 +3675,8 @@ static struct clk_branch gcc_nss_port3_t
3198 .enable_mask = BIT(0),
3199 .hw.init = &(struct clk_init_data){
3200 .name = "gcc_nss_port3_tx_clk",
3201 - .parent_names = (const char *[]){
3202 - "nss_port3_tx_div_clk_src"
3203 - },
3204 + .parent_hws = (const struct clk_hw *[]){
3205 + &nss_port3_tx_div_clk_src.clkr.hw },
3206 .num_parents = 1,
3207 .flags = CLK_SET_RATE_PARENT,
3208 .ops = &clk_branch2_ops,
3209 @@ -3814,9 +3691,8 @@ static struct clk_branch gcc_nss_port4_r
3210 .enable_mask = BIT(0),
3211 .hw.init = &(struct clk_init_data){
3212 .name = "gcc_nss_port4_rx_clk",
3213 - .parent_names = (const char *[]){
3214 - "nss_port4_rx_div_clk_src"
3215 - },
3216 + .parent_hws = (const struct clk_hw *[]){
3217 + &nss_port4_rx_div_clk_src.clkr.hw },
3218 .num_parents = 1,
3219 .flags = CLK_SET_RATE_PARENT,
3220 .ops = &clk_branch2_ops,
3221 @@ -3831,9 +3707,8 @@ static struct clk_branch gcc_nss_port4_t
3222 .enable_mask = BIT(0),
3223 .hw.init = &(struct clk_init_data){
3224 .name = "gcc_nss_port4_tx_clk",
3225 - .parent_names = (const char *[]){
3226 - "nss_port4_tx_div_clk_src"
3227 - },
3228 + .parent_hws = (const struct clk_hw *[]){
3229 + &nss_port4_tx_div_clk_src.clkr.hw },
3230 .num_parents = 1,
3231 .flags = CLK_SET_RATE_PARENT,
3232 .ops = &clk_branch2_ops,
3233 @@ -3848,9 +3723,8 @@ static struct clk_branch gcc_nss_port5_r
3234 .enable_mask = BIT(0),
3235 .hw.init = &(struct clk_init_data){
3236 .name = "gcc_nss_port5_rx_clk",
3237 - .parent_names = (const char *[]){
3238 - "nss_port5_rx_div_clk_src"
3239 - },
3240 + .parent_hws = (const struct clk_hw *[]){
3241 + &nss_port5_rx_div_clk_src.clkr.hw },
3242 .num_parents = 1,
3243 .flags = CLK_SET_RATE_PARENT,
3244 .ops = &clk_branch2_ops,
3245 @@ -3865,9 +3739,8 @@ static struct clk_branch gcc_nss_port5_t
3246 .enable_mask = BIT(0),
3247 .hw.init = &(struct clk_init_data){
3248 .name = "gcc_nss_port5_tx_clk",
3249 - .parent_names = (const char *[]){
3250 - "nss_port5_tx_div_clk_src"
3251 - },
3252 + .parent_hws = (const struct clk_hw *[]){
3253 + &nss_port5_tx_div_clk_src.clkr.hw },
3254 .num_parents = 1,
3255 .flags = CLK_SET_RATE_PARENT,
3256 .ops = &clk_branch2_ops,
3257 @@ -3882,9 +3755,8 @@ static struct clk_branch gcc_nss_port6_r
3258 .enable_mask = BIT(0),
3259 .hw.init = &(struct clk_init_data){
3260 .name = "gcc_nss_port6_rx_clk",
3261 - .parent_names = (const char *[]){
3262 - "nss_port6_rx_div_clk_src"
3263 - },
3264 + .parent_hws = (const struct clk_hw *[]){
3265 + &nss_port6_rx_div_clk_src.clkr.hw },
3266 .num_parents = 1,
3267 .flags = CLK_SET_RATE_PARENT,
3268 .ops = &clk_branch2_ops,
3269 @@ -3899,9 +3771,8 @@ static struct clk_branch gcc_nss_port6_t
3270 .enable_mask = BIT(0),
3271 .hw.init = &(struct clk_init_data){
3272 .name = "gcc_nss_port6_tx_clk",
3273 - .parent_names = (const char *[]){
3274 - "nss_port6_tx_div_clk_src"
3275 - },
3276 + .parent_hws = (const struct clk_hw *[]){
3277 + &nss_port6_tx_div_clk_src.clkr.hw },
3278 .num_parents = 1,
3279 .flags = CLK_SET_RATE_PARENT,
3280 .ops = &clk_branch2_ops,
3281 @@ -3916,9 +3787,8 @@ static struct clk_branch gcc_port1_mac_c
3282 .enable_mask = BIT(0),
3283 .hw.init = &(struct clk_init_data){
3284 .name = "gcc_port1_mac_clk",
3285 - .parent_names = (const char *[]){
3286 - "nss_ppe_clk_src"
3287 - },
3288 + .parent_hws = (const struct clk_hw *[]){
3289 + &nss_ppe_clk_src.clkr.hw },
3290 .num_parents = 1,
3291 .flags = CLK_SET_RATE_PARENT,
3292 .ops = &clk_branch2_ops,
3293 @@ -3933,9 +3803,8 @@ static struct clk_branch gcc_port2_mac_c
3294 .enable_mask = BIT(0),
3295 .hw.init = &(struct clk_init_data){
3296 .name = "gcc_port2_mac_clk",
3297 - .parent_names = (const char *[]){
3298 - "nss_ppe_clk_src"
3299 - },
3300 + .parent_hws = (const struct clk_hw *[]){
3301 + &nss_ppe_clk_src.clkr.hw },
3302 .num_parents = 1,
3303 .flags = CLK_SET_RATE_PARENT,
3304 .ops = &clk_branch2_ops,
3305 @@ -3950,9 +3819,8 @@ static struct clk_branch gcc_port3_mac_c
3306 .enable_mask = BIT(0),
3307 .hw.init = &(struct clk_init_data){
3308 .name = "gcc_port3_mac_clk",
3309 - .parent_names = (const char *[]){
3310 - "nss_ppe_clk_src"
3311 - },
3312 + .parent_hws = (const struct clk_hw *[]){
3313 + &nss_ppe_clk_src.clkr.hw },
3314 .num_parents = 1,
3315 .flags = CLK_SET_RATE_PARENT,
3316 .ops = &clk_branch2_ops,
3317 @@ -3967,9 +3835,8 @@ static struct clk_branch gcc_port4_mac_c
3318 .enable_mask = BIT(0),
3319 .hw.init = &(struct clk_init_data){
3320 .name = "gcc_port4_mac_clk",
3321 - .parent_names = (const char *[]){
3322 - "nss_ppe_clk_src"
3323 - },
3324 + .parent_hws = (const struct clk_hw *[]){
3325 + &nss_ppe_clk_src.clkr.hw },
3326 .num_parents = 1,
3327 .flags = CLK_SET_RATE_PARENT,
3328 .ops = &clk_branch2_ops,
3329 @@ -3984,9 +3851,8 @@ static struct clk_branch gcc_port5_mac_c
3330 .enable_mask = BIT(0),
3331 .hw.init = &(struct clk_init_data){
3332 .name = "gcc_port5_mac_clk",
3333 - .parent_names = (const char *[]){
3334 - "nss_ppe_clk_src"
3335 - },
3336 + .parent_hws = (const struct clk_hw *[]){
3337 + &nss_ppe_clk_src.clkr.hw },
3338 .num_parents = 1,
3339 .flags = CLK_SET_RATE_PARENT,
3340 .ops = &clk_branch2_ops,
3341 @@ -4001,9 +3867,8 @@ static struct clk_branch gcc_port6_mac_c
3342 .enable_mask = BIT(0),
3343 .hw.init = &(struct clk_init_data){
3344 .name = "gcc_port6_mac_clk",
3345 - .parent_names = (const char *[]){
3346 - "nss_ppe_clk_src"
3347 - },
3348 + .parent_hws = (const struct clk_hw *[]){
3349 + &nss_ppe_clk_src.clkr.hw },
3350 .num_parents = 1,
3351 .flags = CLK_SET_RATE_PARENT,
3352 .ops = &clk_branch2_ops,
3353 @@ -4018,9 +3883,8 @@ static struct clk_branch gcc_uniphy0_por
3354 .enable_mask = BIT(0),
3355 .hw.init = &(struct clk_init_data){
3356 .name = "gcc_uniphy0_port1_rx_clk",
3357 - .parent_names = (const char *[]){
3358 - "nss_port1_rx_div_clk_src"
3359 - },
3360 + .parent_hws = (const struct clk_hw *[]){
3361 + &nss_port1_rx_div_clk_src.clkr.hw },
3362 .num_parents = 1,
3363 .flags = CLK_SET_RATE_PARENT,
3364 .ops = &clk_branch2_ops,
3365 @@ -4035,9 +3899,8 @@ static struct clk_branch gcc_uniphy0_por
3366 .enable_mask = BIT(0),
3367 .hw.init = &(struct clk_init_data){
3368 .name = "gcc_uniphy0_port1_tx_clk",
3369 - .parent_names = (const char *[]){
3370 - "nss_port1_tx_div_clk_src"
3371 - },
3372 + .parent_hws = (const struct clk_hw *[]){
3373 + &nss_port1_tx_div_clk_src.clkr.hw },
3374 .num_parents = 1,
3375 .flags = CLK_SET_RATE_PARENT,
3376 .ops = &clk_branch2_ops,
3377 @@ -4052,9 +3915,8 @@ static struct clk_branch gcc_uniphy0_por
3378 .enable_mask = BIT(0),
3379 .hw.init = &(struct clk_init_data){
3380 .name = "gcc_uniphy0_port2_rx_clk",
3381 - .parent_names = (const char *[]){
3382 - "nss_port2_rx_div_clk_src"
3383 - },
3384 + .parent_hws = (const struct clk_hw *[]){
3385 + &nss_port2_rx_div_clk_src.clkr.hw },
3386 .num_parents = 1,
3387 .flags = CLK_SET_RATE_PARENT,
3388 .ops = &clk_branch2_ops,
3389 @@ -4069,9 +3931,8 @@ static struct clk_branch gcc_uniphy0_por
3390 .enable_mask = BIT(0),
3391 .hw.init = &(struct clk_init_data){
3392 .name = "gcc_uniphy0_port2_tx_clk",
3393 - .parent_names = (const char *[]){
3394 - "nss_port2_tx_div_clk_src"
3395 - },
3396 + .parent_hws = (const struct clk_hw *[]){
3397 + &nss_port2_tx_div_clk_src.clkr.hw },
3398 .num_parents = 1,
3399 .flags = CLK_SET_RATE_PARENT,
3400 .ops = &clk_branch2_ops,
3401 @@ -4086,9 +3947,8 @@ static struct clk_branch gcc_uniphy0_por
3402 .enable_mask = BIT(0),
3403 .hw.init = &(struct clk_init_data){
3404 .name = "gcc_uniphy0_port3_rx_clk",
3405 - .parent_names = (const char *[]){
3406 - "nss_port3_rx_div_clk_src"
3407 - },
3408 + .parent_hws = (const struct clk_hw *[]){
3409 + &nss_port3_rx_div_clk_src.clkr.hw },
3410 .num_parents = 1,
3411 .flags = CLK_SET_RATE_PARENT,
3412 .ops = &clk_branch2_ops,
3413 @@ -4103,9 +3963,8 @@ static struct clk_branch gcc_uniphy0_por
3414 .enable_mask = BIT(0),
3415 .hw.init = &(struct clk_init_data){
3416 .name = "gcc_uniphy0_port3_tx_clk",
3417 - .parent_names = (const char *[]){
3418 - "nss_port3_tx_div_clk_src"
3419 - },
3420 + .parent_hws = (const struct clk_hw *[]){
3421 + &nss_port3_tx_div_clk_src.clkr.hw },
3422 .num_parents = 1,
3423 .flags = CLK_SET_RATE_PARENT,
3424 .ops = &clk_branch2_ops,
3425 @@ -4120,9 +3979,8 @@ static struct clk_branch gcc_uniphy0_por
3426 .enable_mask = BIT(0),
3427 .hw.init = &(struct clk_init_data){
3428 .name = "gcc_uniphy0_port4_rx_clk",
3429 - .parent_names = (const char *[]){
3430 - "nss_port4_rx_div_clk_src"
3431 - },
3432 + .parent_hws = (const struct clk_hw *[]){
3433 + &nss_port4_rx_div_clk_src.clkr.hw },
3434 .num_parents = 1,
3435 .flags = CLK_SET_RATE_PARENT,
3436 .ops = &clk_branch2_ops,
3437 @@ -4137,9 +3995,8 @@ static struct clk_branch gcc_uniphy0_por
3438 .enable_mask = BIT(0),
3439 .hw.init = &(struct clk_init_data){
3440 .name = "gcc_uniphy0_port4_tx_clk",
3441 - .parent_names = (const char *[]){
3442 - "nss_port4_tx_div_clk_src"
3443 - },
3444 + .parent_hws = (const struct clk_hw *[]){
3445 + &nss_port4_tx_div_clk_src.clkr.hw },
3446 .num_parents = 1,
3447 .flags = CLK_SET_RATE_PARENT,
3448 .ops = &clk_branch2_ops,
3449 @@ -4154,9 +4011,8 @@ static struct clk_branch gcc_uniphy0_por
3450 .enable_mask = BIT(0),
3451 .hw.init = &(struct clk_init_data){
3452 .name = "gcc_uniphy0_port5_rx_clk",
3453 - .parent_names = (const char *[]){
3454 - "nss_port5_rx_div_clk_src"
3455 - },
3456 + .parent_hws = (const struct clk_hw *[]){
3457 + &nss_port5_rx_div_clk_src.clkr.hw },
3458 .num_parents = 1,
3459 .flags = CLK_SET_RATE_PARENT,
3460 .ops = &clk_branch2_ops,
3461 @@ -4171,9 +4027,8 @@ static struct clk_branch gcc_uniphy0_por
3462 .enable_mask = BIT(0),
3463 .hw.init = &(struct clk_init_data){
3464 .name = "gcc_uniphy0_port5_tx_clk",
3465 - .parent_names = (const char *[]){
3466 - "nss_port5_tx_div_clk_src"
3467 - },
3468 + .parent_hws = (const struct clk_hw *[]){
3469 + &nss_port5_tx_div_clk_src.clkr.hw },
3470 .num_parents = 1,
3471 .flags = CLK_SET_RATE_PARENT,
3472 .ops = &clk_branch2_ops,
3473 @@ -4188,9 +4043,8 @@ static struct clk_branch gcc_uniphy1_por
3474 .enable_mask = BIT(0),
3475 .hw.init = &(struct clk_init_data){
3476 .name = "gcc_uniphy1_port5_rx_clk",
3477 - .parent_names = (const char *[]){
3478 - "nss_port5_rx_div_clk_src"
3479 - },
3480 + .parent_hws = (const struct clk_hw *[]){
3481 + &nss_port5_rx_div_clk_src.clkr.hw },
3482 .num_parents = 1,
3483 .flags = CLK_SET_RATE_PARENT,
3484 .ops = &clk_branch2_ops,
3485 @@ -4205,9 +4059,8 @@ static struct clk_branch gcc_uniphy1_por
3486 .enable_mask = BIT(0),
3487 .hw.init = &(struct clk_init_data){
3488 .name = "gcc_uniphy1_port5_tx_clk",
3489 - .parent_names = (const char *[]){
3490 - "nss_port5_tx_div_clk_src"
3491 - },
3492 + .parent_hws = (const struct clk_hw *[]){
3493 + &nss_port5_tx_div_clk_src.clkr.hw },
3494 .num_parents = 1,
3495 .flags = CLK_SET_RATE_PARENT,
3496 .ops = &clk_branch2_ops,
3497 @@ -4222,9 +4075,8 @@ static struct clk_branch gcc_uniphy2_por
3498 .enable_mask = BIT(0),
3499 .hw.init = &(struct clk_init_data){
3500 .name = "gcc_uniphy2_port6_rx_clk",
3501 - .parent_names = (const char *[]){
3502 - "nss_port6_rx_div_clk_src"
3503 - },
3504 + .parent_hws = (const struct clk_hw *[]){
3505 + &nss_port6_rx_div_clk_src.clkr.hw },
3506 .num_parents = 1,
3507 .flags = CLK_SET_RATE_PARENT,
3508 .ops = &clk_branch2_ops,
3509 @@ -4239,9 +4091,8 @@ static struct clk_branch gcc_uniphy2_por
3510 .enable_mask = BIT(0),
3511 .hw.init = &(struct clk_init_data){
3512 .name = "gcc_uniphy2_port6_tx_clk",
3513 - .parent_names = (const char *[]){
3514 - "nss_port6_tx_div_clk_src"
3515 - },
3516 + .parent_hws = (const struct clk_hw *[]){
3517 + &nss_port6_tx_div_clk_src.clkr.hw },
3518 .num_parents = 1,
3519 .flags = CLK_SET_RATE_PARENT,
3520 .ops = &clk_branch2_ops,
3521 @@ -4257,9 +4108,8 @@ static struct clk_branch gcc_crypto_ahb_
3522 .enable_mask = BIT(0),
3523 .hw.init = &(struct clk_init_data){
3524 .name = "gcc_crypto_ahb_clk",
3525 - .parent_names = (const char *[]){
3526 - "pcnoc_clk_src"
3527 - },
3528 + .parent_hws = (const struct clk_hw *[]){
3529 + &pcnoc_clk_src.hw },
3530 .num_parents = 1,
3531 .flags = CLK_SET_RATE_PARENT,
3532 .ops = &clk_branch2_ops,
3533 @@ -4275,9 +4125,8 @@ static struct clk_branch gcc_crypto_axi_
3534 .enable_mask = BIT(1),
3535 .hw.init = &(struct clk_init_data){
3536 .name = "gcc_crypto_axi_clk",
3537 - .parent_names = (const char *[]){
3538 - "pcnoc_clk_src"
3539 - },
3540 + .parent_hws = (const struct clk_hw *[]){
3541 + &pcnoc_clk_src.hw },
3542 .num_parents = 1,
3543 .flags = CLK_SET_RATE_PARENT,
3544 .ops = &clk_branch2_ops,
3545 @@ -4293,9 +4142,8 @@ static struct clk_branch gcc_crypto_clk
3546 .enable_mask = BIT(2),
3547 .hw.init = &(struct clk_init_data){
3548 .name = "gcc_crypto_clk",
3549 - .parent_names = (const char *[]){
3550 - "crypto_clk_src"
3551 - },
3552 + .parent_hws = (const struct clk_hw *[]){
3553 + &crypto_clk_src.clkr.hw },
3554 .num_parents = 1,
3555 .flags = CLK_SET_RATE_PARENT,
3556 .ops = &clk_branch2_ops,
3557 @@ -4310,9 +4158,8 @@ static struct clk_branch gcc_gp1_clk = {
3558 .enable_mask = BIT(0),
3559 .hw.init = &(struct clk_init_data){
3560 .name = "gcc_gp1_clk",
3561 - .parent_names = (const char *[]){
3562 - "gp1_clk_src"
3563 - },
3564 + .parent_hws = (const struct clk_hw *[]){
3565 + &gp1_clk_src.clkr.hw },
3566 .num_parents = 1,
3567 .flags = CLK_SET_RATE_PARENT,
3568 .ops = &clk_branch2_ops,
3569 @@ -4327,9 +4174,8 @@ static struct clk_branch gcc_gp2_clk = {
3570 .enable_mask = BIT(0),
3571 .hw.init = &(struct clk_init_data){
3572 .name = "gcc_gp2_clk",
3573 - .parent_names = (const char *[]){
3574 - "gp2_clk_src"
3575 - },
3576 + .parent_hws = (const struct clk_hw *[]){
3577 + &gp2_clk_src.clkr.hw },
3578 .num_parents = 1,
3579 .flags = CLK_SET_RATE_PARENT,
3580 .ops = &clk_branch2_ops,
3581 @@ -4344,9 +4190,8 @@ static struct clk_branch gcc_gp3_clk = {
3582 .enable_mask = BIT(0),
3583 .hw.init = &(struct clk_init_data){
3584 .name = "gcc_gp3_clk",
3585 - .parent_names = (const char *[]){
3586 - "gp3_clk_src"
3587 - },
3588 + .parent_hws = (const struct clk_hw *[]){
3589 + &gp3_clk_src.clkr.hw },
3590 .num_parents = 1,
3591 .flags = CLK_SET_RATE_PARENT,
3592 .ops = &clk_branch2_ops,
3593 @@ -4368,7 +4213,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
3594 .clkr.hw.init = &(struct clk_init_data){
3595 .name = "pcie0_rchng_clk_src",
3596 .parent_data = gcc_xo_gpll0,
3597 - .num_parents = 2,
3598 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3599 .ops = &clk_rcg2_ops,
3600 },
3601 };
OpenWrt Source Repository