target/linux/qualcommax/patches-6.1/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch

   1 From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Thu, 3 Nov 2022 14:49:44 +0100
   4 Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
   5  conf
   6
   7 Rework nss_port5/6 to use the new multiple configuration implementation
   8 and correctly fix the clocks for these port under some corner case.
   9
  10 This is particularly relevant for device that have 2.5G or 10G port
  11 connected to port5 or port 6 on ipq8074. As the parent are shared
  12 across multiple port it may be required to select the correct
  13 configuration to accomplish the desired clock. Without this patch such
  14 port doesn't work in some specific ethernet speed as the clock will be
  15 set to the wrong frequency as we just select the first configuration for
  16 the related frequency instead of selecting the best one.
  17
  18 Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
  19 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  20 ---
  21  drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
  22  1 file changed, 48 insertions(+), 16 deletions(-)
  23
  24 --- a/drivers/clk/qcom/gcc-ipq8074.c
  25 +++ b/drivers/clk/qcom/gcc-ipq8074.c
  26 @@ -1682,13 +1682,21 @@ static struct clk_regmap_div nss_port4_t
  27         },
  28  };
  29
  30 +static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
  31 +       C(P_UNIPHY1_RX, 12.5, 0, 0),
  32 +       C(P_UNIPHY0_RX, 5, 0, 0),
  33 +};
  34 +
  35 +static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
  36 +       C(P_UNIPHY1_RX, 2.5, 0, 0),
  37 +       C(P_UNIPHY0_RX, 1, 0, 0),
  38 +};
  39 +
  40  static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
  41         F(19200000, P_XO, 1, 0, 0),
  42 -       F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
  43 -       F(25000000, P_UNIPHY0_RX, 5, 0, 0),
  44 +       FM(25000000, ftbl_nss_port5_rx_clk_src_25),
  45         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
  46 -       F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
  47 -       F(125000000, P_UNIPHY0_RX, 1, 0, 0),
  48 +       FM(125000000, ftbl_nss_port5_rx_clk_src_125),
  49         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
  50         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
  51         { }
  52 @@ -1744,13 +1752,21 @@ static struct clk_regmap_div nss_port5_r
  53         },
  54  };
  55
  56 +static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
  57 +       C(P_UNIPHY1_TX, 12.5, 0, 0),
  58 +       C(P_UNIPHY0_TX, 5, 0, 0),
  59 +};
  60 +
  61 +static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
  62 +       C(P_UNIPHY1_TX, 2.5, 0, 0),
  63 +       C(P_UNIPHY0_TX, 1, 0, 0),
  64 +};
  65 +
  66  static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
  67         F(19200000, P_XO, 1, 0, 0),
  68 -       F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
  69 -       F(25000000, P_UNIPHY0_TX, 5, 0, 0),
  70 +       FM(25000000, ftbl_nss_port5_tx_clk_src_25),
  71         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
  72 -       F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
  73 -       F(125000000, P_UNIPHY0_TX, 1, 0, 0),
  74 +       FM(125000000, ftbl_nss_port5_tx_clk_src_125),
  75         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
  76         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
  77         { }
  78 @@ -1806,13 +1822,21 @@ static struct clk_regmap_div nss_port5_t
  79         },
  80  };
  81
  82 +static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
  83 +       C(P_UNIPHY2_RX, 5, 0, 0),
  84 +       C(P_UNIPHY2_RX, 12.5, 0, 0),
  85 +};
  86 +
  87 +static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
  88 +       C(P_UNIPHY2_RX, 1, 0, 0),
  89 +       C(P_UNIPHY2_RX, 2.5, 0, 0),
  90 +};
  91 +
  92  static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
  93         F(19200000, P_XO, 1, 0, 0),
  94 -       F(25000000, P_UNIPHY2_RX, 5, 0, 0),
  95 -       F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
  96 +       FM(25000000, ftbl_nss_port6_rx_clk_src_25),
  97         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
  98 -       F(125000000, P_UNIPHY2_RX, 1, 0, 0),
  99 -       F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
 100 +       FM(125000000, ftbl_nss_port6_rx_clk_src_125),
 101         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
 102         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
 103         { }
 104 @@ -1863,13 +1887,21 @@ static struct clk_regmap_div nss_port6_r
 105         },
 106  };
 107
 108 +static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
 109 +       C(P_UNIPHY2_TX, 5, 0, 0),
 110 +       C(P_UNIPHY2_TX, 12.5, 0, 0),
 111 +};
 112 +
 113 +static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
 114 +       C(P_UNIPHY2_TX, 1, 0, 0),
 115 +       C(P_UNIPHY2_TX, 2.5, 0, 0),
 116 +};
 117 +
 118  static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
 119         F(19200000, P_XO, 1, 0, 0),
 120 -       F(25000000, P_UNIPHY2_TX, 5, 0, 0),
 121 -       F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
 122 +       FM(25000000, ftbl_nss_port6_tx_clk_src_25),
 123         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
 124 -       F(125000000, P_UNIPHY2_TX, 1, 0, 0),
 125 -       F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
 126 +       FM(125000000, ftbl_nss_port6_tx_clk_src_125),
 127         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
 128         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
 129         { }