5ece7567f354d4e033db5cb5e15210451808a61e
[openwrt/openwrt.git] / target / linux / ramips / dts / ZBT-WE1226.dts
1 /dts-v1/;
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4
5 #include "mt7628an.dtsi"
6
7 / {
8 compatible = "zbtlink,zbt-we1226", "mediatek,mt7628an-soc";
9 model = "Zbtlink ZBT-WE1226";
10
11 chosen {
12 bootargs = "console=ttyS0,115200";
13 };
14
15 memory@0 {
16 device_type = "memory";
17 reg = <0x0 0x4000000>;
18 };
19
20 gpio-keys-polled {
21 compatible = "gpio-keys-polled";
22 #address-cells = <1>;
23 #size-cells = <0>;
24 poll-interval = <20>;
25
26 reset {
27 label = "reset";
28 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
29 linux,code = <KEY_RESTART>;
30 };
31 };
32
33 gpio-leds {
34 compatible = "gpio-leds";
35
36 wan {
37 label = "zbt-we1226:green:wan";
38 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
39 };
40
41 lan1 {
42 label = "zbt-we1226:green:lan1";
43 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
44 };
45
46 lan2 {
47 label = "zbt-we1226:green:lan2";
48 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
49 };
50
51 wlan {
52 label = "zbt-we1226:green:wlan";
53 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
54 };
55 };
56 };
57
58 &pinctrl {
59 state_default: pinctrl0 {
60 gpio {
61 ralink,group = "p0led_an", "p1led_an", "p4led_an", "wdt", "wled_an";
62 ralink,function = "gpio";
63 };
64 };
65 };
66
67 &spi0 {
68 status = "okay";
69
70 m25p80@0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "jedec,spi-nor";
74 reg = <0>;
75 spi-max-frequency = <10000000>;
76 m25p,chunked-io = <32>;
77
78 partition@0 {
79 label = "u-boot";
80 reg = <0x0 0x30000>;
81 read-only;
82 };
83
84 partition@30000 {
85 label = "u-boot-env";
86 reg = <0x30000 0x10000>;
87 read-only;
88 };
89
90 factory: partition@40000 {
91 label = "factory";
92 reg = <0x40000 0x10000>;
93 read-only;
94 };
95
96 partition@50000 {
97 label = "firmware";
98 reg = <0x50000 0x7b0000>;
99 };
100 };
101 };
102
103 &wmac {
104 status = "okay";
105 ralink,mtd-eeprom = <&factory 0x4>;
106 };
107
108 &ethernet {
109 mtd-mac-address = <&factory 0x2e>;
110 mediatek,portmap = "llllw";
111 };