ramips: fix dtc warnings
[openwrt/openwrt.git] / target / linux / ramips / dts / ZBT-WE1226.dts
1 /dts-v1/;
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4
5 #include "mt7628an.dtsi"
6
7 / {
8 compatible = "zbtlink,zbt-we1226", "mediatek,mt7628an-soc";
9 model = "Zbtlink ZBT-WE1226";
10
11 aliases {
12 led-status = &led_wlan;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200";
17 };
18
19 memory@0 {
20 device_type = "memory";
21 reg = <0x0 0x4000000>;
22 };
23
24 gpio-keys-polled {
25 compatible = "gpio-keys-polled";
26 poll-interval = <20>;
27
28 reset {
29 label = "reset";
30 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RESTART>;
32 };
33 };
34
35 gpio-leds {
36 compatible = "gpio-leds";
37
38 wan {
39 label = "zbt-we1226:green:wan";
40 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
41 };
42
43 lan1 {
44 label = "zbt-we1226:green:lan1";
45 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
46 };
47
48 lan2 {
49 label = "zbt-we1226:green:lan2";
50 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
51 };
52
53 led_wlan: wlan {
54 label = "zbt-we1226:green:wlan";
55 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
56 };
57 };
58 };
59
60 &pinctrl {
61 state_default: pinctrl0 {
62 gpio {
63 ralink,group = "p0led_an", "p1led_an", "p4led_an", "wdt", "wled_an";
64 ralink,function = "gpio";
65 };
66 };
67 };
68
69 &spi0 {
70 status = "okay";
71
72 m25p80@0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "jedec,spi-nor";
76 reg = <0>;
77 spi-max-frequency = <10000000>;
78 m25p,chunked-io = <32>;
79
80 partition@0 {
81 label = "u-boot";
82 reg = <0x0 0x30000>;
83 read-only;
84 };
85
86 partition@30000 {
87 label = "u-boot-env";
88 reg = <0x30000 0x10000>;
89 read-only;
90 };
91
92 factory: partition@40000 {
93 label = "factory";
94 reg = <0x40000 0x10000>;
95 read-only;
96 };
97
98 partition@50000 {
99 label = "firmware";
100 reg = <0x50000 0x7b0000>;
101 };
102 };
103 };
104
105 &wmac {
106 status = "okay";
107 ralink,mtd-eeprom = <&factory 0x4>;
108 };
109
110 &ethernet {
111 mtd-mac-address = <&factory 0x2e>;
112 mediatek,portmap = "llllw";
113 };