ramips: fix size-cells for spi nodes
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a.dtsi
1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,mtk7620a-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24KEc";
9 };
10 };
11
12 chosen {
13 bootargs = "console=ttyS0,57600";
14 };
15
16 cpuintc: cpuintc@0 {
17 #address-cells = <0>;
18 #interrupt-cells = <1>;
19 interrupt-controller;
20 compatible = "mti,cpu-interrupt-controller";
21 };
22
23 palmbus@10000000 {
24 compatible = "palmbus";
25 reg = <0x10000000 0x200000>;
26 ranges = <0x0 0x10000000 0x1FFFFF>;
27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 sysc@0 {
32 compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc";
33 reg = <0x0 0x100>;
34 };
35
36 timer@100 {
37 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
38 reg = <0x100 0x20>;
39
40 interrupt-parent = <&intc>;
41 interrupts = <1>;
42 };
43
44 watchdog@120 {
45 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
46 reg = <0x120 0x10>;
47
48 resets = <&rstctrl 8>;
49 reset-names = "wdt";
50
51 interrupt-parent = <&intc>;
52 interrupts = <1>;
53 };
54
55 intc: intc@200 {
56 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
57 reg = <0x200 0x100>;
58
59 resets = <&rstctrl 19>;
60 reset-names = "intc";
61
62 interrupt-controller;
63 #interrupt-cells = <1>;
64
65 interrupt-parent = <&cpuintc>;
66 interrupts = <2>;
67 };
68
69 memc@300 {
70 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
71 reg = <0x300 0x100>;
72
73 resets = <&rstctrl 20>;
74 reset-names = "mc";
75
76 interrupt-parent = <&intc>;
77 interrupts = <3>;
78 };
79
80 uart@500 {
81 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
82 reg = <0x500 0x100>;
83
84 resets = <&rstctrl 12>;
85 reset-names = "uart";
86
87 interrupt-parent = <&intc>;
88 interrupts = <5>;
89
90 reg-shift = <2>;
91
92 status = "disabled";
93 };
94
95 gpio0: gpio@600 {
96 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
97 reg = <0x600 0x34>;
98
99 resets = <&rstctrl 13>;
100 reset-names = "pio";
101
102 interrupt-parent = <&intc>;
103 interrupts = <6>;
104
105 gpio-controller;
106 #gpio-cells = <2>;
107
108 ralink,gpio-base = <0>;
109 ralink,num-gpios = <24>;
110 ralink,register-map = [ 00 04 08 0c
111 20 24 28 2c
112 30 34 ];
113 };
114
115 gpio1: gpio@638 {
116 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
117 reg = <0x638 0x24>;
118
119 interrupt-parent = <&intc>;
120 interrupts = <6>;
121
122 gpio-controller;
123 #gpio-cells = <2>;
124
125 ralink,gpio-base = <24>;
126 ralink,num-gpios = <16>;
127 ralink,register-map = [ 00 04 08 0c
128 10 14 18 1c
129 20 24 ];
130
131 status = "disabled";
132 };
133
134 gpio2: gpio@660 {
135 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
136 reg = <0x660 0x24>;
137
138 interrupt-parent = <&intc>;
139 interrupts = <6>;
140
141 gpio-controller;
142 #gpio-cells = <2>;
143
144 ralink,gpio-base = <40>;
145 ralink,num-gpios = <32>;
146 ralink,register-map = [ 00 04 08 0c
147 10 14 18 1c
148 20 24 ];
149
150 status = "disabled";
151 };
152
153 gpio3: gpio@688 {
154 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
155 reg = <0x688 0x24>;
156
157 interrupt-parent = <&intc>;
158 interrupts = <6>;
159
160 gpio-controller;
161 #gpio-cells = <2>;
162
163 ralink,gpio-base = <72>;
164 ralink,num-gpios = <1>;
165 ralink,register-map = [ 00 04 08 0c
166 10 14 18 1c
167 20 24 ];
168
169 status = "disabled";
170 };
171
172 i2c@900 {
173 compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c";
174 reg = <0x900 0x100>;
175
176 resets = <&rstctrl 16>;
177 reset-names = "i2c";
178
179 #address-cells = <1>;
180 #size-cells = <0>;
181
182 status = "disabled";
183
184 pinctrl-names = "default";
185 pinctrl-0 = <&i2c_pins>;
186 };
187
188 i2s@a00 {
189 compatible = "ralink,mt7620a-i2s";
190 reg = <0xa00 0x100>;
191
192 resets = <&rstctrl 17>;
193 reset-names = "i2s";
194
195 interrupt-parent = <&intc>;
196 interrupts = <10>;
197
198 dmas = <&gdma 4>,
199 <&gdma 5>;
200 dma-names = "tx", "rx";
201
202 status = "disabled";
203 };
204
205 spi@b00 {
206 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
207 reg = <0xb00 0x100>;
208
209 resets = <&rstctrl 18>;
210 reset-names = "spi";
211
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 status = "disabled";
216
217 pinctrl-names = "default";
218 pinctrl-0 = <&spi_pins>;
219 };
220
221 uartlite@c00 {
222 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
223 reg = <0xc00 0x100>;
224
225 resets = <&rstctrl 19>;
226 reset-names = "uartl";
227
228 interrupt-parent = <&intc>;
229 interrupts = <12>;
230
231 reg-shift = <2>;
232
233 pinctrl-names = "default";
234 pinctrl-0 = <&uartlite_pins>;
235 };
236
237 systick@d00 {
238 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
239 reg = <0xd00 0x10>;
240
241 resets = <&rstctrl 28>;
242 reset-names = "intc";
243
244 interrupt-parent = <&cpuintc>;
245 interrupts = <7>;
246 };
247
248 pcm@2000 {
249 compatible = "ralink,mt7620a-pcm";
250 reg = <0x2000 0x800>;
251
252 resets = <&rstctrl 11>;
253 reset-names = "pcm";
254
255 interrupt-parent = <&intc>;
256 interrupts = <4>;
257
258 status = "disabled";
259 };
260
261 gdma: gdma@2800 {
262 compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
263 reg = <0x2800 0x800>;
264
265 resets = <&rstctrl 14>;
266 reset-names = "dma";
267
268 interrupt-parent = <&intc>;
269 interrupts = <7>;
270
271 #dma-cells = <1>;
272 #dma-channels = <16>;
273 #dma-requests = <16>;
274
275 status = "disabled";
276 };
277 };
278
279 pinctrl {
280 compatible = "ralink,rt2880-pinmux";
281 pinctrl-names = "default";
282 pinctrl-0 = <&state_default>;
283
284 state_default: pinctrl0 {
285 };
286
287 pcm_i2s_pins: pcm_i2s {
288 pcm_i2s {
289 ralink,group = "uartf";
290 ralink,function = "pcm i2s";
291 };
292 };
293
294 uartf_gpio_pins: uartf_gpio {
295 uartf_gpio {
296 ralink,group = "uartf";
297 ralink,function = "gpio uartf";
298 };
299 };
300
301 spi_pins: spi {
302 spi {
303 ralink,group = "spi";
304 ralink,function = "spi";
305 };
306 };
307
308 i2c_pins: i2c {
309 i2c {
310 ralink,group = "i2c";
311 ralink,function = "i2c";
312 };
313 };
314
315 uartlite_pins: uartlite {
316 uart {
317 ralink,group = "uartlite";
318 ralink,function = "uartlite";
319 };
320 };
321
322 mdio_pins: mdio {
323 mdio {
324 ralink,group = "mdio";
325 ralink,function = "mdio";
326 };
327 };
328
329 ephy_pins: ephy {
330 ephy {
331 ralink,group = "ephy";
332 ralink,function = "ephy";
333 };
334 };
335
336 wled_pins: wled {
337 wled {
338 ralink,group = "wled";
339 ralink,function = "wled";
340 };
341 };
342
343 rgmii1_pins: rgmii1 {
344 rgmii1 {
345 ralink,group = "rgmii1";
346 ralink,function = "rgmii1";
347 };
348 };
349
350 rgmii2_pins: rgmii2 {
351 rgmii2 {
352 ralink,group = "rgmii2";
353 ralink,function = "rgmii2";
354 };
355 };
356
357 pcie_pins: pcie {
358 pcie {
359 ralink,group = "pcie";
360 ralink,function = "pcie rst";
361 };
362 };
363 };
364
365 rstctrl: rstctrl {
366 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
367 #reset-cells = <1>;
368 };
369
370 usbphy: usbphy {
371 compatible = "ralink,mt7620a-usbphy";
372 #phy-cells = <1>;
373
374 resets = <&rstctrl 22 &rstctrl 25>;
375 reset-names = "host", "device";
376 };
377
378 ethernet@10100000 {
379 compatible = "ralink,mt7620a-eth";
380 reg = <0x10100000 10000>;
381
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 interrupt-parent = <&cpuintc>;
386 interrupts = <5>;
387
388 resets = <&rstctrl 21 &rstctrl 23>;
389 reset-names = "fe", "esw";
390
391 port@4 {
392 compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
393 reg = <4>;
394
395 status = "disabled";
396 };
397
398 port@5 {
399 compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
400 reg = <5>;
401
402 status = "disabled";
403 };
404
405 mdio-bus {
406 #address-cells = <1>;
407 #size-cells = <0>;
408
409 status = "disabled";
410 };
411 };
412
413 gsw@10110000 {
414 compatible = "ralink,mt7620a-gsw";
415 reg = <0x10110000 8000>;
416
417 resets = <&rstctrl 23>;
418 reset-names = "esw";
419
420 interrupt-parent = <&intc>;
421 interrupts = <17>;
422 };
423
424 sdhci@10130000 {
425 compatible = "ralink,mt7620-sdhci";
426 reg = <0x10130000 4000>;
427
428 interrupt-parent = <&intc>;
429 interrupts = <14>;
430
431 status = "disabled";
432 };
433
434 ehci@101c0000 {
435 compatible = "ralink,rt3xxx-ehci";
436 reg = <0x101c0000 0x1000>;
437
438 interrupt-parent = <&intc>;
439 interrupts = <18>;
440
441 phys = <&usbphy 1>;
442 phy-names = "usb";
443
444 status = "disabled";
445 };
446
447 ohci@101c1000 {
448 compatible = "ralink,rt3xxx-ohci";
449 reg = <0x101c1000 0x1000>;
450
451 interrupt-parent = <&intc>;
452 interrupts = <18>;
453
454 phys = <&usbphy 1>;
455 phy-names = "usb";
456
457 status = "disabled";
458 };
459
460 pcie@10140000 {
461 compatible = "mediatek,mt7620-pci";
462 reg = <0x10140000 0x100
463 0x10142000 0x100>;
464
465 #address-cells = <3>;
466 #size-cells = <2>;
467
468 resets = <&rstctrl 26>;
469 reset-names = "pcie0";
470
471 interrupt-parent = <&cpuintc>;
472 interrupts = <4>;
473
474 pinctrl-names = "default";
475 pinctrl-0 = <&pcie_pins>;
476
477 device_type = "pci";
478
479 bus-range = <0 255>;
480 ranges = <
481 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
482 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
483 >;
484
485 status = "disabled";
486
487 pcie-bridge {
488 reg = <0x0000 0 0 0 0>;
489
490 #address-cells = <3>;
491 #size-cells = <2>;
492
493 device_type = "pci";
494 };
495 };
496
497 wmac@10180000 {
498 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
499 reg = <0x10180000 40000>;
500
501 interrupt-parent = <&cpuintc>;
502 interrupts = <6>;
503
504 ralink,eeprom = "soc_wmac.eeprom";
505 };
506 };