target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "head-weblink,hdrm200", "ralink,mt7620a-soc";
  10         model = "Head Weblink HDRM200";
  11
  12         aliases {
  13                 led-boot = &led_system;
  14                 led-failsafe = &led_system;
  15                 led-running = &led_system;
  16                 led-upgrade = &led_system;
  17         };
  18
  19         chosen {
  20                 bootargs = "console=ttyS1,57600";
  21         };
  22
  23         leds {
  24                 compatible = "gpio-leds";
  25
  26                 rssi {
  27                         label = "red:rssi";
  28                         gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
  29                 };
  30
  31                 led_system: system {
  32                         label = "green:system";
  33                         gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
  34                 };
  35
  36                 air {
  37                         label = "green:wifi";
  38                         gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  39                 };
  40         };
  41
  42         keys {
  43                 compatible = "gpio-keys";
  44
  45                 wps {
  46                         label = "wps";
  47                         gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  48                         linux,code = <KEY_WPS_BUTTON>;
  49                 };
  50
  51                 reset {
  52                         label = "reset";
  53                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  54                         linux,code = <KEY_RESTART>;
  55                 };
  56         };
  57 };
  58
  59 &spi0 {
  60         status = "okay";
  61
  62         flash@0 {
  63                 compatible = "jedec,spi-nor";
  64                 reg = <0>;
  65                 spi-max-frequency = <10000000>;
  66
  67                 partitions {
  68                         compatible = "fixed-partitions";
  69                         #address-cells = <1>;
  70                         #size-cells = <1>;
  71
  72                         partition@0 {
  73                                 label = "u-boot";
  74                                 reg = <0x0 0x30000>;
  75                                 read-only;
  76                         };
  77
  78                         partition@30000 {
  79                                 label = "u-boot-env";
  80                                 reg = <0x30000 0x10000>;
  81                                 read-only;
  82                         };
  83
  84                         partition@40000 {
  85                                 label = "factory";
  86                                 reg = <0x40000 0x10000>;
  87                                 read-only;
  88
  89                                 nvmem-layout {
  90                                         compatible = "fixed-layout";
  91                                         #address-cells = <1>;
  92                                         #size-cells = <1>;
  93
  94                                         eeprom_factory_0: eeprom@0 {
  95                                                 reg = <0x0 0x200>;
  96                                         };
  97
  98                                         eeprom_factory_8000: eeprom@8000 {
  99                                                 reg = <0x8000 0x200>;
 100                                         };
 101
 102                                         macaddr_factory_4: macaddr@4 {
 103                                                 reg = <0x4 0x6>;
 104                                         };
 105                                 };
 106                         };
 107
 108                         partition@50000 {
 109                                 compatible = "denx,uimage";
 110                                 label = "firmware";
 111                                 reg = <0x50000 0xfb0000>;
 112                         };
 113                 };
 114         };
 115 };
 116
 117 &gpio1 {
 118         status = "okay";
 119 };
 120
 121 &gpio3 {
 122         status = "okay";
 123 };
 124
 125 &sdhci {
 126         status = "okay";
 127 };
 128
 129 &ehci {
 130         status = "okay";
 131 };
 132
 133 &ohci {
 134         status = "okay";
 135 };
 136
 137 &ethernet {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
 140
 141         nvmem-cells = <&macaddr_factory_4>;
 142         nvmem-cell-names = "mac-address";
 143
 144         port@4 {
 145                 status = "okay";
 146                 phy-handle = <&phy4>;
 147                 phy-mode = "rgmii";
 148         };
 149
 150         port@5 {
 151                 status = "okay";
 152                 phy-handle = <&phy5>;
 153                 phy-mode = "rgmii";
 154         };
 155
 156         mdio-bus {
 157                 status = "okay";
 158
 159                 phy4: ethernet-phy@4 {
 160                         reg = <4>;
 161                         phy-mode = "rgmii";
 162                 };
 163
 164                 phy5: ethernet-phy@5 {
 165                         reg = <5>;
 166                         phy-mode = "rgmii";
 167                 };
 168         };
 169 };
 170
 171 &gsw {
 172         mediatek,port4-gmac;
 173         mediatek,ephy-base = /bits/ 8 <8>;
 174 };
 175
 176 &wmac {
 177         nvmem-cells = <&eeprom_factory_0>;
 178         nvmem-cell-names = "eeprom";
 179 };
 180
 181 &state_default {
 182         default {
 183                 groups = "i2c", "uartf", "pa", "spi refclk",
 184                                "wled";
 185                 function = "gpio";
 186         };
 187 };
 188
 189 &pcie {
 190         status = "okay";
 191 };
 192
 193 &pcie0 {
 194         wifi@0,0 {
 195                 compatible = "mediatek,mt76";
 196                 reg = <0x0000 0 0 0 0>;
 197                 nvmem-cells = <&eeprom_factory_8000>;
 198                 nvmem-cell-names = "eeprom";
 199                 ieee80211-freq-limit = <5000000 6000000>;
 200         };
 201 };
 202
 203 &uart {
 204         status = "okay";
 205 };