target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
  11         model = "LB-Link BL-W1200";
  12
  13         aliases {
  14                 led-boot = &led_wps;
  15                 led-failsafe = &led_wps;
  16                 led-upgrade = &led_wps;
  17         };
  18
  19         keys {
  20                 compatible = "gpio-keys";
  21
  22                 reset_wps {
  23                         label = "reset_wps";
  24                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  25                         linux,code = <KEY_RESTART>;
  26                 };
  27         };
  28
  29         leds {
  30                 compatible = "gpio-leds";
  31
  32                 led_wps: wps {
  33                         function = LED_FUNCTION_WPS;
  34                         color = <LED_COLOR_ID_GREEN>;
  35                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  36                 };
  37         };
  38 };
  39
  40 &gpio1 {
  41         status = "okay";
  42 };
  43
  44 &spi0 {
  45         status = "okay";
  46
  47         flash@0 {
  48                 compatible = "jedec,spi-nor";
  49                 reg = <0>;
  50                 spi-max-frequency = <50000000>;
  51
  52                 partitions {
  53                         compatible = "fixed-partitions";
  54                         #address-cells = <1>;
  55                         #size-cells = <1>;
  56
  57                         partition@0 {
  58                                 label = "u-boot";
  59                                 reg = <0x0 0x30000>;
  60                                 read-only;
  61                         };
  62
  63                         partition@30000 {
  64                                 label = "config";
  65                                 reg = <0x30000 0x10000>;
  66                                 read-only;
  67                         };
  68
  69                         partition@40000 {
  70                                 label = "factory";
  71                                 reg = <0x40000 0x10000>;
  72                                 read-only;
  73
  74                                 nvmem-layout {
  75                                         compatible = "fixed-layout";
  76                                         #address-cells = <1>;
  77                                         #size-cells = <1>;
  78
  79                                         eeprom_factory_0: eeprom@0 {
  80                                                 reg = <0x0 0x200>;
  81                                         };
  82
  83                                         eeprom_factory_8000: eeprom@8000 {
  84                                                 reg = <0x8000 0x200>;
  85                                         };
  86
  87                                         macaddr_factory_28: macaddr@28 {
  88                                                 reg = <0x28 0x6>;
  89                                         };
  90                                 };
  91                         };
  92
  93                         partition@50000 {
  94                                 compatible = "denx,uimage";
  95                                 label = "firmware";
  96                                 reg = <0x50000 0x7b0000>;
  97                         };
  98                 };
  99         };
 100 };
 101
 102 &state_default {
 103         gpio {
 104                 groups = "uartf", "spi refclk";
 105                 function = "gpio";
 106         };
 107 };
 108
 109 &ethernet {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&rgmii2_pins &mdio_pins>;
 112
 113         nvmem-cells = <&macaddr_factory_28>;
 114         nvmem-cell-names = "mac-address";
 115
 116         mediatek,portmap = "wllll";
 117
 118         port@5 {
 119                 status = "okay";
 120                 mediatek,fixed-link = <1000 1 1 1>;
 121                 phy-mode = "rgmii";
 122         };
 123
 124         mdio-bus {
 125                 status = "okay";
 126
 127                 ethernet-phy@0 {
 128                         reg = <0>;
 129                         phy-mode = "rgmii";
 130                 };
 131
 132                 ethernet-phy@1 {
 133                         reg = <1>;
 134                         phy-mode = "rgmii";
 135                 };
 136
 137                 ethernet-phy@2 {
 138                         reg = <2>;
 139                         phy-mode = "rgmii";
 140                 };
 141
 142                 ethernet-phy@3 {
 143                         reg = <3>;
 144                         phy-mode = "rgmii";
 145                 };
 146
 147                 ethernet-phy@4 {
 148                         reg = <4>;
 149                         phy-mode = "rgmii";
 150                 };
 151
 152                 ethernet-phy@1f {
 153                         reg = <0x1f>;
 154                         phy-mode = "rgmii";
 155                 };
 156         };
 157 };
 158
 159 &gsw {
 160         mediatek,ephy-base = /bits/ 8 <12>;
 161 };
 162
 163 &wmac {
 164         nvmem-cells = <&eeprom_factory_0>;
 165         nvmem-cell-names = "eeprom";
 166 };
 167
 168 &pcie {
 169         status = "okay";
 170 };
 171
 172 &pcie0 {
 173         wifi@0,0 {
 174                 compatible = "mediatek,mt76";
 175                 reg = <0x0000 0 0 0 0>;
 176                 ieee80211-freq-limit = <5000000 6000000>;
 177                 nvmem-cells = <&eeprom_factory_8000>;
 178                 nvmem-cell-names = "eeprom";
 179
 180                 led {
 181                         led-sources = <2>;
 182                         led-active-low;
 183                 };
 184         };
 185 };
 186
 187 &ehci {
 188         status = "okay";
 189 };
 190
 191 &ohci {
 192         status = "okay";
 193 };