63643927d51f078d9300a8f06aa432151508b38a
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_tplink_archer-c2-v1.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
8 model = "TP-Link Archer C2 v1";
9
10 aliases {
11 led-boot = &led_wps;
12 led-failsafe = &led_wps;
13 led-running = &led_wps;
14 led-upgrade = &led_wps;
15 };
16
17 chosen {
18 bootargs = "console=ttyS0,115200";
19 };
20
21 leds {
22 compatible = "gpio-leds";
23
24 lan {
25 label = "green:lan";
26 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
27 };
28
29 usb {
30 label = "green:usb";
31 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
32 trigger-sources = <&ohci_port1>, <&ehci_port1>;
33 linux,default-trigger = "usbport";
34 };
35
36 led_wps: wps {
37 label = "green:wps";
38 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
39 };
40
41 wan {
42 label = "green:wan";
43 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
44 };
45
46 wlan {
47 label = "green:wlan";
48 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
49 linux,default-trigger = "phy1tpt";
50 };
51 };
52
53 keys {
54 compatible = "gpio-keys";
55
56 reset_wps {
57 label = "reset_wps";
58 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_RESTART>;
60 };
61
62 rfkill {
63 label = "rfkill";
64 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
65 linux,code = <KEY_RFKILL>;
66 };
67 };
68
69 rtl8367rb {
70 compatible = "realtek,rtl8367b", "rtl8367b";
71 cpu_port = <6>;
72 realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
73 mii-bus = <&mdio0>;
74 };
75 };
76
77 &spi0 {
78 status = "okay";
79
80 flash@0 {
81 compatible = "jedec,spi-nor";
82 reg = <0>;
83 spi-max-frequency = <30000000>;
84
85 partitions {
86 compatible = "fixed-partitions";
87 #address-cells = <1>;
88 #size-cells = <1>;
89
90 partition@0 {
91 label = "u-boot";
92 reg = <0x0 0x20000>;
93 read-only;
94 };
95
96 partition@20000 {
97 compatible = "tplink,firmware";
98 label = "firmware";
99 reg = <0x20000 0x7a0000>;
100 };
101
102 partition@7c0000 {
103 label = "config";
104 reg = <0x7c0000 0x10000>;
105 read-only;
106 };
107
108 rom: partition@7d0000 {
109 label = "rom";
110 reg = <0x7d0000 0x10000>;
111 read-only;
112 };
113
114 partition@7e0000 {
115 label = "romfile";
116 reg = <0x7e0000 0x10000>;
117 read-only;
118 };
119
120 radio: partition@7f0000 {
121 label = "radio";
122 reg = <0x7f0000 0x10000>;
123 read-only;
124 };
125 };
126 };
127 };
128
129 &ethernet {
130 pinctrl-names = "default";
131 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
132
133 nvmem-cells = <&macaddr_rom_f100>;
134 nvmem-cell-names = "mac-address";
135
136 port@5 {
137 status = "okay";
138 mediatek,fixed-link = <1000 1 1 1>;
139 phy-mode = "rgmii";
140 };
141
142 mdio0: mdio-bus {
143 status = "okay";
144 };
145 };
146
147 &gpio1 {
148 status = "okay";
149 };
150
151 &gpio2 {
152 status = "okay";
153 };
154
155 &gpio3 {
156 status = "okay";
157 };
158
159 &state_default {
160 gpio {
161 groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
162 function = "gpio";
163 };
164 };
165
166 &wmac {
167 ralink,mtd-eeprom = <&radio 0x0>;
168 nvmem-cells = <&macaddr_rom_f100>;
169 nvmem-cell-names = "mac-address";
170 };
171
172 &ehci {
173 status = "okay";
174 };
175
176 &ohci {
177 status = "okay";
178 };
179
180 &pcie {
181 status = "okay";
182 };
183
184 &pcie0 {
185 mt76@0,0 {
186 reg = <0x0000 0 0 0 0>;
187 mediatek,mtd-eeprom = <&radio 0x8000>;
188 nvmem-cells = <&macaddr_rom_f100>;
189 nvmem-cell-names = "mac-address";
190 mac-address-increment = <(-1)>;
191 };
192 };
193
194 &rom {
195 compatible = "nvmem-cells";
196 #address-cells = <1>;
197 #size-cells = <1>;
198
199 macaddr_rom_f100: macaddr@f100 {
200 reg = <0xf100 0x6>;
201 };
202 };