ramips: use DT trigger for 2G WiFi on ASUS RT-AC51U
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_zte_q7.dts
1 /dts-v1/;
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "zte,q7", "ralink,mt7620a-soc";
10 model = "ZTE Q7";
11
12 aliases {
13 led-boot = &led_status_blue;
14 led-failsafe = &led_status_blue;
15 led-running = &led_status_blue;
16 led-upgrade = &led_status_blue;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 statred {
23 label = "zte-q7:red:status";
24 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
25 };
26
27 led_status_blue: statblue {
28 label = "zte-q7:blue:status";
29 gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
30 };
31 };
32
33 keys {
34 compatible = "gpio-keys";
35
36 reset {
37 label = "reset";
38 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
39 linux,code = <KEY_RESTART>;
40 };
41 };
42 };
43
44 &gpio0 {
45 status = "okay";
46 };
47
48 &gpio1 {
49 status = "okay";
50 };
51
52 &spi0 {
53 status = "okay";
54
55 flash@0 {
56 compatible = "jedec,spi-nor";
57 reg = <0>;
58 spi-max-frequency = <10000000>;
59
60 partitions {
61 compatible = "fixed-partitions";
62 #address-cells = <1>;
63 #size-cells = <1>;
64
65 partition@0 {
66 label = "u-boot";
67 reg = <0x0 0x30000>;
68 read-only;
69 };
70
71 partition@30000 {
72 label = "u-boot-env";
73 reg = <0x30000 0x10000>;
74 read-only;
75 };
76
77 factory: partition@40000 {
78 label = "factory";
79 reg = <0x40000 0x10000>;
80 read-only;
81 };
82
83 partition@50000 {
84 compatible = "denx,uimage";
85 label = "firmware";
86 reg = <0x50000 0x7b0000>;
87 };
88 };
89 };
90 };
91
92 &state_default {
93 gpio {
94 groups = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled";
95 function = "gpio";
96 };
97 };
98
99 &ethernet {
100 mtd-mac-address = <&factory 0x4>;
101
102 mediatek,portmap = "wllll";
103 };
104
105 &wmac {
106 ralink,mtd-eeprom = <&factory 0x0>;
107 };
108
109 &sdhci {
110 status = "okay";
111 };
112
113 &ehci {
114 status = "okay";
115 };
116
117 &ohci {
118 status = "okay";
119 };
120
121 &gsw {
122 mediatek,port4 = "ephy";
123 };