target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/mips-gic.h>
   4 #include <dt-bindings/clock/mt7621-clk.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         compatible = "mediatek,mt7621-soc";
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15
  16                 cpu@0 {
  17                         device_type = "cpu";
  18                         compatible = "mips,mips1004Kc";
  19                         reg = <0>;
  20                 };
  21
  22                 cpu@1 {
  23                         device_type = "cpu";
  24                         compatible = "mips,mips1004Kc";
  25                         reg = <1>;
  26                 };
  27         };
  28
  29         cpuintc: cpuintc {
  30                 #address-cells = <0>;
  31                 #interrupt-cells = <1>;
  32                 interrupt-controller;
  33                 compatible = "mti,cpu-interrupt-controller";
  34         };
  35
  36         aliases {
  37                 serial0 = &uartlite;
  38         };
  39
  40         chosen {
  41                 bootargs = "console=ttyS0,57600";
  42         };
  43
  44         pll: pll {
  45                 compatible = "mediatek,mt7621-pll", "syscon";
  46
  47                 #clock-cells = <1>;
  48                 clock-output-names = "cpu", "bus";
  49         };
  50
  51         sysclock: sysclock {
  52                 #clock-cells = <0>;
  53                 compatible = "fixed-clock";
  54
  55                 /* FIXME: there should be way to detect this */
  56                 clock-frequency = <50000000>;
  57         };
  58
  59         palmbus: palmbus@1E000000 {
  60                 compatible = "palmbus";
  61                 reg = <0x1E000000 0x100000>;
  62                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  63
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66
  67                 sysc: sysc@0 {
  68                         compatible = "mtk,mt7621-sysc";
  69                         reg = <0x0 0x100>;
  70                 };
  71
  72                 wdt: wdt@100 {
  73                         compatible = "mediatek,mt7621-wdt";
  74                         reg = <0x100 0x100>;
  75                 };
  76
  77                 gpio: gpio@600 {
  78                         #gpio-cells = <2>;
  79                         #interrupt-cells = <2>;
  80                         compatible = "mediatek,mt7621-gpio";
  81                         gpio-controller;
  82                         interrupt-controller;
  83                         reg = <0x600 0x100>;
  84                         interrupt-parent = <&gic>;
  85                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  86                 };
  87
  88                 i2c: i2c@900 {
  89                         compatible = "mediatek,mt7621-i2c";
  90                         reg = <0x900 0x100>;
  91
  92                         clocks = <&sysclock>;
  93
  94                         resets = <&rstctrl 16>;
  95                         reset-names = "i2c";
  96
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99
 100                         status = "disabled";
 101
 102                         pinctrl-names = "default";
 103                         pinctrl-0 = <&i2c_pins>;
 104                 };
 105
 106                 i2s: i2s@a00 {
 107                         compatible = "mediatek,mt7621-i2s";
 108                         reg = <0xa00 0x100>;
 109
 110                         clocks = <&sysclock>;
 111
 112                         resets = <&rstctrl 17>;
 113                         reset-names = "i2s";
 114
 115                         interrupt-parent = <&gic>;
 116                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 117
 118                         txdma-req = <2>;
 119                         rxdma-req = <3>;
 120
 121                         dmas = <&gdma 4>,
 122                                 <&gdma 6>;
 123                         dma-names = "tx", "rx";
 124
 125                         status = "disabled";
 126                 };
 127
 128                 systick: systick@500 {
 129                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 130                         reg = <0x500 0x10>;
 131
 132                         resets = <&rstctrl 28>;
 133                         reset-names = "intc";
 134
 135                         interrupt-parent = <&gic>;
 136                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 137                 };
 138
 139                 memc: memc@5000 {
 140                         compatible = "mtk,mt7621-memc";
 141                         reg = <0x5000 0x1000>;
 142                 };
 143
 144                 cpc: cpc@1fbf0000 {
 145                         compatible = "mtk,mt7621-cpc";
 146                         reg = <0x1fbf0000 0x8000>;
 147                 };
 148
 149                 mc: mc@1fbf8000 {
 150                         compatible = "mtk,mt7621-mc";
 151                         reg = <0x1fbf8000 0x8000>;
 152                 };
 153
 154                 uartlite: uartlite@c00 {
 155                         compatible = "ns16550a";
 156                         reg = <0xc00 0x100>;
 157
 158                         clock-frequency = <50000000>;
 159
 160                         interrupt-parent = <&gic>;
 161                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 162
 163                         reg-shift = <2>;
 164                         reg-io-width = <4>;
 165                         no-loopback-test;
 166                 };
 167
 168                 uartlite2: uartlite2@d00 {
 169                         compatible = "ns16550a";
 170                         reg = <0xd00 0x100>;
 171
 172                         clock-frequency = <50000000>;
 173
 174                         interrupt-parent = <&gic>;
 175                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 176
 177                         reg-shift = <2>;
 178                         reg-io-width = <4>;
 179
 180                         pinctrl-names = "default";
 181                         pinctrl-0 = <&uart2_pins>;
 182
 183                         status = "disabled";
 184                 };
 185
 186                 uartlite3: uartlite3@e00 {
 187                         compatible = "ns16550a";
 188                         reg = <0xe00 0x100>;
 189
 190                         clock-frequency = <50000000>;
 191
 192                         interrupt-parent = <&gic>;
 193                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 194
 195                         reg-shift = <2>;
 196                         reg-io-width = <4>;
 197
 198                         pinctrl-names = "default";
 199                         pinctrl-0 = <&uart3_pins>;
 200
 201                         status = "disabled";
 202                 };
 203
 204                 spi0: spi@b00 {
 205                         status = "disabled";
 206
 207                         compatible = "ralink,mt7621-spi";
 208                         reg = <0xb00 0x100>;
 209
 210                         clocks = <&pll MT7621_CLK_BUS>;
 211
 212                         resets = <&rstctrl 18>;
 213                         reset-names = "spi";
 214
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217
 218                         pinctrl-names = "default";
 219                         pinctrl-0 = <&spi_pins>;
 220                 };
 221
 222                 gdma: gdma@2800 {
 223                         compatible = "ralink,rt3883-gdma";
 224                         reg = <0x2800 0x800>;
 225
 226                         resets = <&rstctrl 14>;
 227                         reset-names = "dma";
 228
 229                         interrupt-parent = <&gic>;
 230                         interrupts = <0 13 4>;
 231
 232                         #dma-cells = <1>;
 233                         #dma-channels = <16>;
 234                         #dma-requests = <16>;
 235
 236                         status = "disabled";
 237                 };
 238
 239                 hsdma: hsdma@7000 {
 240                         compatible = "mediatek,mt7621-hsdma";
 241                         reg = <0x7000 0x1000>;
 242
 243                         resets = <&rstctrl 5>;
 244                         reset-names = "hsdma";
 245
 246                         interrupt-parent = <&gic>;
 247                         interrupts = <0 11 4>;
 248
 249                         #dma-cells = <1>;
 250                         #dma-channels = <1>;
 251                         #dma-requests = <1>;
 252
 253                         status = "disabled";
 254                 };
 255         };
 256
 257         pinctrl: pinctrl {
 258                 compatible = "ralink,rt2880-pinmux";
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&state_default>;
 261
 262                 state_default: pinctrl0 {
 263                 };
 264
 265                 i2c_pins: i2c_pins {
 266                         i2c_pins {
 267                                 groups = "i2c";
 268                                 function = "i2c";
 269                         };
 270                 };
 271
 272                 spi_pins: spi_pins {
 273                         spi_pins {
 274                                 groups = "spi";
 275                                 function = "spi";
 276                         };
 277                 };
 278
 279                 uart1_pins: uart1 {
 280                         uart1 {
 281                                 groups = "uart1";
 282                                 function = "uart1";
 283                         };
 284                 };
 285
 286                 uart2_pins: uart2 {
 287                         uart2 {
 288                                 groups = "uart2";
 289                                 function = "uart2";
 290                         };
 291                 };
 292
 293                 uart3_pins: uart3 {
 294                         uart3 {
 295                                 groups = "uart3";
 296                                 function = "uart3";
 297                         };
 298                 };
 299
 300                 rgmii1_pins: rgmii1 {
 301                         rgmii1 {
 302                                 groups = "rgmii1";
 303                                 function = "rgmii1";
 304                         };
 305                 };
 306
 307                 rgmii2_pins: rgmii2 {
 308                         rgmii2 {
 309                                 groups = "rgmii2";
 310                                 function = "rgmii2";
 311                         };
 312                 };
 313
 314                 mdio_pins: mdio {
 315                         mdio {
 316                                 groups = "mdio";
 317                                 function = "mdio";
 318                         };
 319                 };
 320
 321                 pcie_pins: pcie {
 322                         pcie {
 323                                 groups = "pcie";
 324                                 function = "gpio";
 325                         };
 326                 };
 327
 328                 nand_pins: nand {
 329                         spi-nand {
 330                                 groups = "spi";
 331                                 function = "nand1";
 332                         };
 333
 334                         sdhci-nand {
 335                                 groups = "sdhci";
 336                                 function = "nand2";
 337                         };
 338                 };
 339
 340                 sdhci_pins: sdhci {
 341                         sdhci {
 342                                 groups = "sdhci";
 343                                 function = "sdhci";
 344                         };
 345                 };
 346         };
 347
 348         rstctrl: rstctrl {
 349                 compatible = "ralink,rt2880-reset";
 350                 #reset-cells = <1>;
 351         };
 352
 353         clkctrl: clkctrl {
 354                 compatible = "ralink,rt2880-clock";
 355                 #clock-cells = <1>;
 356         };
 357
 358         sdhci: sdhci@1E130000 {
 359                 status = "disabled";
 360
 361                 compatible = "ralink,mt7620-sdhci";
 362                 reg = <0x1E130000 0x4000>;
 363
 364                 interrupt-parent = <&gic>;
 365                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 366
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&sdhci_pins>;
 369         };
 370
 371         xhci: xhci@1E1C0000 {
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 status = "okay";
 375
 376                 compatible = "mediatek,mt8173-xhci";
 377                 reg = <0x1e1c0000 0x1000
 378                        0x1e1d0700 0x0100>;
 379                 reg-names = "mac", "ippc";
 380
 381                 clocks = <&sysclock>;
 382                 clock-names = "sys_ck";
 383
 384                 interrupt-parent = <&gic>;
 385                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 386
 387                 /*
 388                  * Port 1 of both hubs is one usb slot and referenced here.
 389                  * The binding doesn't allow to address individual hubs.
 390                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 391                  */
 392                 xhci_ehci_port1: port@1 {
 393                         reg = <1>;
 394                         #trigger-source-cells = <0>;
 395                 };
 396
 397                 /*
 398                  * Only the second usb hub has a second port. That port serves
 399                  * ehci and ohci.
 400                  */
 401                 ehci_port2: port@2 {
 402                         reg = <2>;
 403                         #trigger-source-cells = <0>;
 404                 };
 405         };
 406
 407         gic: interrupt-controller@1fbc0000 {
 408                 compatible = "mti,gic";
 409                 reg = <0x1fbc0000 0x2000>;
 410
 411                 interrupt-controller;
 412                 #interrupt-cells = <3>;
 413
 414                 mti,reserved-cpu-vectors = <7>;
 415
 416                 timer {
 417                         compatible = "mti,gic-timer";
 418                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 419                         clocks = <&pll MT7621_CLK_CPU>;
 420                 };
 421         };
 422
 423         nficlock: nficlock {
 424                 #clock-cells = <0>;
 425                 compatible = "fixed-clock";
 426
 427                 clock-frequency = <125000000>;
 428         };
 429
 430         nand: nand@1e003000 {
 431                 status = "disabled";
 432
 433                 compatible = "mediatek,mt7621-nfc";
 434                 reg = <0x1e003000 0x800
 435                         0x1e003800 0x800>;
 436                 reg-names = "nfi", "ecc";
 437
 438                 clocks = <&nficlock>;
 439                 clock-names = "nfi_clk";
 440         };
 441
 442         ethsys: syscon@1e000000 {
 443                 compatible = "mediatek,mt7621-ethsys",
 444                              "syscon";
 445                 reg = <0x1e000000 0x1000>;
 446                 #clock-cells = <1>;
 447         };
 448
 449         ethernet: ethernet@1e100000 {
 450                 compatible = "mediatek,mt7621-eth";
 451                 reg = <0x1e100000 0x10000>;
 452
 453                 clocks = <&sysclock>;
 454                 clock-names = "ethif";
 455
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458
 459                 resets = <&rstctrl 6 &rstctrl 23>;
 460                 reset-names = "fe", "eth";
 461
 462                 interrupt-parent = <&gic>;
 463                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 464
 465                 mediatek,ethsys = <&ethsys>;
 466
 467                 gmac0: mac@0 {
 468                         compatible = "mediatek,eth-mac";
 469                         reg = <0>;
 470                         phy-mode = "rgmii";
 471
 472                         fixed-link {
 473                                 speed = <1000>;
 474                                 full-duplex;
 475                                 pause;
 476                         };
 477                 };
 478
 479                 gmac1: mac@1 {
 480                         compatible = "mediatek,eth-mac";
 481                         reg = <1>;
 482                         status = "disabled";
 483                         phy-mode = "rgmii-rxid";
 484                 };
 485
 486                 mdio: mdio-bus {
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489
 490                         switch0: switch@1f {
 491                                 compatible = "mediatek,mt7621";
 492                                 #address-cells = <1>;
 493                                 #size-cells = <0>;
 494                                 reg = <0x1f>;
 495                                 mediatek,mcm;
 496                                 resets = <&rstctrl 2>;
 497                                 reset-names = "mcm";
 498
 499                                 ports {
 500                                         #address-cells = <1>;
 501                                         #size-cells = <0>;
 502                                         reg = <0>;
 503
 504                                         port@0 {
 505                                                 status = "disabled";
 506                                                 reg = <0>;
 507                                                 label = "lan0";
 508                                         };
 509
 510                                         port@1 {
 511                                                 status = "disabled";
 512                                                 reg = <1>;
 513                                                 label = "lan1";
 514                                         };
 515
 516                                         port@2 {
 517                                                 status = "disabled";
 518                                                 reg = <2>;
 519                                                 label = "lan2";
 520                                         };
 521
 522                                         port@3 {
 523                                                 status = "disabled";
 524                                                 reg = <3>;
 525                                                 label = "lan3";
 526                                         };
 527
 528                                         port@4 {
 529                                                 status = "disabled";
 530                                                 reg = <4>;
 531                                                 label = "lan4";
 532                                         };
 533
 534                                         port@6 {
 535                                                 reg = <6>;
 536                                                 label = "cpu";
 537                                                 ethernet = <&gmac0>;
 538                                                 phy-mode = "rgmii";
 539
 540                                                 fixed-link {
 541                                                         speed = <1000>;
 542                                                         full-duplex;
 543                                                 };
 544                                         };
 545                                 };
 546                         };
 547                 };
 548         };
 549
 550         gsw: gsw@1e110000 {
 551                 compatible = "mediatek,mt7621-gsw";
 552                 reg = <0x1e110000 0x8000>;
 553                 interrupt-parent = <&gic>;
 554                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 555         };
 556
 557         pcie: pcie@1e140000 {
 558                 compatible = "mediatek,mt7621-pci";
 559                 reg = <0x1e140000 0x100     /* host-pci bridge registers */
 560                         0x1e142000 0x100    /* pcie port 0 RC control registers */
 561                         0x1e143000 0x100    /* pcie port 1 RC control registers */
 562                         0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 563                 #address-cells = <3>;
 564                 #size-cells = <2>;
 565
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&pcie_pins>;
 568
 569                 device_type = "pci";
 570
 571                 bus-range = <0 255>;
 572                 ranges = <
 573                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 574                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 575                 >;
 576
 577                 interrupt-parent = <&gic>;
 578                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 579                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 580                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 581
 582                 status = "disabled";
 583
 584                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 585                 reset-names = "pcie0", "pcie1", "pcie2";
 586                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 587                 clock-names = "pcie0", "pcie1", "pcie2";
 588                 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 589                 phy-names = "pcie-phy0", "pcie-phy2";
 590
 591                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 592
 593                 pcie0: pcie@0,0 {
 594                         reg = <0x0000 0 0 0 0>;
 595                         #address-cells = <3>;
 596                         #size-cells = <2>;
 597                         ranges;
 598                         bus-range = <0x00 0xff>;
 599                 };
 600
 601                 pcie1: pcie@1,0 {
 602                         reg = <0x0800 0 0 0 0>;
 603                         #address-cells = <3>;
 604                         #size-cells = <2>;
 605                         ranges;
 606                         bus-range = <0x00 0xff>;
 607                 };
 608
 609                 pcie2: pcie@2,0 {
 610                         reg = <0x1000 0 0 0 0>;
 611                         #address-cells = <3>;
 612                         #size-cells = <2>;
 613                         ranges;
 614                         bus-range = <0x00 0xff>;
 615                 };
 616         };
 617
 618         pcie0_phy: pcie-phy@1e149000 {
 619                 compatible = "mediatek,mt7621-pci-phy";
 620                 reg = <0x1e149000 0x0700>;
 621                 #phy-cells = <1>;
 622         };
 623
 624         pcie2_phy: pcie-phy@1e14a000 {
 625                 compatible = "mediatek,mt7621-pci-phy";
 626                 reg = <0x1e14a000 0x0700>;
 627                 #phy-cells = <1>;
 628         };
 629 };