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ramips: fix mtd partition node names for Phicomm PSG1208
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7621.dtsi
1 /dts-v1/;
2
3 #include <dt-bindings/clock/mt7621-clk.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 #include <dt-bindings/reset/mt7621-reset.h>
7
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "mediatek,mt7621-soc";
12
13 aliases {
14 serial0 = &uartlite;
15 };
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "mips,mips1004Kc";
24 reg = <0>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "mips,mips1004Kc";
30 reg = <1>;
31 };
32 };
33
34 cpuintc: cpuintc {
35 #address-cells = <0>;
36 #interrupt-cells = <1>;
37 interrupt-controller;
38 compatible = "mti,cpu-interrupt-controller";
39 };
40
41 chosen {
42 bootargs = "console=ttyS0,57600";
43 };
44
45 palmbus: palmbus@1e000000 {
46 compatible = "palmbus";
47 reg = <0x1e000000 0x100000>;
48 ranges = <0x0 0x1e000000 0x0fffff>;
49
50 #address-cells = <1>;
51 #size-cells = <1>;
52
53 sysc: syscon@0 {
54 compatible = "mediatek,mt7621-sysc", "syscon";
55 #clock-cells = <1>;
56 #reset-cells = <1>;
57 ralink,memctl = <&memc>;
58 clock-output-names = "xtal", "cpu", "bus",
59 "50m", "125m", "150m",
60 "250m", "270m";
61 reg = <0x0 0x100>;
62 };
63
64 wdt: watchdog@100 {
65 compatible = "mediatek,mt7621-wdt";
66 reg = <0x100 0x100>;
67 mediatek,sysctl = <&sysc>;
68 };
69
70 gpio: gpio@600 {
71 #gpio-cells = <2>;
72 #interrupt-cells = <2>;
73 compatible = "mediatek,mt7621-gpio";
74 gpio-controller;
75 gpio-ranges = <&pinctrl 0 0 95>;
76 interrupt-controller;
77 reg = <0x600 0x100>;
78 interrupt-parent = <&gic>;
79 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
80 };
81
82 i2c: i2c@900 {
83 compatible = "mediatek,mt7621-i2c";
84 reg = <0x900 0x100>;
85
86 clocks = <&sysc MT7621_CLK_I2C>;
87 clock-names = "i2c";
88
89 resets = <&sysc MT7621_RST_I2C>;
90 reset-names = "i2c";
91
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 status = "disabled";
96
97 pinctrl-names = "default";
98 pinctrl-0 = <&i2c_pins>;
99 };
100
101 i2s: i2s@a00 {
102 compatible = "mediatek,mt7621-i2s";
103 reg = <0xa00 0x100>;
104
105 clocks = <&sysc MT7621_CLK_I2S>;
106
107 resets = <&sysc MT7621_RST_I2S>;
108 reset-names = "i2s";
109
110 interrupt-parent = <&gic>;
111 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
112
113 txdma-req = <2>;
114 rxdma-req = <3>;
115
116 dmas = <&gdma 4>,
117 <&gdma 6>;
118 dma-names = "tx", "rx";
119
120 status = "disabled";
121 };
122
123 systick: systick@500 {
124 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
125 reg = <0x500 0x10>;
126
127 resets = <&sysc MT7621_RST_AUX_STCK>;
128 reset-names = "intc";
129
130 interrupt-parent = <&gic>;
131 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
132 };
133
134 memc: memory-controller@5000 {
135 compatible = "mediatek,mt7621-memc", "syscon";
136 reg = <0x5000 0x1000>;
137 };
138
139 uartlite: uartlite@c00 {
140 compatible = "ns16550a";
141 reg = <0xc00 0x100>;
142
143 clocks = <&sysc MT7621_CLK_UART1>;
144
145 resets = <&sysc MT7621_RST_UART1>;
146
147 interrupt-parent = <&gic>;
148 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
149
150 reg-shift = <2>;
151 reg-io-width = <4>;
152 no-loopback-test;
153 };
154
155 uartlite2: uartlite2@d00 {
156 compatible = "ns16550a";
157 reg = <0xd00 0x100>;
158
159 clocks = <&sysc MT7621_CLK_UART2>;
160
161 resets = <&sysc MT7621_RST_UART2>;
162
163 interrupt-parent = <&gic>;
164 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
165
166 reg-shift = <2>;
167 reg-io-width = <4>;
168
169 pinctrl-names = "default";
170 pinctrl-0 = <&uart2_pins>;
171
172 status = "disabled";
173 };
174
175 uartlite3: uartlite3@e00 {
176 compatible = "ns16550a";
177 reg = <0xe00 0x100>;
178
179 clocks = <&sysc MT7621_CLK_UART3>;
180
181 resets = <&sysc MT7621_RST_UART3>;
182
183 interrupt-parent = <&gic>;
184 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
185
186 reg-shift = <2>;
187 reg-io-width = <4>;
188
189 pinctrl-names = "default";
190 pinctrl-0 = <&uart3_pins>;
191
192 status = "disabled";
193 };
194
195 spi0: spi@b00 {
196 status = "disabled";
197
198 compatible = "ralink,mt7621-spi";
199 reg = <0xb00 0x100>;
200
201 clocks = <&sysc MT7621_CLK_SPI>;
202 clock-names = "spi";
203
204 resets = <&sysc MT7621_RST_SPI>;
205 reset-names = "spi";
206
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 pinctrl-names = "default";
211 pinctrl-0 = <&spi_pins>;
212 };
213
214 gdma: gdma@2800 {
215 compatible = "ralink,rt3883-gdma";
216 reg = <0x2800 0x800>;
217
218 resets = <&sysc MT7621_RST_GDMA>;
219 reset-names = "dma";
220
221 interrupt-parent = <&gic>;
222 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
223
224 #dma-cells = <1>;
225 #dma-channels = <16>;
226 #dma-requests = <16>;
227
228 status = "disabled";
229 };
230
231 hsdma: hsdma@7000 {
232 compatible = "mediatek,mt7621-hsdma";
233 reg = <0x7000 0x1000>;
234
235 resets = <&sysc MT7621_RST_HSDMA>;
236 reset-names = "hsdma";
237
238 interrupt-parent = <&gic>;
239 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
240
241 #dma-cells = <1>;
242 #dma-channels = <1>;
243 #dma-requests = <1>;
244
245 status = "disabled";
246 };
247 };
248
249 pinctrl: pinctrl {
250 compatible = "ralink,rt2880-pinmux";
251 pinctrl-names = "default";
252 pinctrl-0 = <&state_default>;
253
254 state_default: pinctrl0 {
255 };
256
257 i2c_pins: i2c_pins {
258 i2c_pins {
259 groups = "i2c";
260 function = "i2c";
261 };
262 };
263
264 spi_pins: spi_pins {
265 spi_pins {
266 groups = "spi";
267 function = "spi";
268 };
269 };
270
271 uart1_pins: uart1 {
272 uart1 {
273 groups = "uart1";
274 function = "uart1";
275 };
276 };
277
278 uart2_pins: uart2 {
279 uart2 {
280 groups = "uart2";
281 function = "uart2";
282 };
283 };
284
285 uart3_pins: uart3 {
286 uart3 {
287 groups = "uart3";
288 function = "uart3";
289 };
290 };
291
292 rgmii1_pins: rgmii1 {
293 rgmii1 {
294 groups = "rgmii1";
295 function = "rgmii1";
296 };
297 };
298
299 rgmii2_pins: rgmii2 {
300 rgmii2 {
301 groups = "rgmii2";
302 function = "rgmii2";
303 };
304 };
305
306 mdio_pins: mdio {
307 mdio {
308 groups = "mdio";
309 function = "mdio";
310 };
311 };
312
313 pcie_pins: pcie {
314 pcie {
315 groups = "pcie";
316 function = "gpio";
317 };
318 };
319
320 nand_pins: nand {
321 spi-nand {
322 groups = "spi";
323 function = "nand1";
324 };
325
326 sdhci-nand {
327 groups = "sdhci";
328 function = "nand2";
329 };
330 };
331
332 sdhci_pins: sdhci {
333 sdhci {
334 groups = "sdhci";
335 function = "sdhci";
336 };
337 };
338 };
339
340 sdhci: sdhci@1e130000 {
341 status = "disabled";
342
343 compatible = "ralink,mt7620-sdhci";
344 reg = <0x1e130000 0x4000>;
345
346 interrupt-parent = <&gic>;
347 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
348
349 pinctrl-names = "default";
350 pinctrl-0 = <&sdhci_pins>;
351 };
352
353 xhci: xhci@1e1c0000 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356
357 compatible = "mediatek,mt8173-xhci";
358 reg = <0x1e1c0000 0x1000
359 0x1e1d0700 0x0100>;
360 reg-names = "mac", "ippc";
361
362 clocks = <&sysc MT7621_CLK_XTAL>;
363 clock-names = "sys_ck";
364
365 interrupt-parent = <&gic>;
366 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
367
368 /*
369 * Port 1 of both hubs is one usb slot and referenced here.
370 * The binding doesn't allow to address individual hubs.
371 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
372 */
373 xhci_ehci_port1: port@1 {
374 reg = <1>;
375 #trigger-source-cells = <0>;
376 };
377
378 /*
379 * Only the second usb hub has a second port. That port serves
380 * ehci and ohci.
381 */
382 ehci_port2: port@2 {
383 reg = <2>;
384 #trigger-source-cells = <0>;
385 };
386 };
387
388 gic: interrupt-controller@1fbc0000 {
389 compatible = "mti,gic";
390 reg = <0x1fbc0000 0x2000>;
391
392 interrupt-controller;
393 #interrupt-cells = <3>;
394
395 mti,reserved-cpu-vectors = <7>;
396
397 timer {
398 compatible = "mti,gic-timer";
399 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
400 clocks = <&sysc MT7621_CLK_CPU>;
401 };
402 };
403
404 cpc: cpc@1fbf0000 {
405 compatible = "mti,mips-cpc";
406 reg = <0x1fbf0000 0x8000>;
407 };
408
409 mc: mc@1fbf8000 {
410 compatible = "mti,mips-cdmm";
411 reg = <0x1fbf8000 0x8000>;
412 };
413
414 nand: nand@1e003000 {
415 status = "disabled";
416
417 compatible = "mediatek,mt7621-nfc";
418 reg = <0x1e003000 0x800
419 0x1e003800 0x800>;
420 reg-names = "nfi", "ecc";
421
422 clocks = <&sysc MT7621_CLK_NAND>;
423 clock-names = "nfi_clk";
424 };
425
426 crypto: crypto@1e004000 {
427 compatible = "mediatek,mtk-eip93";
428 reg = <0x1e004000 0x1000>;
429
430 interrupt-parent = <&gic>;
431 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
432 };
433
434 ethernet: ethernet@1e100000 {
435 compatible = "mediatek,mt7621-eth";
436 reg = <0x1e100000 0x10000>;
437
438 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
439 clock-names = "fe", "ethif";
440
441 #address-cells = <1>;
442 #size-cells = <0>;
443
444 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
445 reset-names = "fe", "eth";
446
447 interrupt-parent = <&gic>;
448 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
449
450 mediatek,ethsys = <&sysc>;
451
452 pinctrl-names = "default";
453 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
454
455 gmac0: mac@0 {
456 compatible = "mediatek,eth-mac";
457 reg = <0>;
458 phy-mode = "rgmii";
459
460 fixed-link {
461 speed = <1000>;
462 full-duplex;
463 pause;
464 };
465 };
466
467 gmac1: mac@1 {
468 compatible = "mediatek,eth-mac";
469 reg = <1>;
470 status = "disabled";
471 phy-mode = "rgmii";
472 };
473
474 mdio: mdio-bus {
475 #address-cells = <1>;
476 #size-cells = <0>;
477
478 switch0: switch@1f {
479 compatible = "mediatek,mt7621";
480 reg = <0x1f>;
481 mediatek,mcm;
482 resets = <&sysc MT7621_RST_MCM>;
483 reset-names = "mcm";
484 interrupt-controller;
485 #interrupt-cells = <1>;
486 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
487
488 ports {
489 #address-cells = <1>;
490 #size-cells = <0>;
491
492 port@0 {
493 status = "disabled";
494 reg = <0>;
495 label = "lan0";
496 };
497
498 port@1 {
499 status = "disabled";
500 reg = <1>;
501 label = "lan1";
502 };
503
504 port@2 {
505 status = "disabled";
506 reg = <2>;
507 label = "lan2";
508 };
509
510 port@3 {
511 status = "disabled";
512 reg = <3>;
513 label = "lan3";
514 };
515
516 port@4 {
517 status = "disabled";
518 reg = <4>;
519 label = "lan4";
520 };
521
522 port@6 {
523 reg = <6>;
524 ethernet = <&gmac0>;
525 phy-mode = "rgmii";
526
527 fixed-link {
528 speed = <1000>;
529 full-duplex;
530 pause;
531 };
532 };
533 };
534 };
535 };
536 };
537
538 pcie: pcie@1e140000 {
539 compatible = "mediatek,mt7621-pci";
540 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
541 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
542 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
543 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
544 #address-cells = <3>;
545 #size-cells = <2>;
546
547 pinctrl-names = "default";
548 pinctrl-0 = <&pcie_pins>;
549
550 device_type = "pci";
551
552 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
553 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
554
555 status = "disabled";
556
557 #interrupt-cells = <1>;
558 interrupt-map-mask = <0xF800 0 0 0>;
559 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
560 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
561 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
562
563 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
564
565 pcie0: pcie@0,0 {
566 reg = <0x0000 0 0 0 0>;
567 #address-cells = <3>;
568 #size-cells = <2>;
569 device_type = "pci";
570 ranges;
571 #interrupt-cells = <1>;
572 interrupt-map-mask = <0 0 0 0>;
573 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
574 resets = <&sysc MT7621_RST_PCIE0>;
575 clocks = <&sysc MT7621_CLK_PCIE0>;
576 phys = <&pcie0_phy 1>;
577 phy-names = "pcie-phy0";
578 };
579
580 pcie1: pcie@1,0 {
581 reg = <0x0800 0 0 0 0>;
582 #address-cells = <3>;
583 #size-cells = <2>;
584 device_type = "pci";
585 ranges;
586 #interrupt-cells = <1>;
587 interrupt-map-mask = <0 0 0 0>;
588 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
589 resets = <&sysc MT7621_RST_PCIE1>;
590 clocks = <&sysc MT7621_CLK_PCIE1>;
591 phys = <&pcie0_phy 1>;
592 phy-names = "pcie-phy1";
593 };
594
595 pcie2: pcie@2,0 {
596 reg = <0x1000 0 0 0 0>;
597 #address-cells = <3>;
598 #size-cells = <2>;
599 device_type = "pci";
600 ranges;
601 #interrupt-cells = <1>;
602 interrupt-map-mask = <0 0 0 0>;
603 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
604 resets = <&sysc MT7621_RST_PCIE2>;
605 clocks = <&sysc MT7621_CLK_PCIE2>;
606 phys = <&pcie2_phy 0>;
607 phy-names = "pcie-phy2";
608 };
609 };
610
611 pcie0_phy: pcie-phy@1e149000 {
612 compatible = "mediatek,mt7621-pci-phy";
613 reg = <0x1e149000 0x0700>;
614 clocks = <&sysc MT7621_CLK_XTAL>;
615 #phy-cells = <1>;
616 };
617
618 pcie2_phy: pcie-phy@1e14a000 {
619 compatible = "mediatek,mt7621-pci-phy";
620 reg = <0x1e14a000 0x0700>;
621 clocks = <&sysc MT7621_CLK_XTAL>;
622 #phy-cells = <1>;
623 };
624 };
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