target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         aliases {
  26                 serial0 = &uartlite;
  27         };
  28
  29         cpuclock: cpuclock@0 {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-clock";
  32
  33                 /* FIXME: there should be way to detect this */
  34                 clock-frequency = <880000000>;
  35         };
  36
  37         sysclock: sysclock@0 {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40
  41                 /* FIXME: there should be way to detect this */
  42                 clock-frequency = <50000000>;
  43         };
  44
  45         palmbus: palmbus@1E000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1E000000 0x100000>;
  48                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: sysc@0 {
  54                         compatible = "mtk,mt7621-sysc";
  55                         reg = <0x0 0x100>;
  56                 };
  57
  58                 wdt: wdt@100 {
  59                         compatible = "mtk,mt7621-wdt";
  60                         reg = <0x100 0x100>;
  61                 };
  62
  63                 gpio@600 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66
  67                         compatible = "mtk,mt7621-gpio";
  68                         reg = <0x600 0x100>;
  69
  70                         gpio0: bank@0 {
  71                                 reg = <0>;
  72                                 compatible = "mtk,mt7621-gpio-bank";
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                         };
  76
  77                         gpio1: bank@1 {
  78                                 reg = <1>;
  79                                 compatible = "mtk,mt7621-gpio-bank";
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82                         };
  83
  84                         gpio2: bank@2 {
  85                                 reg = <2>;
  86                                 compatible = "mtk,mt7621-gpio-bank";
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89                         };
  90                 };
  91
  92                 i2c: i2c@900 {
  93                         compatible = "mediatek,mt7621-i2c";
  94                         reg = <0x900 0x100>;
  95
  96                         clocks = <&sysclock>;
  97
  98                         resets = <&rstctrl 16>;
  99                         reset-names = "i2c";
 100
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103
 104                         status = "disabled";
 105
 106                         pinctrl-names = "default";
 107                         pinctrl-0 = <&i2c_pins>;
 108                 };
 109
 110                 memc: memc@5000 {
 111                         compatible = "mtk,mt7621-memc";
 112                         reg = <0x300 0x100>;
 113                 };
 114
 115                 cpc: cpc@1fbf0000 {
 116                              compatible = "mtk,mt7621-cpc";
 117                              reg = <0x1fbf0000 0x8000>;
 118                 };
 119
 120                 mc: mc@1fbf8000 {
 121                             compatible = "mtk,mt7621-mc";
 122                             reg = <0x1fbf8000 0x8000>;
 123                 };
 124
 125                 uartlite: uartlite@c00 {
 126                         compatible = "ns16550a";
 127                         reg = <0xc00 0x100>;
 128
 129                         clocks = <&sysclock>;
 130                         clock-frequency = <50000000>;
 131
 132                         interrupt-parent = <&gic>;
 133                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 134
 135                         reg-shift = <2>;
 136                         reg-io-width = <4>;
 137                         no-loopback-test;
 138                 };
 139
 140                 spi0: spi@b00 {
 141                         status = "okay";
 142
 143                         compatible = "ralink,mt7621-spi";
 144                         reg = <0xb00 0x100>;
 145
 146                         clocks = <&sysclock>;
 147
 148                         resets = <&rstctrl 18>;
 149                         reset-names = "spi";
 150
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153
 154                         pinctrl-names = "default";
 155                         pinctrl-0 = <&spi_pins>;
 156
 157                         m25p80@0 {
 158                                 #address-cells = <1>;
 159                                 #size-cells = <1>;
 160                                 reg = <0>;
 161                                 spi-max-frequency = <10000000>;
 162                                 m25p,chunked-io = <32>;
 163                         };
 164                 };
 165
 166                 gdma: gdma@2800 {
 167                         compatible = "ralink,rt3883-gdma";
 168                         reg = <0x2800 0x800>;
 169
 170                         resets = <&rstctrl 14>;
 171                         reset-names = "dma";
 172
 173                         interrupt-parent = <&gic>;
 174                         interrupts = <0 13 4>;
 175
 176                         #dma-cells = <1>;
 177                         #dma-channels = <16>;
 178                         #dma-requests = <16>;
 179
 180                         status = "disabled";
 181                 };
 182
 183                 hsdma: hsdma@7000 {
 184                         compatible = "mediatek,mt7621-hsdma";
 185                         reg = <0x7000 0x1000>;
 186
 187                         resets = <&rstctrl 5>;
 188                         reset-names = "hsdma";
 189
 190                         interrupt-parent = <&gic>;
 191                         interrupts = <0 11 4>;
 192
 193                         #dma-cells = <1>;
 194                         #dma-channels = <1>;
 195                         #dma-requests = <1>;
 196
 197                         status = "disabled";
 198                 };
 199         };
 200
 201         pinctrl: pinctrl {
 202                 compatible = "ralink,rt2880-pinmux";
 203                 pinctrl-names = "default";
 204                 pinctrl-0 = <&state_default>;
 205
 206                 state_default: pinctrl0 {
 207                 };
 208
 209                 i2c_pins: i2c {
 210                         i2c {
 211                                 ralink,group = "i2c";
 212                                 ralink,function = "i2c";
 213                         };
 214                 };
 215
 216                 spi_pins: spi {
 217                         spi {
 218                                 ralink,group = "spi";
 219                                 ralink,function = "spi";
 220                         };
 221                 };
 222
 223                 uart1_pins: uart1 {
 224                         uart1 {
 225                                 ralink,group = "uart1";
 226                                 ralink,function = "uart1";
 227                         };
 228                 };
 229
 230                 uart2_pins: uart2 {
 231                         uart2 {
 232                                 ralink,group = "uart2";
 233                                 ralink,function = "uart2";
 234                         };
 235                 };
 236
 237                 uart3_pins: uart3 {
 238                         uart3 {
 239                                 ralink,group = "uart3";
 240                                 ralink,function = "uart3";
 241                         };
 242                 };
 243
 244                 rgmii1_pins: rgmii1 {
 245                         rgmii1 {
 246                                 ralink,group = "rgmii1";
 247                                 ralink,function = "rgmii1";
 248                         };
 249                 };
 250
 251                 rgmii2_pins: rgmii2 {
 252                         rgmii2 {
 253                                 ralink,group = "rgmii2";
 254                                 ralink,function = "rgmii2";
 255                         };
 256                 };
 257
 258                 mdio_pins: mdio {
 259                         mdio {
 260                                 ralink,group = "mdio";
 261                                 ralink,function = "mdio";
 262                         };
 263                 };
 264
 265                 pcie_pins: pcie {
 266                         pcie {
 267                                 ralink,group = "pcie";
 268                                 ralink,function = "pcie rst";
 269                         };
 270                 };
 271
 272                 nand_pins: nand {
 273                         spi-nand {
 274                                 ralink,group = "spi";
 275                                 ralink,function = "nand1";
 276                         };
 277
 278                         sdhci-nand {
 279                                 ralink,group = "sdhci";
 280                                 ralink,function = "nand2";
 281                         };
 282                 };
 283
 284                 sdhci_pins: sdhci {
 285                         sdhci {
 286                                 ralink,group = "sdhci";
 287                                 ralink,function = "sdhci";
 288                         };
 289                 };
 290         };
 291
 292         rstctrl: rstctrl {
 293                 compatible = "ralink,rt2880-reset";
 294                 #reset-cells = <1>;
 295         };
 296
 297         clkctrl: clkctrl {
 298                 compatible = "ralink,rt2880-clock";
 299                 #clock-cells = <1>;
 300         };
 301
 302         sdhci: sdhci@1E130000 {
 303                 compatible = "ralink,mt7620-sdhci";
 304                 reg = <0x1E130000 0x4000>;
 305
 306                 interrupt-parent = <&gic>;
 307                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 308         };
 309
 310         xhci: xhci@1E1C0000 {
 311                 status = "okay";
 312
 313                 compatible = "mediatek,mt8173-xhci";
 314                 reg = <0x1e1c0000 0x1000
 315                        0x1e1d0700 0x0100>;
 316
 317                 clocks = <&sysclock>;
 318                 clock-names = "sys_ck";
 319
 320                 interrupt-parent = <&gic>;
 321                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 322         };
 323
 324         gic: interrupt-controller@1fbc0000 {
 325                 compatible = "mti,gic";
 326                 reg = <0x1fbc0000 0x2000>;
 327
 328                 interrupt-controller;
 329                 #interrupt-cells = <3>;
 330
 331                 mti,reserved-cpu-vectors = <7>;
 332
 333                 timer {
 334                         compatible = "mti,gic-timer";
 335                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 336                         clocks = <&cpuclock>;
 337                 };
 338         };
 339
 340         nand: nand@1e003000 {
 341                 status = "disabled";
 342
 343                 compatible = "mtk,mt7621-nand";
 344                 bank-width = <2>;
 345                 reg = <0x1e003000 0x800
 346                         0x1e003800 0x800>;
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349         };
 350
 351         ethernet: ethernet@1e100000 {
 352                 compatible = "mediatek,mt7621-eth";
 353                 reg = <0x1e100000 0x10000>;
 354
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357
 358                 resets = <&rstctrl 6 &rstctrl 23>;
 359                 reset-names = "fe", "eth";
 360
 361                 interrupt-parent = <&gic>;
 362                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 363
 364                 mediatek,switch = <&gsw>;
 365
 366                 mdio-bus {
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369
 370                         phy1f: ethernet-phy@1f {
 371                                 reg = <0x1f>;
 372                                 phy-mode = "rgmii";
 373                         };
 374                 };
 375         };
 376
 377         gsw: gsw@1e110000 {
 378                 compatible = "mediatek,mt7621-gsw";
 379                 reg = <0x1e110000 0x8000>;
 380                 interrupt-parent = <&gic>;
 381                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 382         };
 383
 384         pcie: pcie@1e140000 {
 385                 compatible = "mediatek,mt7621-pci";
 386                 reg = <0x1e140000 0x100
 387                         0x1e142000 0x100>;
 388
 389                 #address-cells = <3>;
 390                 #size-cells = <2>;
 391
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&pcie_pins>;
 394
 395                 device_type = "pci";
 396
 397                 bus-range = <0 255>;
 398                 ranges = <
 399                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 400                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 401                 >;
 402
 403                 interrupt-parent = <&gic>;
 404                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 405                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 406                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 407
 408                 status = "okay";
 409
 410                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 411                 reset-names = "pcie0", "pcie1", "pcie2";
 412                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 413                 clock-names = "pcie0", "pcie1", "pcie2";
 414
 415                 pcie0 {
 416                         reg = <0x0000 0 0 0 0>;
 417
 418                         #address-cells = <3>;
 419                         #size-cells = <2>;
 420
 421                         device_type = "pci";
 422                 };
 423
 424                 pcie1 {
 425                         reg = <0x0800 0 0 0 0>;
 426
 427                         #address-cells = <3>;
 428                         #size-cells = <2>;
 429
 430                         device_type = "pci";
 431                 };
 432
 433                 pcie2 {
 434                         reg = <0x1000 0 0 0 0>;
 435
 436                         #address-cells = <3>;
 437                         #size-cells = <2>;
 438
 439                         device_type = "pci";
 440                 };
 441         };
 442 };