fd584a12ab75549e6683d91ff31d08897531deb0
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7628an.dtsi
1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,mtk7628an-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24KEc";
9 };
10 };
11
12 chosen {
13 bootargs = "console=ttyS0,57600";
14 };
15
16 cpuintc: cpuintc@0 {
17 #address-cells = <0>;
18 #interrupt-cells = <1>;
19 interrupt-controller;
20 compatible = "mti,cpu-interrupt-controller";
21 };
22
23 palmbus@10000000 {
24 compatible = "palmbus";
25 reg = <0x10000000 0x200000>;
26 ranges = <0x0 0x10000000 0x1FFFFF>;
27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 sysc@0 {
32 compatible = "ralink,mt7620a-sysc";
33 reg = <0x0 0x100>;
34 };
35
36 watchdog@120 {
37 compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
38 reg = <0x120 0x10>;
39
40 resets = <&rstctrl 8>;
41 reset-names = "wdt";
42
43 interrupt-parent = <&intc>;
44 interrupts = <24>;
45 };
46
47 intc: intc@200 {
48 compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
49 reg = <0x200 0x100>;
50
51 resets = <&rstctrl 9>;
52 reset-names = "intc";
53
54 interrupt-controller;
55 #interrupt-cells = <1>;
56
57 interrupt-parent = <&cpuintc>;
58 interrupts = <2>;
59
60 ralink,intc-registers = <0x9c 0xa0
61 0x6c 0xa4
62 0x80 0x78>;
63 };
64
65 memc@300 {
66 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
67 reg = <0x300 0x100>;
68
69 resets = <&rstctrl 20>;
70 reset-names = "mc";
71
72 interrupt-parent = <&intc>;
73 interrupts = <3>;
74 };
75
76 gpio@600 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
81 reg = <0x600 0x100>;
82
83 interrupt-parent = <&intc>;
84 interrupts = <6>;
85
86 gpio0: bank@0 {
87 reg = <0>;
88 compatible = "mtk,mt7621-gpio-bank";
89 gpio-controller;
90 #gpio-cells = <2>;
91 };
92
93 gpio1: bank@1 {
94 reg = <1>;
95 compatible = "mtk,mt7621-gpio-bank";
96 gpio-controller;
97 #gpio-cells = <2>;
98 };
99
100 gpio2: bank@2 {
101 reg = <2>;
102 compatible = "mtk,mt7621-gpio-bank";
103 gpio-controller;
104 #gpio-cells = <2>;
105 };
106 };
107
108 spi@b00 {
109 compatible = "ralink,mt7621-spi";
110 reg = <0xb00 0x100>;
111
112 resets = <&rstctrl 18>;
113 reset-names = "spi";
114
115 #address-cells = <1>;
116 #size-cells = <1>;
117
118 pinctrl-names = "default";
119 pinctrl-0 = <&spi_pins>;
120
121 status = "disabled";
122 };
123
124 uartlite@c00 {
125 compatible = "ns16550a";
126 reg = <0xc00 0x100>;
127
128 reg-shift = <2>;
129 reg-io-width = <4>;
130 no-loopback-test;
131
132 resets = <&rstctrl 12>;
133 reset-names = "uartl";
134
135 interrupt-parent = <&intc>;
136 interrupts = <20>;
137
138 pinctrl-names = "default";
139 pinctrl-0 = <&uart0_pins>;
140 };
141
142 uart1@d00 {
143 compatible = "ns16550a";
144 reg = <0xd00 0x100>;
145
146 reg-shift = <2>;
147 reg-io-width = <4>;
148 no-loopback-test;
149
150 resets = <&rstctrl 19>;
151 reset-names = "uart1";
152
153 interrupt-parent = <&intc>;
154 interrupts = <21>;
155
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart1_pins>;
158
159 status = "disabled";
160 };
161
162 uart2@e00 {
163 compatible = "ns16550a";
164 reg = <0xe00 0x100>;
165
166 reg-shift = <2>;
167 reg-io-width = <4>;
168 no-loopback-test;
169
170 resets = <&rstctrl 20>;
171 reset-names = "uart2";
172
173 interrupt-parent = <&intc>;
174 interrupts = <22>;
175
176 pinctrl-names = "default";
177 pinctrl-0 = <&uart2_pins>;
178
179 status = "disabled";
180 };
181 };
182
183 pinctrl {
184 compatible = "ralink,rt2880-pinmux";
185 pinctrl-names = "default";
186 pinctrl-0 = <&state_default>;
187
188 state_default: pinctrl0 {
189 };
190
191 spi_pins: spi {
192 spi {
193 ralink,group = "spi";
194 ralink,function = "spi";
195 };
196 };
197
198 uart0_pins: uartlite {
199 uartlite {
200 ralink,group = "uart0";
201 ralink,function = "uart0";
202 };
203 };
204
205 uart1_pins: uart1 {
206 uart1 {
207 ralink,group = "uart1";
208 ralink,function = "uart1";
209 };
210 };
211
212 uart2_pins: uart2 {
213 uart2 {
214 ralink,group = "uart2";
215 ralink,function = "uart2";
216 };
217 };
218
219 sdxc_pins: sdxc {
220 sdxc {
221 ralink,group = "sdmode";
222 ralink,function = "sdxc";
223 };
224 };
225 };
226
227 rstctrl: rstctrl {
228 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
229 #reset-cells = <1>;
230 };
231
232 usbphy: usbphy {
233 compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
234 #phy-cells = <1>;
235
236 resets = <&rstctrl 22>;
237 reset-names = "host";
238 };
239
240 sdhci@10130000 {
241 compatible = "ralink,mt7620-sdhci";
242 reg = <0x10130000 4000>;
243
244 interrupt-parent = <&intc>;
245 interrupts = <14>;
246
247 pinctrl-names = "default";
248 pinctrl-0 = <&sdxc_pins>;
249
250 status = "disabled";
251 };
252
253 ehci@101c0000 {
254 compatible = "ralink,rt3xxx-ehci";
255 reg = <0x101c0000 0x1000>;
256
257 phys = <&usbphy 1>;
258 phy-names = "usb";
259
260 interrupt-parent = <&intc>;
261 interrupts = <18>;
262 };
263
264 ohci@101c1000 {
265 compatible = "ralink,rt3xxx-ohci";
266 reg = <0x101c1000 0x1000>;
267
268 phys = <&usbphy 1>;
269 phy-names = "usb";
270
271 interrupt-parent = <&intc>;
272 interrupts = <18>;
273 };
274
275 ethernet@10100000 {
276 compatible = "ralink,rt5350-eth";
277 reg = <0x10100000 10000>;
278
279 interrupt-parent = <&cpuintc>;
280 interrupts = <5>;
281
282 resets = <&rstctrl 21 &rstctrl 23>;
283 reset-names = "fe", "esw";
284 };
285
286 esw@10110000 {
287 compatible = "ralink,rt3050-esw";
288 reg = <0x10110000 8000>;
289
290 resets = <&rstctrl 23>;
291 reset-names = "esw";
292
293 interrupt-parent = <&intc>;
294 interrupts = <17>;
295 };
296
297 pcie@10140000 {
298 compatible = "mediatek,mt7620-pci";
299 reg = <0x10140000 0x100
300 0x10142000 0x100>;
301
302 #address-cells = <3>;
303 #size-cells = <2>;
304
305 resets = <&rstctrl 26>;
306 reset-names = "pcie0";
307
308 interrupt-parent = <&cpuintc>;
309 interrupts = <4>;
310
311 status = "disabled";
312
313 device_type = "pci";
314
315 bus-range = <0 255>;
316 ranges = <
317 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
318 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
319 >;
320
321 pcie-bridge {
322 reg = <0x0000 0 0 0 0>;
323
324 #address-cells = <3>;
325 #size-cells = <2>;
326
327 device_type = "pci";
328 };
329 };
330 };