ramips: add proper system clock and reset driver support for legacy SoCs
[openwrt/openwrt.git] / target / linux / ramips / dts / rt3050.dtsi
1 /dts-v1/;
2
3 / {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
7
8 aliases {
9 spi0 = &spi0;
10 serial0 = &uartlite;
11 };
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "mips,mips24KEc";
19 reg = <0>;
20 };
21 };
22
23 chosen {
24 bootargs = "console=ttyS0,57600";
25 };
26
27 cpuintc: cpuintc {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
32 };
33
34 palmbus: palmbus@10000000 {
35 compatible = "palmbus";
36 reg = <0x10000000 0x200000>;
37 ranges = <0x0 0x10000000 0x1FFFFF>;
38
39 #address-cells = <1>;
40 #size-cells = <1>;
41
42 sysc: syscon@0 {
43 compatible = "ralink,rt3050-sysc", "syscon";
44 reg = <0x0 0x100>;
45 #clock-cells = <1>;
46 #reset-cells = <1>;
47 };
48
49 timer: timer@100 {
50 compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
51 reg = <0x100 0x20>;
52
53 clocks = <&sysc 3>;
54
55 interrupt-parent = <&intc>;
56 interrupts = <1>;
57 };
58
59 watchdog: watchdog@120 {
60 compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
61 reg = <0x120 0x10>;
62
63 clocks = <&sysc 4>;
64
65 resets = <&sysc 8>;
66 reset-names = "wdt";
67
68 interrupt-parent = <&intc>;
69 interrupts = <1>;
70 };
71
72 intc: intc@200 {
73 compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
74 reg = <0x200 0x100>;
75
76 resets = <&sysc 19>;
77 reset-names = "intc";
78
79 interrupt-controller;
80 #interrupt-cells = <1>;
81
82 interrupt-parent = <&cpuintc>;
83 interrupts = <2>;
84 };
85
86 memc: memc@300 {
87 compatible = "ralink,rt3050-memc";
88 reg = <0x300 0x100>;
89
90 resets = <&sysc 20>;
91 reset-names = "mc";
92
93 interrupt-parent = <&intc>;
94 interrupts = <3>;
95 };
96
97 uart: uart@500 {
98 compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
99 reg = <0x500 0x100>;
100
101 clocks = <&sysc 5>;
102
103 resets = <&sysc 12>;
104
105 interrupt-parent = <&intc>;
106 interrupts = <5>;
107
108 reg-shift = <2>;
109
110 status = "disabled";
111 };
112
113 gpio0: gpio@600 {
114 compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
115 reg = <0x600 0x34>;
116
117 gpio-controller;
118 #gpio-cells = <2>;
119
120 ngpios = <24>;
121 ralink,gpio-base = <0>;
122 ralink,register-map = [ 00 04 08 0c
123 20 24 28 2c
124 30 34 ];
125
126 resets = <&sysc 13>;
127 reset-names = "pio";
128
129 interrupt-parent = <&intc>;
130 interrupts = <6>;
131 };
132
133 gpio1: gpio@638 {
134 compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
135 reg = <0x638 0x24>;
136
137 gpio-controller;
138 #gpio-cells = <2>;
139
140 ngpios = <16>;
141 ralink,gpio-base = <24>;
142 ralink,register-map = [ 00 04 08 0c
143 10 14 18 1c
144 20 24 ];
145
146 status = "disabled";
147 };
148
149 gpio2: gpio@660 {
150 compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
151 reg = <0x660 0x24>;
152
153 gpio-controller;
154 #gpio-cells = <2>;
155
156 ngpios = <12>;
157 ralink,gpio-base = <40>;
158 ralink,register-map = [ 00 04 08 0c
159 10 14 18 1c
160 20 24 ];
161
162 status = "disabled";
163 };
164
165 gdma: gdma@700 {
166 compatible = "ralink,rt305x-gdma";
167 reg = <0x700 0x100>;
168
169 resets = <&sysc 14>;
170 reset-names = "dma";
171
172 interrupt-parent = <&intc>;
173 interrupts = <7>;
174
175 #dma-cells = <1>;
176 #dma-channels = <8>;
177 #dma-requests = <8>;
178
179 status = "disabled";
180 };
181
182 i2c@900 {
183 compatible = "ralink,rt2880-i2c";
184 reg = <0x900 0x100>;
185
186 clocks = <&sysc 6>;
187
188 resets = <&sysc 16>;
189 reset-names = "i2c";
190
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 status = "disabled";
195
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2c_pins>;
198 };
199
200 i2s@a00 {
201 compatible = "ralink,rt3050-i2s";
202 reg = <0xa00 0x100>;
203
204 clocks = <&sysc 7>;
205
206 resets = <&sysc 17>;
207 reset-names = "i2s";
208
209 interrupt-parent = <&intc>;
210 interrupts = <10>;
211
212 txdma-req = <2>;
213
214 dmas = <&gdma 4>;
215 dma-names = "tx";
216
217 status = "disabled";
218 };
219
220 spi0: spi@b00 {
221 compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
222 reg = <0xb00 0x100>;
223
224 resets = <&sysc 18>;
225 reset-names = "spi";
226
227 clocks = <&sysc 8>;
228
229 #address-cells = <1>;
230 #size-cells = <0>;
231
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi_pins>;
234
235 status = "disabled";
236 };
237
238 uartlite: uartlite@c00 {
239 compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
240 reg = <0xc00 0x100>;
241
242 clocks = <&sysc 10>;
243
244 resets = <&sysc 19>;
245
246 interrupt-parent = <&intc>;
247 interrupts = <12>;
248
249 reg-shift = <2>;
250
251 pinctrl-names = "default";
252 pinctrl-0 = <&uartlite_pins>;
253 };
254 };
255
256 pinctrl: pinctrl {
257 compatible = "ralink,rt2880-pinmux";
258
259 pinctrl-names = "default";
260 pinctrl-0 = <&state_default>;
261
262 state_default: pinctrl0 {
263 sdram {
264 groups = "sdram";
265 function = "sdram";
266 };
267 };
268
269 i2c_pins: i2c_pins {
270 i2c_pins {
271 groups = "i2c";
272 function = "i2c";
273 };
274 };
275
276 spi_pins: spi_pins {
277 spi_pins {
278 groups = "spi";
279 function = "spi";
280 };
281 };
282
283 rgmii_pins: rgmii {
284 rgmii {
285 groups = "rgmii";
286 function = "rgmii";
287 };
288 };
289
290 uartlite_pins: uartlite {
291 uart {
292 groups = "uartlite";
293 function = "uartlite";
294 };
295 };
296 };
297
298 usbphy: usbphy {
299 compatible = "ralink,rt3050-usbphy";
300 #phy-cells = <0>;
301
302 ralink,sysctl = <&sysc>;
303 resets = <&sysc 22>;
304 reset-names = "host";
305 };
306
307 ethernet: ethernet@10100000 {
308 compatible = "ralink,rt3050-eth";
309 reg = <0x10100000 0x10000>;
310
311 clocks = <&sysc 11>;
312
313 resets = <&sysc 21>;
314 reset-names = "fe";
315
316 interrupt-parent = <&cpuintc>;
317 interrupts = <5>;
318
319 mediatek,switch = <&esw>;
320 };
321
322 esw: esw@10110000 {
323 compatible = "ralink,rt3050-esw";
324 reg = <0x10110000 0x8000>;
325
326 resets = <&sysc 23>, <&sysc 24>;
327 reset-names = "esw", "ephy";
328
329 interrupt-parent = <&intc>;
330 interrupts = <17>;
331 };
332
333 wmac: wmac@10180000 {
334 compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
335 reg = <0x10180000 0x40000>;
336
337 clocks = <&sysc 12>;
338
339 interrupt-parent = <&cpuintc>;
340 interrupts = <6>;
341
342 ralink,eeprom = "soc_wmac.eeprom";
343 };
344
345 otg: otg@101c0000 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 compatible = "ralink,rt3050-otg", "snps,dwc2";
349 reg = <0x101c0000 0x40000>;
350
351 interrupt-parent = <&intc>;
352 interrupts = <18>;
353
354 resets = <&sysc 22>;
355 reset-names = "otg";
356
357 status = "disabled";
358
359 otg_port1: port@1 {
360 reg = <1>;
361 #trigger-source-cells = <0>;
362 };
363 };
364 };