target/linux/ramips/dts/rt3050.dtsi

   1 /dts-v1/;
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
   7
   8         aliases {
   9                 spi0 = &spi0;
  10                 serial0 = &uartlite;
  11         };
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu@0 {
  18                         compatible = "mips,mips24KEc";
  19                         reg = <0>;
  20                 };
  21         };
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,57600";
  25         };
  26
  27         cpuintc: cpuintc {
  28                 #address-cells = <0>;
  29                 #interrupt-cells = <1>;
  30                 interrupt-controller;
  31                 compatible = "mti,cpu-interrupt-controller";
  32         };
  33
  34         palmbus: palmbus@10000000 {
  35                 compatible = "palmbus";
  36                 reg = <0x10000000 0x200000>;
  37                 ranges = <0x0 0x10000000 0x1FFFFF>;
  38
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41
  42                 sysc: syscon@0 {
  43                         compatible = "ralink,rt3050-sysc", "ralink,rt3052-sysc", "syscon";
  44                         reg = <0x0 0x100>;
  45                         #clock-cells = <1>;
  46                         #reset-cells = <1>;
  47                 };
  48
  49                 timer: timer@100 {
  50                         compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
  51                         reg = <0x100 0x20>;
  52
  53                         clocks = <&sysc 3>;
  54
  55                         interrupt-parent = <&intc>;
  56                         interrupts = <1>;
  57                 };
  58
  59                 watchdog: watchdog@120 {
  60                         compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
  61                         reg = <0x120 0x10>;
  62
  63                         clocks = <&sysc 4>;
  64
  65                         resets = <&sysc 8>;
  66                         reset-names = "wdt";
  67
  68                         interrupt-parent = <&intc>;
  69                         interrupts = <1>;
  70                 };
  71
  72                 intc: intc@200 {
  73                         compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
  74                         reg = <0x200 0x100>;
  75
  76                         interrupt-controller;
  77                         #interrupt-cells = <1>;
  78
  79                         interrupt-parent = <&cpuintc>;
  80                         interrupts = <2>;
  81                 };
  82
  83                 memc: memc@300 {
  84                         compatible = "ralink,rt3050-memc";
  85                         reg = <0x300 0x100>;
  86
  87                         interrupt-parent = <&intc>;
  88                         interrupts = <3>;
  89                 };
  90
  91                 uart: uart@500 {
  92                         compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
  93                         reg = <0x500 0x100>;
  94
  95                         clocks = <&sysc 5>;
  96
  97                         resets = <&sysc 12>;
  98
  99                         interrupt-parent = <&intc>;
 100                         interrupts = <5>;
 101
 102                         reg-shift = <2>;
 103
 104                         status = "disabled";
 105                 };
 106
 107                 gpio0: gpio@600 {
 108                         compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
 109                         reg = <0x600 0x34>;
 110
 111                         gpio-controller;
 112                         #gpio-cells = <2>;
 113
 114                         ngpios = <24>;
 115                         ralink,gpio-base = <0>;
 116                         ralink,register-map = [ 00 04 08 0c
 117                                                 20 24 28 2c
 118                                                 30 34 ];
 119
 120                         interrupt-parent = <&intc>;
 121                         interrupts = <6>;
 122                 };
 123
 124                 gpio1: gpio@638 {
 125                         compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
 126                         reg = <0x638 0x24>;
 127
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130
 131                         ngpios = <16>;
 132                         ralink,gpio-base = <24>;
 133                         ralink,register-map = [ 00 04 08 0c
 134                                                 10 14 18 1c
 135                                                 20 24 ];
 136
 137                         status = "disabled";
 138                 };
 139
 140                 gpio2: gpio@660 {
 141                         compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
 142                         reg = <0x660 0x24>;
 143
 144                         gpio-controller;
 145                         #gpio-cells = <2>;
 146
 147                         ngpios = <12>;
 148                         ralink,gpio-base = <40>;
 149                         ralink,register-map = [ 00 04 08 0c
 150                                                 10 14 18 1c
 151                                                 20 24 ];
 152
 153                         status = "disabled";
 154                 };
 155
 156                 gdma: gdma@700 {
 157                         compatible = "ralink,rt305x-gdma";
 158                         reg = <0x700 0x100>;
 159
 160                         resets = <&sysc 14>;
 161                         reset-names = "dma";
 162
 163                         interrupt-parent = <&intc>;
 164                         interrupts = <7>;
 165
 166                         #dma-cells = <1>;
 167                         #dma-channels = <8>;
 168                         #dma-requests = <8>;
 169
 170                         status = "disabled";
 171                 };
 172
 173                 i2c@900 {
 174                         compatible = "ralink,rt2880-i2c";
 175                         reg = <0x900 0x100>;
 176
 177                         clocks = <&sysc 6>;
 178
 179                         resets = <&sysc 16>;
 180                         reset-names = "i2c";
 181
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184
 185                         status = "disabled";
 186
 187                         pinctrl-names = "default";
 188                         pinctrl-0 = <&i2c_pins>;
 189                 };
 190
 191                 i2s@a00 {
 192                         compatible = "ralink,rt3050-i2s";
 193                         reg = <0xa00 0x100>;
 194
 195                         clocks = <&sysc 7>;
 196
 197                         resets = <&sysc 17>;
 198                         reset-names = "i2s";
 199
 200                         interrupt-parent = <&intc>;
 201                         interrupts = <10>;
 202
 203                         txdma-req = <2>;
 204
 205                         dmas = <&gdma 4>;
 206                         dma-names = "tx";
 207
 208                         status = "disabled";
 209                 };
 210
 211                 spi0: spi@b00 {
 212                         compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
 213                         reg = <0xb00 0x100>;
 214
 215                         resets = <&sysc 18>;
 216                         reset-names = "spi";
 217
 218                         clocks = <&sysc 8>;
 219
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222
 223                         pinctrl-names = "default";
 224                         pinctrl-0 = <&spi_pins>;
 225
 226                         status = "disabled";
 227                 };
 228
 229                 uartlite: uartlite@c00 {
 230                         compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
 231                         reg = <0xc00 0x100>;
 232
 233                         clocks = <&sysc 10>;
 234
 235                         resets = <&sysc 19>;
 236
 237                         interrupt-parent = <&intc>;
 238                         interrupts = <12>;
 239
 240                         reg-shift = <2>;
 241
 242                         pinctrl-names = "default";
 243                         pinctrl-0 = <&uartlite_pins>;
 244                 };
 245         };
 246
 247         pinctrl: pinctrl {
 248                 compatible = "ralink,rt2880-pinmux";
 249
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&state_default>;
 252
 253                 state_default: pinctrl0 {
 254                         sdram {
 255                                 groups = "sdram";
 256                                 function = "sdram";
 257                         };
 258                 };
 259
 260                 i2c_pins: i2c_pins {
 261                         i2c_pins {
 262                                 groups = "i2c";
 263                                 function = "i2c";
 264                         };
 265                 };
 266
 267                 spi_pins: spi_pins {
 268                         spi_pins {
 269                                 groups = "spi";
 270                                 function = "spi";
 271                         };
 272                 };
 273
 274                 rgmii_pins: rgmii {
 275                         rgmii {
 276                                 groups = "rgmii";
 277                                 function = "rgmii";
 278                         };
 279                 };
 280
 281                 uartlite_pins: uartlite {
 282                         uart {
 283                                 groups = "uartlite";
 284                                 function = "uartlite";
 285                         };
 286                 };
 287         };
 288
 289         usbphy: usbphy {
 290                 compatible = "ralink,rt3050-usbphy";
 291                 #phy-cells = <0>;
 292
 293                 ralink,sysctl = <&sysc>;
 294                 resets = <&sysc 22>;
 295                 reset-names = "host";
 296         };
 297
 298         ethernet: ethernet@10100000 {
 299                 compatible = "ralink,rt3050-eth";
 300                 reg = <0x10100000 0x10000>;
 301
 302                 clocks = <&sysc 11>;
 303
 304                 resets = <&sysc 21>, <&sysc 23>;
 305                 reset-names = "fe", "esw";
 306
 307                 interrupt-parent = <&cpuintc>;
 308                 interrupts = <5>;
 309
 310                 mediatek,switch = <&esw>;
 311         };
 312
 313         esw: esw@10110000 {
 314                 compatible = "ralink,rt3050-esw";
 315                 reg = <0x10110000 0x8000>;
 316
 317                 resets = <&sysc 24>;
 318                 reset-names = "ephy";
 319
 320                 interrupt-parent = <&intc>;
 321                 interrupts = <17>;
 322         };
 323
 324         wmac: wmac@10180000 {
 325                 compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
 326                 reg = <0x10180000 0x40000>;
 327
 328                 clocks = <&sysc 12>;
 329
 330                 interrupt-parent = <&cpuintc>;
 331                 interrupts = <6>;
 332
 333                 ralink,eeprom = "soc_wmac.eeprom";
 334         };
 335
 336         otg: otg@101c0000 {
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 compatible = "ralink,rt3050-otg", "snps,dwc2";
 340                 reg = <0x101c0000 0x40000>;
 341
 342                 interrupt-parent = <&intc>;
 343                 interrupts = <18>;
 344
 345                 resets = <&sysc 22>;
 346                 reset-names = "otg";
 347
 348                 status = "disabled";
 349
 350                 otg_port1: port@1 {
 351                         reg = <1>;
 352                         #trigger-source-cells = <0>;
 353                 };
 354         };
 355 };