target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts

   1 #include "rt3050.dtsi"
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4
   5 / {
   6         compatible = "planex,mzk-wdpr", "ralink,rt3052-soc";
   7         model = "Planex MZK-WDPR";
   8
   9         chosen {
  10                 bootargs = "console=ttyS0,115200";
  11         };
  12
  13         flash@1f000000 {
  14                 compatible = "cfi-flash";
  15                 reg = <0x1f000000 0x800000>;
  16
  17                 bank-width = <2>;
  18                 device-width = <2>;
  19
  20                 partitions {
  21                         compatible = "fixed-partitions";
  22                         #address-cells = <1>;
  23                         #size-cells = <1>;
  24
  25                         partition@0 {
  26                                 label = "u-boot";
  27                                 reg = <0x0 0x30000>;
  28                                 read-only;
  29                         };
  30
  31                         partition@30000 {
  32                                 label = "u-boot-env";
  33                                 reg = <0x30000 0x10000>;
  34                                 read-only;
  35                         };
  36
  37                         factory: partition@40000 {
  38                                 label = "factory";
  39                                 reg = <0x40000 0x10000>;
  40                                 read-only;
  41
  42                                 nvmem-layout {
  43                                         compatible = "fixed-layout";
  44                                         #address-cells = <1>;
  45                                         #size-cells = <1>;
  46
  47                                         eeprom_factory_0: eeprom@0 {
  48                                                 reg = <0x0 0x200>;
  49                                         };
  50
  51                                         macaddr_factory_28: macaddr@28 {
  52                                                 reg = <0x28 0x6>;
  53                                         };
  54                                 };
  55                         };
  56
  57                         partition@7f0000 {
  58                                 label = "Data3G";
  59                                 reg = <0x7f0000 0x10000>;
  60                                 read-only;
  61                         };
  62
  63                         partition@50000 {
  64                                 compatible = "denx,uimage";
  65                                 label = "firmware";
  66                                 reg = <0x50000 0x680000>;
  67                         };
  68                 };
  69         };
  70
  71         gpio-export {
  72                 compatible = "gpio-export";
  73
  74                 lcd_ctrl1 {
  75                         gpio-export,name = "lcd_ctrl1";
  76                         gpio-export,output = <0>;
  77                         gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  78                 };
  79         };
  80 };
  81
  82 &state_default {
  83         gpio {
  84                 groups = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  85                 function = "gpio";
  86         };
  87 };
  88
  89 &ethernet {
  90         nvmem-cells = <&macaddr_factory_28>;
  91         nvmem-cell-names = "mac-address";
  92 };
  93
  94 &esw {
  95         mediatek,portmap = <0x2f>;
  96 };
  97
  98 &wmac {
  99         nvmem-cells = <&eeprom_factory_0>;
 100         nvmem-cell-names = "eeprom";
 101 };
 102
 103 &otg {
 104         status = "okay";
 105 };