ramips: convert mt76 PCIe NIC EEPROM to NVMEM format for legacy SoCs
[openwrt/openwrt.git] / target / linux / ramips / dts / rt3052_sitecom_wl-351.dts
1 #include "rt3050.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "sitecom,wl-351", "ralink,rt3052-soc";
8 model = "Sitecom WL-351 v1 002";
9
10 aliases {
11 led-boot = &led_power;
12 led-failsafe = &led_power;
13 led-running = &led_power;
14 led-upgrade = &led_power;
15 };
16
17 flash@1f000000 {
18 compatible = "cfi-flash";
19 reg = <0x1f000000 0x800000>;
20 bank-width = <2>;
21 device-width = <2>;
22
23 partitions {
24 compatible = "fixed-partitions";
25 #address-cells = <1>;
26 #size-cells = <1>;
27
28 partition@0 {
29 label = "u-boot";
30 reg = <0x0 0x30000>;
31 read-only;
32 };
33
34 partition@30000 {
35 label = "u-boot-env";
36 reg = <0x30000 0x10000>;
37 read-only;
38 };
39
40 factory: partition@40000 {
41 compatible = "nvmem-cells";
42 label = "factory";
43 reg = <0x40000 0x10000>;
44 #address-cells = <1>;
45 #size-cells = <1>;
46 read-only;
47
48 eeprom_factory_0: eeprom@0 {
49 reg = <0x0 0x200>;
50 };
51
52 macaddr_factory_4: macaddr@4 {
53 reg = <0x4 0x6>;
54 };
55 };
56
57 partition@50000 {
58 compatible = "denx,uimage";
59 label = "firmware";
60 reg = <0x50000 0x3b0000>;
61 };
62 };
63 };
64
65 leds {
66 compatible = "gpio-leds";
67
68 led_power: power {
69 label = "amber:power";
70 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
71 };
72
73 unpopulated {
74 label = "amber:unpopulated";
75 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
76 };
77
78 unpopulated2 {
79 label = "blue:unpopulated";
80 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
81 };
82 };
83
84 keys {
85 compatible = "gpio-keys-polled";
86 poll-interval = <20>;
87
88 reset {
89 label = "reset";
90 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
91 linux,code = <KEY_RESTART>;
92 };
93
94 wps {
95 label = "wps";
96 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
97 linux,code = <KEY_WPS_BUTTON>;
98 };
99 };
100
101 rtl8366rb {
102 compatible = "realtek,rtl8366rb";
103 gpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;
104 gpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;
105 };
106 };
107
108 &state_default {
109 gpio {
110 groups = "spi", "i2c", "jtag", "mdio", "uartf";
111 function = "gpio";
112 };
113 };
114
115 &ethernet {
116 nvmem-cells = <&macaddr_factory_4>;
117 nvmem-cell-names = "mac-address";
118 pinctrl-names = "default";
119 pinctrl-0 = <&rgmii_pins>;
120 };
121
122 &esw {
123 ralink,rgmii = <1>;
124 mediatek,portmap = <0x3f>;
125 ralink,fct2 = <0x0002500c>;
126 /*
127 * ext phy base addr 31, rx/tx clock skew 0,
128 * turbo mii off, rgmi 3.3v off, port 5 polling off
129 * port5: enabled, gige, full-duplex, rx/tx-flow-control
130 * port6: enabled, gige, full-duplex, rx/tx-flow-control
131 */
132 ralink,fpa2 = <0x1f003fff>;
133 };
134
135 &wmac {
136 nvmem-cells = <&eeprom_factory_0>;
137 nvmem-cell-names = "eeprom";
138 };
139
140 &otg {
141 status = "okay";
142 };