1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_irq.h>
22 #include <linux/switch.h>
24 #include "mtk_eth_soc.h"
26 /* HW limitations for this switch:
27 * - No large frame support (PKT_MAX_LEN at most 1536)
28 * - Can't have untagged vlan and tagged vlan on one port at the same time,
29 * though this might be possible using the undocumented PPE.
32 #define RT305X_ESW_REG_ISR 0x00
33 #define RT305X_ESW_REG_IMR 0x04
34 #define RT305X_ESW_REG_FCT0 0x08
35 #define RT305X_ESW_REG_PFC1 0x14
36 #define RT305X_ESW_REG_ATS 0x24
37 #define RT305X_ESW_REG_ATS0 0x28
38 #define RT305X_ESW_REG_ATS1 0x2c
39 #define RT305X_ESW_REG_ATS2 0x30
40 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
41 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
42 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
43 #define RT305X_ESW_REG_POA 0x80
44 #define RT305X_ESW_REG_FPA 0x84
45 #define RT305X_ESW_REG_SOCPC 0x8c
46 #define RT305X_ESW_REG_POC0 0x90
47 #define RT305X_ESW_REG_POC1 0x94
48 #define RT305X_ESW_REG_POC2 0x98
49 #define RT305X_ESW_REG_SGC 0x9c
50 #define RT305X_ESW_REG_STRT 0xa0
51 #define RT305X_ESW_REG_PCR0 0xc0
52 #define RT305X_ESW_REG_PCR1 0xc4
53 #define RT305X_ESW_REG_FPA2 0xc8
54 #define RT305X_ESW_REG_FCT2 0xcc
55 #define RT305X_ESW_REG_SGC2 0xe4
56 #define RT305X_ESW_REG_P0LED 0xa4
57 #define RT305X_ESW_REG_P1LED 0xa8
58 #define RT305X_ESW_REG_P2LED 0xac
59 #define RT305X_ESW_REG_P3LED 0xb0
60 #define RT305X_ESW_REG_P4LED 0xb4
61 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
62 #define RT305X_ESW_REG_P1PC 0xec
63 #define RT305X_ESW_REG_P2PC 0xf0
64 #define RT305X_ESW_REG_P3PC 0xf4
65 #define RT305X_ESW_REG_P4PC 0xf8
66 #define RT305X_ESW_REG_P5PC 0xfc
68 #define RT305X_ESW_LED_LINK 0
69 #define RT305X_ESW_LED_100M 1
70 #define RT305X_ESW_LED_DUPLEX 2
71 #define RT305X_ESW_LED_ACTIVITY 3
72 #define RT305X_ESW_LED_COLLISION 4
73 #define RT305X_ESW_LED_LINKACT 5
74 #define RT305X_ESW_LED_DUPLCOLL 6
75 #define RT305X_ESW_LED_10MACT 7
76 #define RT305X_ESW_LED_100MACT 8
77 /* Additional led states not in datasheet: */
78 #define RT305X_ESW_LED_BLINK 10
79 #define RT305X_ESW_LED_ON 12
81 #define RT305X_ESW_LINK_S 25
82 #define RT305X_ESW_DUPLEX_S 9
83 #define RT305X_ESW_SPD_S 0
85 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
86 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
87 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
89 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
91 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
92 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
94 #define RT305X_ESW_PVIDC_PVID_M 0xfff
95 #define RT305X_ESW_PVIDC_PVID_S 12
97 #define RT305X_ESW_VLANI_VID_M 0xfff
98 #define RT305X_ESW_VLANI_VID_S 12
100 #define RT305X_ESW_VMSC_MSC_M 0xff
101 #define RT305X_ESW_VMSC_MSC_S 8
103 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
104 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
105 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
106 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
108 #define RT305X_ESW_POC0_EN_BP_S 0
109 #define RT305X_ESW_POC0_EN_FC_S 8
110 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
111 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
112 #define RT305X_ESW_POC0_DIS_PORT_S 23
114 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
115 #define RT305X_ESW_POC2_UNTAG_EN_S 0
116 #define RT305X_ESW_POC2_ENAGING_S 8
117 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
119 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
120 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
121 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
122 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
124 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
125 #define RT305X_ESW_PFC1_EN_VLAN_S 16
126 #define RT305X_ESW_PFC1_EN_TOS_S 24
128 #define RT305X_ESW_VLAN_NONE 0xfff
130 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
131 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
133 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
134 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
136 #define RT305X_ESW_POA_LINK_MASK 0x1f
137 #define RT305X_ESW_POA_LINK_SHIFT 25
139 #define RT305X_ESW_PORT_ST_CHG BIT(26)
140 #define RT305X_ESW_PORT0 0
141 #define RT305X_ESW_PORT1 1
142 #define RT305X_ESW_PORT2 2
143 #define RT305X_ESW_PORT3 3
144 #define RT305X_ESW_PORT4 4
145 #define RT305X_ESW_PORT5 5
146 #define RT305X_ESW_PORT6 6
148 #define RT305X_ESW_PORTS_NONE 0
150 #define RT305X_ESW_PMAP_LLLLLL 0x3f
151 #define RT305X_ESW_PMAP_LLLLWL 0x2f
152 #define RT305X_ESW_PMAP_WLLLLL 0x3e
154 #define RT305X_ESW_PORTS_INTERNAL \
155 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
156 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
157 BIT(RT305X_ESW_PORT4))
159 #define RT305X_ESW_PORTS_NOCPU \
160 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
162 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
164 #define RT305X_ESW_PORTS_ALL \
165 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
167 #define RT305X_ESW_NUM_VLANS 16
168 #define RT305X_ESW_NUM_VIDS 4096
169 #define RT305X_ESW_NUM_PORTS 7
170 #define RT305X_ESW_NUM_LANWAN 6
171 #define RT305X_ESW_NUM_LEDS 5
173 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
174 #define RT5350_EWS_REG_LED_POLARITY 0x168
175 #define RT5350_RESET_EPHY BIT(24)
178 /* Global attributes. */
179 RT305X_ESW_ATTR_ENABLE_VLAN
,
180 RT305X_ESW_ATTR_ALT_VLAN_DISABLE
,
181 RT305X_ESW_ATTR_BC_STATUS
,
182 RT305X_ESW_ATTR_LED_FREQ
,
183 /* Port attributes. */
184 RT305X_ESW_ATTR_PORT_DISABLE
,
185 RT305X_ESW_ATTR_PORT_DOUBLETAG
,
186 RT305X_ESW_ATTR_PORT_UNTAG
,
187 RT305X_ESW_ATTR_PORT_LED
,
188 RT305X_ESW_ATTR_PORT_LAN
,
189 RT305X_ESW_ATTR_PORT_RECV_BAD
,
190 RT305X_ESW_ATTR_PORT_RECV_GOOD
,
191 RT5350_ESW_ATTR_PORT_TR_BAD
,
192 RT5350_ESW_ATTR_PORT_TR_GOOD
,
209 RT305X_ESW_VLAN_CONFIG_NONE
= 0,
210 RT305X_ESW_VLAN_CONFIG_LLLLW
,
211 RT305X_ESW_VLAN_CONFIG_WLLLL
,
219 /* Protects against concurrent register r/w operations. */
220 spinlock_t reg_rw_lock
;
222 unsigned char port_map
;
223 unsigned char port_disable
;
224 unsigned int reg_initval_fct2
;
225 unsigned int reg_initval_fpa2
;
226 unsigned int reg_led_polarity
;
228 struct switch_dev swdev
;
229 bool global_vlan_enable
;
230 bool alt_vlan_disable
;
231 int bc_storm_protect
;
233 struct esw_vlan vlans
[RT305X_ESW_NUM_VLANS
];
234 struct esw_port ports
[RT305X_ESW_NUM_PORTS
];
238 static inline void esw_w32(struct rt305x_esw
*esw
, u32 val
, unsigned reg
)
240 __raw_writel(val
, esw
->base
+ reg
);
243 static inline u32
esw_r32(struct rt305x_esw
*esw
, unsigned reg
)
245 return __raw_readl(esw
->base
+ reg
);
248 static inline void esw_rmw_raw(struct rt305x_esw
*esw
, unsigned reg
,
249 unsigned long mask
, unsigned long val
)
253 t
= __raw_readl(esw
->base
+ reg
) & ~mask
;
254 __raw_writel(t
| val
, esw
->base
+ reg
);
257 static void esw_rmw(struct rt305x_esw
*esw
, unsigned reg
,
258 unsigned long mask
, unsigned long val
)
262 spin_lock_irqsave(&esw
->reg_rw_lock
, flags
);
263 esw_rmw_raw(esw
, reg
, mask
, val
);
264 spin_unlock_irqrestore(&esw
->reg_rw_lock
, flags
);
267 static u32
rt305x_mii_write(struct rt305x_esw
*esw
, u32 phy_addr
,
268 u32 phy_register
, u32 write_data
)
270 unsigned long t_start
= jiffies
;
274 if (!(esw_r32(esw
, RT305X_ESW_REG_PCR1
) &
275 RT305X_ESW_PCR1_WT_DONE
))
277 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
283 write_data
&= 0xffff;
284 esw_w32(esw
, (write_data
<< RT305X_ESW_PCR0_WT_NWAY_DATA_S
) |
285 (phy_register
<< RT305X_ESW_PCR0_CPU_PHY_REG_S
) |
286 (phy_addr
) | RT305X_ESW_PCR0_WT_PHY_CMD
,
287 RT305X_ESW_REG_PCR0
);
291 if (esw_r32(esw
, RT305X_ESW_REG_PCR1
) &
292 RT305X_ESW_PCR1_WT_DONE
)
295 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
302 dev_err(esw
->dev
, "ramips_eth: MDIO timeout\n");
306 static unsigned esw_get_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
)
311 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
312 val
= esw_r32(esw
, RT305X_ESW_REG_VLANI(vlan
/ 2));
313 val
= (val
>> s
) & RT305X_ESW_VLANI_VID_M
;
318 static void esw_set_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
, unsigned vid
)
322 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
324 RT305X_ESW_REG_VLANI(vlan
/ 2),
325 RT305X_ESW_VLANI_VID_M
<< s
,
326 (vid
& RT305X_ESW_VLANI_VID_M
) << s
);
329 static unsigned esw_get_pvid(struct rt305x_esw
*esw
, unsigned port
)
333 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
334 val
= esw_r32(esw
, RT305X_ESW_REG_PVIDC(port
/ 2));
335 return (val
>> s
) & RT305X_ESW_PVIDC_PVID_M
;
338 static void esw_set_pvid(struct rt305x_esw
*esw
, unsigned port
, unsigned pvid
)
342 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
344 RT305X_ESW_REG_PVIDC(port
/ 2),
345 RT305X_ESW_PVIDC_PVID_M
<< s
,
346 (pvid
& RT305X_ESW_PVIDC_PVID_M
) << s
);
349 static unsigned esw_get_vmsc(struct rt305x_esw
*esw
, unsigned vlan
)
353 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
354 val
= esw_r32(esw
, RT305X_ESW_REG_VMSC(vlan
/ 4));
355 val
= (val
>> s
) & RT305X_ESW_VMSC_MSC_M
;
360 static void esw_set_vmsc(struct rt305x_esw
*esw
, unsigned vlan
, unsigned msc
)
364 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
366 RT305X_ESW_REG_VMSC(vlan
/ 4),
367 RT305X_ESW_VMSC_MSC_M
<< s
,
368 (msc
& RT305X_ESW_VMSC_MSC_M
) << s
);
371 static unsigned esw_get_port_disable(struct rt305x_esw
*esw
)
375 reg
= esw_r32(esw
, RT305X_ESW_REG_POC0
);
376 return (reg
>> RT305X_ESW_POC0_DIS_PORT_S
) &
377 RT305X_ESW_POC0_DIS_PORT_M
;
380 static void esw_set_port_disable(struct rt305x_esw
*esw
, unsigned disable_mask
)
383 unsigned enable_mask
;
387 old_mask
= esw_get_port_disable(esw
);
388 changed
= old_mask
^ disable_mask
;
389 enable_mask
= old_mask
& disable_mask
;
391 /* enable before writing to MII */
392 esw_rmw(esw
, RT305X_ESW_REG_POC0
,
393 (RT305X_ESW_POC0_DIS_PORT_M
<<
394 RT305X_ESW_POC0_DIS_PORT_S
),
395 enable_mask
<< RT305X_ESW_POC0_DIS_PORT_S
);
397 for (i
= 0; i
< RT305X_ESW_NUM_LEDS
; i
++) {
398 if (!(changed
& (1 << i
)))
400 if (disable_mask
& (1 << i
)) {
402 rt305x_mii_write(esw
, i
, MII_BMCR
,
406 rt305x_mii_write(esw
, i
, MII_BMCR
,
414 /* disable after writing to MII */
415 esw_rmw(esw
, RT305X_ESW_REG_POC0
,
416 (RT305X_ESW_POC0_DIS_PORT_M
<<
417 RT305X_ESW_POC0_DIS_PORT_S
),
418 disable_mask
<< RT305X_ESW_POC0_DIS_PORT_S
);
421 static void esw_set_gsc(struct rt305x_esw
*esw
)
423 esw_rmw(esw
, RT305X_ESW_REG_SGC
,
424 RT305X_ESW_GSC_BC_STROM_MASK
<< RT305X_ESW_GSC_BC_STROM_SHIFT
,
425 esw
->bc_storm_protect
<< RT305X_ESW_GSC_BC_STROM_SHIFT
);
426 esw_rmw(esw
, RT305X_ESW_REG_SGC
,
427 RT305X_ESW_GSC_LED_FREQ_MASK
<< RT305X_ESW_GSC_LED_FREQ_SHIFT
,
428 esw
->led_frequency
<< RT305X_ESW_GSC_LED_FREQ_SHIFT
);
431 static int esw_apply_config(struct switch_dev
*dev
);
433 static void esw_hw_init(struct rt305x_esw
*esw
)
437 u8 port_map
= RT305X_ESW_PMAP_LLLLLL
;
439 /* vodoo from original driver */
440 esw_w32(esw
, 0xC8A07850, RT305X_ESW_REG_FCT0
);
441 esw_w32(esw
, 0x00000000, RT305X_ESW_REG_SGC2
);
442 /* Port priority 1 for all ports, vlan enabled. */
443 esw_w32(esw
, 0x00005555 |
444 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_PFC1_EN_VLAN_S
),
445 RT305X_ESW_REG_PFC1
);
447 /* Enable all ports, Back Pressure and Flow Control */
448 esw_w32(esw
, ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC0_EN_BP_S
) |
449 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC0_EN_FC_S
)),
450 RT305X_ESW_REG_POC0
);
452 /* Enable Aging, and VLAN TAG removal */
453 esw_w32(esw
, ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC2_ENAGING_S
) |
454 (RT305X_ESW_PORTS_NOCPU
<< RT305X_ESW_POC2_UNTAG_EN_S
)),
455 RT305X_ESW_REG_POC2
);
457 if (esw
->reg_initval_fct2
)
458 esw_w32(esw
, esw
->reg_initval_fct2
, RT305X_ESW_REG_FCT2
);
460 esw_w32(esw
, 0x0002500c, RT305X_ESW_REG_FCT2
);
462 /* 300s aging timer, max packet len 1536, broadcast storm prevention
463 * disabled, disable collision abort, mac xor48 hash, 10 packet back
464 * pressure jam, GMII disable was_transmit, back pressure disabled,
465 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
468 esw_w32(esw
, 0x0008a301, RT305X_ESW_REG_SGC
);
470 /* Setup SoC Port control register */
472 (RT305X_ESW_SOCPC_CRC_PADDING
|
473 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISUN2CPU_S
) |
474 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISMC2CPU_S
) |
475 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISBC2CPU_S
)),
476 RT305X_ESW_REG_SOCPC
);
478 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
479 * turbo mii off, rgmi 3.3v off
481 * port6: enabled, gige, full-duplex, rx/tx-flow-control
483 if (esw
->reg_initval_fpa2
)
484 esw_w32(esw
, esw
->reg_initval_fpa2
, RT305X_ESW_REG_FPA2
);
486 esw_w32(esw
, 0x3f502b28, RT305X_ESW_REG_FPA2
);
487 esw_w32(esw
, 0x00000000, RT305X_ESW_REG_FPA
);
489 /* Force Link/Activity on ports */
490 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P0LED
);
491 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P1LED
);
492 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P2LED
);
493 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P3LED
);
494 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P4LED
);
496 /* Copy disabled port configuration from device tree setup */
497 port_disable
= esw
->port_disable
;
499 /* Disable nonexistent ports by reading the switch config
500 * after having enabled all possible ports above
502 port_disable
|= esw_get_port_disable(esw
);
504 for (i
= 0; i
< 6; i
++)
505 esw
->ports
[i
].disable
= (port_disable
& (1 << i
)) != 0;
507 if (ralink_soc
== RT305X_SOC_RT3352
) {
509 fe_reset(RT5350_RESET_EPHY
);
511 rt305x_mii_write(esw
, 0, 31, 0x8000);
512 for (i
= 0; i
< 5; i
++) {
513 if (esw
->ports
[i
].disable
) {
514 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
516 rt305x_mii_write(esw
, i
, MII_BMCR
,
521 /* TX10 waveform coefficient LSB=0 disable PHY */
522 rt305x_mii_write(esw
, i
, 26, 0x1601);
523 /* TX100/TX10 AD/DA current bias */
524 rt305x_mii_write(esw
, i
, 29, 0x7016);
525 /* TX100 slew rate control */
526 rt305x_mii_write(esw
, i
, 30, 0x0038);
529 /* select global register */
530 rt305x_mii_write(esw
, 0, 31, 0x0);
531 /* enlarge agcsel threshold 3 and threshold 2 */
532 rt305x_mii_write(esw
, 0, 1, 0x4a40);
533 /* enlarge agcsel threshold 5 and threshold 4 */
534 rt305x_mii_write(esw
, 0, 2, 0x6254);
535 /* enlarge agcsel threshold */
536 rt305x_mii_write(esw
, 0, 3, 0xa17f);
537 rt305x_mii_write(esw
, 0, 12, 0x7eaa);
538 /* longer TP_IDL tail length */
539 rt305x_mii_write(esw
, 0, 14, 0x65);
540 /* increased squelch pulse count threshold. */
541 rt305x_mii_write(esw
, 0, 16, 0x0684);
542 /* set TX10 signal amplitude threshold to minimum */
543 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
544 /* set squelch amplitude to higher threshold */
545 rt305x_mii_write(esw
, 0, 18, 0x40ba);
546 /* tune TP_IDL tail and head waveform, enable power
547 * down slew rate control
549 rt305x_mii_write(esw
, 0, 22, 0x253f);
550 /* set PLL/Receive bias current are calibrated */
551 rt305x_mii_write(esw
, 0, 27, 0x2fda);
552 /* change PLL/Receive bias current to internal(RT3350) */
553 rt305x_mii_write(esw
, 0, 28, 0xc410);
554 /* change PLL bias current to internal(RT3052_MP3) */
555 rt305x_mii_write(esw
, 0, 29, 0x598b);
556 /* select local register */
557 rt305x_mii_write(esw
, 0, 31, 0x8000);
558 } else if (ralink_soc
== RT305X_SOC_RT5350
) {
560 fe_reset(RT5350_RESET_EPHY
);
562 /* set the led polarity */
563 esw_w32(esw
, esw
->reg_led_polarity
& 0x1F,
564 RT5350_EWS_REG_LED_POLARITY
);
566 /* local registers */
567 rt305x_mii_write(esw
, 0, 31, 0x8000);
568 for (i
= 0; i
< 5; i
++) {
569 if (esw
->ports
[i
].disable
) {
570 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
572 rt305x_mii_write(esw
, i
, MII_BMCR
,
577 /* TX10 waveform coefficient LSB=0 disable PHY */
578 rt305x_mii_write(esw
, i
, 26, 0x1601);
579 /* TX100/TX10 AD/DA current bias */
580 rt305x_mii_write(esw
, i
, 29, 0x7015);
581 /* TX100 slew rate control */
582 rt305x_mii_write(esw
, i
, 30, 0x0038);
585 /* global registers */
586 rt305x_mii_write(esw
, 0, 31, 0x0);
587 /* enlarge agcsel threshold 3 and threshold 2 */
588 rt305x_mii_write(esw
, 0, 1, 0x4a40);
589 /* enlarge agcsel threshold 5 and threshold 4 */
590 rt305x_mii_write(esw
, 0, 2, 0x6254);
591 /* enlarge agcsel threshold 6 */
592 rt305x_mii_write(esw
, 0, 3, 0xa17f);
593 rt305x_mii_write(esw
, 0, 12, 0x7eaa);
594 /* longer TP_IDL tail length */
595 rt305x_mii_write(esw
, 0, 14, 0x65);
596 /* increased squelch pulse count threshold. */
597 rt305x_mii_write(esw
, 0, 16, 0x0684);
598 /* set TX10 signal amplitude threshold to minimum */
599 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
600 /* set squelch amplitude to higher threshold */
601 rt305x_mii_write(esw
, 0, 18, 0x40ba);
602 /* tune TP_IDL tail and head waveform, enable power
603 * down slew rate control
605 rt305x_mii_write(esw
, 0, 22, 0x253f);
606 /* set PLL/Receive bias current are calibrated */
607 rt305x_mii_write(esw
, 0, 27, 0x2fda);
608 /* change PLL/Receive bias current to internal(RT3350) */
609 rt305x_mii_write(esw
, 0, 28, 0xc410);
610 /* change PLL bias current to internal(RT3052_MP3) */
611 rt305x_mii_write(esw
, 0, 29, 0x598b);
612 /* select local register */
613 rt305x_mii_write(esw
, 0, 31, 0x8000);
614 } else if (ralink_soc
== MT762X_SOC_MT7628AN
|| ralink_soc
== MT762X_SOC_MT7688
) {
618 fe_reset(RT5350_RESET_EPHY
);
620 /* set the led polarity */
621 esw_w32(esw
, esw
->reg_led_polarity
& 0x1F,
622 RT5350_EWS_REG_LED_POLARITY
);
624 rt305x_mii_write(esw
, 0, 31, 0x2000); /* change G2 page */
625 rt305x_mii_write(esw
, 0, 26, 0x0020);
627 for (i
= 0; i
< 5; i
++) {
628 rt305x_mii_write(esw
, i
, 31, 0x8000);
629 rt305x_mii_write(esw
, i
, 0, 0x3100);
630 rt305x_mii_write(esw
, i
, 30, 0xa000);
631 rt305x_mii_write(esw
, i
, 31, 0xa000);
632 rt305x_mii_write(esw
, i
, 16, 0x0606);
633 rt305x_mii_write(esw
, i
, 23, 0x0f0e);
634 rt305x_mii_write(esw
, i
, 24, 0x1610);
635 rt305x_mii_write(esw
, i
, 30, 0x1f15);
636 rt305x_mii_write(esw
, i
, 28, 0x6111);
637 rt305x_mii_write(esw
, i
, 31, 0x2000);
638 rt305x_mii_write(esw
, i
, 26, 0x0000);
641 /* 100Base AOI setting */
642 rt305x_mii_write(esw
, 0, 31, 0x5000);
643 rt305x_mii_write(esw
, 0, 19, 0x004a);
644 rt305x_mii_write(esw
, 0, 20, 0x015a);
645 rt305x_mii_write(esw
, 0, 21, 0x00ee);
646 rt305x_mii_write(esw
, 0, 22, 0x0033);
647 rt305x_mii_write(esw
, 0, 23, 0x020a);
648 rt305x_mii_write(esw
, 0, 24, 0x0000);
649 rt305x_mii_write(esw
, 0, 25, 0x024a);
650 rt305x_mii_write(esw
, 0, 26, 0x035a);
651 rt305x_mii_write(esw
, 0, 27, 0x02ee);
652 rt305x_mii_write(esw
, 0, 28, 0x0233);
653 rt305x_mii_write(esw
, 0, 29, 0x000a);
654 rt305x_mii_write(esw
, 0, 30, 0x0000);
656 rt305x_mii_write(esw
, 0, 31, 0x8000);
657 for (i
= 0; i
< 5; i
++) {
658 if (esw
->ports
[i
].disable
) {
659 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
661 rt305x_mii_write(esw
, i
, MII_BMCR
,
666 /* TX10 waveform coefficient */
667 rt305x_mii_write(esw
, i
, 26, 0x1601);
668 /* TX100/TX10 AD/DA current bias */
669 rt305x_mii_write(esw
, i
, 29, 0x7058);
670 /* TX100 slew rate control */
671 rt305x_mii_write(esw
, i
, 30, 0x0018);
675 /* select global register */
676 rt305x_mii_write(esw
, 0, 31, 0x0);
677 /* tune TP_IDL tail and head waveform */
678 rt305x_mii_write(esw
, 0, 22, 0x052f);
679 /* set TX10 signal amplitude threshold to minimum */
680 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
681 /* set squelch amplitude to higher threshold */
682 rt305x_mii_write(esw
, 0, 18, 0x40ba);
683 /* longer TP_IDL tail length */
684 rt305x_mii_write(esw
, 0, 14, 0x65);
685 /* select local register */
686 rt305x_mii_write(esw
, 0, 31, 0x8000);
690 port_map
= esw
->port_map
;
692 port_map
= RT305X_ESW_PMAP_LLLLLL
;
694 /* Unused HW feature, but still nice to be consistent here...
695 * This is also exported to userspace ('lan' attribute) so it's
696 * conveniently usable to decide which ports go into the wan vlan by
699 esw_rmw(esw
, RT305X_ESW_REG_SGC2
,
700 RT305X_ESW_SGC2_LAN_PMAP_M
<< RT305X_ESW_SGC2_LAN_PMAP_S
,
701 port_map
<< RT305X_ESW_SGC2_LAN_PMAP_S
);
703 /* make the switch leds blink */
704 for (i
= 0; i
< RT305X_ESW_NUM_LEDS
; i
++)
705 esw
->ports
[i
].led
= 0x05;
707 /* Apply the empty config. */
708 esw_apply_config(&esw
->swdev
);
710 /* Only unmask the port change interrupt */
711 esw_w32(esw
, ~RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_IMR
);
714 static irqreturn_t
esw_interrupt(int irq
, void *_esw
)
716 struct rt305x_esw
*esw
= (struct rt305x_esw
*)_esw
;
719 status
= esw_r32(esw
, RT305X_ESW_REG_ISR
);
720 if (status
& RT305X_ESW_PORT_ST_CHG
) {
721 u32 link
= esw_r32(esw
, RT305X_ESW_REG_POA
);
723 link
>>= RT305X_ESW_POA_LINK_SHIFT
;
724 link
&= RT305X_ESW_POA_LINK_MASK
;
725 dev_info(esw
->dev
, "link changed 0x%02X\n", link
);
727 esw_w32(esw
, status
, RT305X_ESW_REG_ISR
);
732 static int esw_apply_config(struct switch_dev
*dev
)
734 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
741 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
743 if (esw
->global_vlan_enable
) {
744 vid
= esw
->vlans
[i
].vid
;
745 vmsc
= esw
->vlans
[i
].ports
;
747 vid
= RT305X_ESW_VLAN_NONE
;
748 vmsc
= RT305X_ESW_PORTS_NONE
;
750 esw_set_vlan_id(esw
, i
, vid
);
751 esw_set_vmsc(esw
, i
, vmsc
);
754 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++) {
756 disable
|= esw
->ports
[i
].disable
<< i
;
757 if (esw
->global_vlan_enable
) {
758 doubletag
|= esw
->ports
[i
].doubletag
<< i
;
760 untag
|= esw
->ports
[i
].untag
<< i
;
761 pvid
= esw
->ports
[i
].pvid
;
763 int x
= esw
->alt_vlan_disable
? 0 : 1;
769 esw_set_pvid(esw
, i
, pvid
);
770 if (i
< RT305X_ESW_NUM_LEDS
)
771 esw_w32(esw
, esw
->ports
[i
].led
,
772 RT305X_ESW_REG_P0LED
+ 4*i
);
776 esw_set_port_disable(esw
, disable
);
777 esw_rmw(esw
, RT305X_ESW_REG_SGC2
,
778 (RT305X_ESW_SGC2_DOUBLE_TAG_M
<<
779 RT305X_ESW_SGC2_DOUBLE_TAG_S
),
780 doubletag
<< RT305X_ESW_SGC2_DOUBLE_TAG_S
);
781 esw_rmw(esw
, RT305X_ESW_REG_PFC1
,
782 RT305X_ESW_PFC1_EN_VLAN_M
<< RT305X_ESW_PFC1_EN_VLAN_S
,
783 en_vlan
<< RT305X_ESW_PFC1_EN_VLAN_S
);
784 esw_rmw(esw
, RT305X_ESW_REG_POC2
,
785 RT305X_ESW_POC2_UNTAG_EN_M
<< RT305X_ESW_POC2_UNTAG_EN_S
,
786 untag
<< RT305X_ESW_POC2_UNTAG_EN_S
);
788 if (!esw
->global_vlan_enable
) {
790 * Still need to put all ports into vlan 0 or they'll be
792 * NOTE: vlan 0 is special, no vlan tag is prepended
794 esw_set_vlan_id(esw
, 0, 0);
795 esw_set_vmsc(esw
, 0, RT305X_ESW_PORTS_ALL
);
801 static int esw_reset_switch(struct switch_dev
*dev
)
803 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
805 esw
->global_vlan_enable
= 0;
806 memset(esw
->ports
, 0, sizeof(esw
->ports
));
807 memset(esw
->vlans
, 0, sizeof(esw
->vlans
));
813 static int esw_get_vlan_enable(struct switch_dev
*dev
,
814 const struct switch_attr
*attr
,
815 struct switch_val
*val
)
817 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
819 val
->value
.i
= esw
->global_vlan_enable
;
824 static int esw_set_vlan_enable(struct switch_dev
*dev
,
825 const struct switch_attr
*attr
,
826 struct switch_val
*val
)
828 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
830 esw
->global_vlan_enable
= val
->value
.i
!= 0;
835 static int esw_get_alt_vlan_disable(struct switch_dev
*dev
,
836 const struct switch_attr
*attr
,
837 struct switch_val
*val
)
839 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
841 val
->value
.i
= esw
->alt_vlan_disable
;
846 static int esw_set_alt_vlan_disable(struct switch_dev
*dev
,
847 const struct switch_attr
*attr
,
848 struct switch_val
*val
)
850 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
852 esw
->alt_vlan_disable
= val
->value
.i
!= 0;
858 rt305x_esw_set_bc_status(struct switch_dev
*dev
,
859 const struct switch_attr
*attr
,
860 struct switch_val
*val
)
862 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
864 esw
->bc_storm_protect
= val
->value
.i
& RT305X_ESW_GSC_BC_STROM_MASK
;
870 rt305x_esw_get_bc_status(struct switch_dev
*dev
,
871 const struct switch_attr
*attr
,
872 struct switch_val
*val
)
874 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
876 val
->value
.i
= esw
->bc_storm_protect
;
882 rt305x_esw_set_led_freq(struct switch_dev
*dev
,
883 const struct switch_attr
*attr
,
884 struct switch_val
*val
)
886 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
888 esw
->led_frequency
= val
->value
.i
& RT305X_ESW_GSC_LED_FREQ_MASK
;
894 rt305x_esw_get_led_freq(struct switch_dev
*dev
,
895 const struct switch_attr
*attr
,
896 struct switch_val
*val
)
898 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
900 val
->value
.i
= esw
->led_frequency
;
905 static int esw_get_port_link(struct switch_dev
*dev
,
907 struct switch_port_link
*link
)
909 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
912 if (port
< 0 || port
>= RT305X_ESW_NUM_PORTS
)
915 poa
= esw_r32(esw
, RT305X_ESW_REG_POA
) >> port
;
917 link
->link
= (poa
>> RT305X_ESW_LINK_S
) & 1;
918 link
->duplex
= (poa
>> RT305X_ESW_DUPLEX_S
) & 1;
919 if (port
< RT305X_ESW_NUM_LEDS
) {
920 speed
= (poa
>> RT305X_ESW_SPD_S
) & 1;
922 if (port
== RT305X_ESW_NUM_PORTS
- 1)
924 speed
= (poa
>> RT305X_ESW_SPD_S
) & 3;
928 link
->speed
= SWITCH_PORT_SPEED_10
;
931 link
->speed
= SWITCH_PORT_SPEED_100
;
934 case 3: /* forced gige speed can be 2 or 3 */
935 link
->speed
= SWITCH_PORT_SPEED_1000
;
938 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
945 static int esw_get_port_bool(struct switch_dev
*dev
,
946 const struct switch_attr
*attr
,
947 struct switch_val
*val
)
949 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
950 int idx
= val
->port_vlan
;
953 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
)
957 case RT305X_ESW_ATTR_PORT_DISABLE
:
958 reg
= RT305X_ESW_REG_POC0
;
959 shift
= RT305X_ESW_POC0_DIS_PORT_S
;
961 case RT305X_ESW_ATTR_PORT_DOUBLETAG
:
962 reg
= RT305X_ESW_REG_SGC2
;
963 shift
= RT305X_ESW_SGC2_DOUBLE_TAG_S
;
965 case RT305X_ESW_ATTR_PORT_UNTAG
:
966 reg
= RT305X_ESW_REG_POC2
;
967 shift
= RT305X_ESW_POC2_UNTAG_EN_S
;
969 case RT305X_ESW_ATTR_PORT_LAN
:
970 reg
= RT305X_ESW_REG_SGC2
;
971 shift
= RT305X_ESW_SGC2_LAN_PMAP_S
;
972 if (idx
>= RT305X_ESW_NUM_LANWAN
)
979 x
= esw_r32(esw
, reg
);
980 val
->value
.i
= (x
>> (idx
+ shift
)) & 1;
985 static int esw_set_port_bool(struct switch_dev
*dev
,
986 const struct switch_attr
*attr
,
987 struct switch_val
*val
)
989 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
990 int idx
= val
->port_vlan
;
992 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
||
993 val
->value
.i
< 0 || val
->value
.i
> 1)
997 case RT305X_ESW_ATTR_PORT_DISABLE
:
998 esw
->ports
[idx
].disable
= val
->value
.i
;
1000 case RT305X_ESW_ATTR_PORT_DOUBLETAG
:
1001 esw
->ports
[idx
].doubletag
= val
->value
.i
;
1003 case RT305X_ESW_ATTR_PORT_UNTAG
:
1004 esw
->ports
[idx
].untag
= val
->value
.i
;
1013 static int esw_get_port_recv_badgood(struct switch_dev
*dev
,
1014 const struct switch_attr
*attr
,
1015 struct switch_val
*val
)
1017 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1018 int idx
= val
->port_vlan
;
1019 int shift
= attr
->id
== RT305X_ESW_ATTR_PORT_RECV_GOOD
? 0 : 16;
1022 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LANWAN
)
1024 reg
= esw_r32(esw
, RT305X_ESW_REG_PXPC(idx
));
1025 val
->value
.i
= (reg
>> shift
) & 0xffff;
1031 esw_get_port_tr_badgood(struct switch_dev
*dev
,
1032 const struct switch_attr
*attr
,
1033 struct switch_val
*val
)
1035 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1037 int idx
= val
->port_vlan
;
1038 int shift
= attr
->id
== RT5350_ESW_ATTR_PORT_TR_GOOD
? 0 : 16;
1041 if ((ralink_soc
!= RT305X_SOC_RT5350
) && (ralink_soc
!= MT762X_SOC_MT7628AN
) && (ralink_soc
!= MT762X_SOC_MT7688
))
1044 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LANWAN
)
1047 reg
= esw_r32(esw
, RT5350_ESW_REG_PXTPC(idx
));
1048 val
->value
.i
= (reg
>> shift
) & 0xffff;
1053 static int esw_get_port_led(struct switch_dev
*dev
,
1054 const struct switch_attr
*attr
,
1055 struct switch_val
*val
)
1057 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1058 int idx
= val
->port_vlan
;
1060 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
||
1061 idx
>= RT305X_ESW_NUM_LEDS
)
1064 val
->value
.i
= esw_r32(esw
, RT305X_ESW_REG_P0LED
+ 4*idx
);
1069 static int esw_set_port_led(struct switch_dev
*dev
,
1070 const struct switch_attr
*attr
,
1071 struct switch_val
*val
)
1073 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1074 int idx
= val
->port_vlan
;
1076 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LEDS
)
1079 esw
->ports
[idx
].led
= val
->value
.i
;
1084 static int esw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1086 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1088 if (port
>= RT305X_ESW_NUM_PORTS
)
1091 *val
= esw_get_pvid(esw
, port
);
1096 static int esw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1098 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1100 if (port
>= RT305X_ESW_NUM_PORTS
)
1103 esw
->ports
[port
].pvid
= val
;
1108 static int esw_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1110 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1117 if (val
->port_vlan
< 0 || val
->port_vlan
>= RT305X_ESW_NUM_VIDS
)
1121 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
1122 if (esw_get_vlan_id(esw
, i
) == val
->port_vlan
&&
1123 esw_get_vmsc(esw
, i
) != RT305X_ESW_PORTS_NONE
) {
1132 vmsc
= esw_get_vmsc(esw
, vlan_idx
);
1133 poc2
= esw_r32(esw
, RT305X_ESW_REG_POC2
);
1135 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++) {
1136 struct switch_port
*p
;
1137 int port_mask
= 1 << i
;
1139 if (!(vmsc
& port_mask
))
1142 p
= &val
->value
.ports
[val
->len
++];
1144 if (poc2
& (port_mask
<< RT305X_ESW_POC2_UNTAG_EN_S
))
1147 p
->flags
= 1 << SWITCH_PORT_FLAG_TAGGED
;
1153 static int esw_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1155 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1160 if (val
->port_vlan
< 0 || val
->port_vlan
>= RT305X_ESW_NUM_VIDS
||
1161 val
->len
> RT305X_ESW_NUM_PORTS
)
1164 /* one of the already defined vlans? */
1165 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
1166 if (esw
->vlans
[i
].vid
== val
->port_vlan
&&
1167 esw
->vlans
[i
].ports
!= RT305X_ESW_PORTS_NONE
) {
1173 /* select a free slot */
1174 for (i
= 0; vlan_idx
== -1 && i
< RT305X_ESW_NUM_VLANS
; i
++) {
1175 if (esw
->vlans
[i
].ports
== RT305X_ESW_PORTS_NONE
)
1179 /* bail if all slots are in use */
1183 ports
= RT305X_ESW_PORTS_NONE
;
1184 for (i
= 0; i
< val
->len
; i
++) {
1185 struct switch_port
*p
= &val
->value
.ports
[i
];
1186 int port_mask
= 1 << p
->id
;
1187 bool untagged
= !(p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
));
1189 if (p
->id
>= RT305X_ESW_NUM_PORTS
)
1193 esw
->ports
[p
->id
].untag
= untagged
;
1195 esw
->vlans
[vlan_idx
].ports
= ports
;
1196 if (ports
== RT305X_ESW_PORTS_NONE
)
1197 esw
->vlans
[vlan_idx
].vid
= RT305X_ESW_VLAN_NONE
;
1199 esw
->vlans
[vlan_idx
].vid
= val
->port_vlan
;
1204 static const struct switch_attr esw_global
[] = {
1206 .type
= SWITCH_TYPE_INT
,
1207 .name
= "enable_vlan",
1208 .description
= "VLAN mode (1:enabled)",
1210 .id
= RT305X_ESW_ATTR_ENABLE_VLAN
,
1211 .get
= esw_get_vlan_enable
,
1212 .set
= esw_set_vlan_enable
,
1215 .type
= SWITCH_TYPE_INT
,
1216 .name
= "alternate_vlan_disable",
1217 .description
= "Use en_vlan instead of doubletag to disable"
1220 .id
= RT305X_ESW_ATTR_ALT_VLAN_DISABLE
,
1221 .get
= esw_get_alt_vlan_disable
,
1222 .set
= esw_set_alt_vlan_disable
,
1225 .type
= SWITCH_TYPE_INT
,
1226 .name
= "bc_storm_protect",
1227 .description
= "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1229 .id
= RT305X_ESW_ATTR_BC_STATUS
,
1230 .get
= rt305x_esw_get_bc_status
,
1231 .set
= rt305x_esw_set_bc_status
,
1234 .type
= SWITCH_TYPE_INT
,
1235 .name
= "led_frequency",
1236 .description
= "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1238 .id
= RT305X_ESW_ATTR_LED_FREQ
,
1239 .get
= rt305x_esw_get_led_freq
,
1240 .set
= rt305x_esw_set_led_freq
,
1244 static const struct switch_attr esw_port
[] = {
1246 .type
= SWITCH_TYPE_INT
,
1248 .description
= "Port state (1:disabled)",
1250 .id
= RT305X_ESW_ATTR_PORT_DISABLE
,
1251 .get
= esw_get_port_bool
,
1252 .set
= esw_set_port_bool
,
1255 .type
= SWITCH_TYPE_INT
,
1256 .name
= "doubletag",
1257 .description
= "Double tagging for incoming vlan packets "
1260 .id
= RT305X_ESW_ATTR_PORT_DOUBLETAG
,
1261 .get
= esw_get_port_bool
,
1262 .set
= esw_set_port_bool
,
1265 .type
= SWITCH_TYPE_INT
,
1267 .description
= "Untag (1:strip outgoing vlan tag)",
1269 .id
= RT305X_ESW_ATTR_PORT_UNTAG
,
1270 .get
= esw_get_port_bool
,
1271 .set
= esw_set_port_bool
,
1274 .type
= SWITCH_TYPE_INT
,
1276 .description
= "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1277 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1278 " 8:100mact, 10:blink, 11:off, 12:on)",
1280 .id
= RT305X_ESW_ATTR_PORT_LED
,
1281 .get
= esw_get_port_led
,
1282 .set
= esw_set_port_led
,
1285 .type
= SWITCH_TYPE_INT
,
1287 .description
= "HW port group (0:wan, 1:lan)",
1289 .id
= RT305X_ESW_ATTR_PORT_LAN
,
1290 .get
= esw_get_port_bool
,
1293 .type
= SWITCH_TYPE_INT
,
1295 .description
= "Receive bad packet counter",
1296 .id
= RT305X_ESW_ATTR_PORT_RECV_BAD
,
1297 .get
= esw_get_port_recv_badgood
,
1300 .type
= SWITCH_TYPE_INT
,
1301 .name
= "recv_good",
1302 .description
= "Receive good packet counter",
1303 .id
= RT305X_ESW_ATTR_PORT_RECV_GOOD
,
1304 .get
= esw_get_port_recv_badgood
,
1307 .type
= SWITCH_TYPE_INT
,
1310 .description
= "Transmit bad packet counter. rt5350 only",
1311 .id
= RT5350_ESW_ATTR_PORT_TR_BAD
,
1312 .get
= esw_get_port_tr_badgood
,
1315 .type
= SWITCH_TYPE_INT
,
1318 .description
= "Transmit good packet counter. rt5350 only",
1319 .id
= RT5350_ESW_ATTR_PORT_TR_GOOD
,
1320 .get
= esw_get_port_tr_badgood
,
1324 static const struct switch_attr esw_vlan
[] = {
1327 static const struct switch_dev_ops esw_ops
= {
1330 .n_attr
= ARRAY_SIZE(esw_global
),
1334 .n_attr
= ARRAY_SIZE(esw_port
),
1338 .n_attr
= ARRAY_SIZE(esw_vlan
),
1340 .get_vlan_ports
= esw_get_vlan_ports
,
1341 .set_vlan_ports
= esw_set_vlan_ports
,
1342 .get_port_pvid
= esw_get_port_pvid
,
1343 .set_port_pvid
= esw_set_port_pvid
,
1344 .get_port_link
= esw_get_port_link
,
1345 .apply_config
= esw_apply_config
,
1346 .reset_switch
= esw_reset_switch
,
1349 static int esw_probe(struct platform_device
*pdev
)
1351 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1352 struct device_node
*np
= pdev
->dev
.of_node
;
1353 const __be32
*port_map
, *port_disable
, *reg_init
;
1354 struct switch_dev
*swdev
;
1355 struct rt305x_esw
*esw
;
1358 esw
= devm_kzalloc(&pdev
->dev
, sizeof(*esw
), GFP_KERNEL
);
1362 esw
->dev
= &pdev
->dev
;
1363 esw
->irq
= irq_of_parse_and_map(np
, 0);
1364 esw
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1365 if (IS_ERR(esw
->base
))
1366 return PTR_ERR(esw
->base
);
1368 port_map
= of_get_property(np
, "mediatek,portmap", NULL
);
1370 esw
->port_map
= be32_to_cpu(*port_map
);
1372 port_disable
= of_get_property(np
, "mediatek,portdisable", NULL
);
1374 esw
->port_disable
= be32_to_cpu(*port_disable
);
1376 reg_init
= of_get_property(np
, "ralink,fct2", NULL
);
1378 esw
->reg_initval_fct2
= be32_to_cpu(*reg_init
);
1380 reg_init
= of_get_property(np
, "ralink,fpa2", NULL
);
1382 esw
->reg_initval_fpa2
= be32_to_cpu(*reg_init
);
1384 reg_init
= of_get_property(np
, "mediatek,led_polarity", NULL
);
1386 esw
->reg_led_polarity
= be32_to_cpu(*reg_init
);
1388 swdev
= &esw
->swdev
;
1389 swdev
->of_node
= pdev
->dev
.of_node
;
1390 swdev
->name
= "rt305x-esw";
1391 swdev
->alias
= "rt305x";
1392 swdev
->cpu_port
= RT305X_ESW_PORT6
;
1393 swdev
->ports
= RT305X_ESW_NUM_PORTS
;
1394 swdev
->vlans
= RT305X_ESW_NUM_VIDS
;
1395 swdev
->ops
= &esw_ops
;
1397 ret
= register_switch(swdev
, NULL
);
1399 dev_err(&pdev
->dev
, "register_switch failed\n");
1403 platform_set_drvdata(pdev
, esw
);
1405 spin_lock_init(&esw
->reg_rw_lock
);
1409 reg_init
= of_get_property(np
, "ralink,rgmii", NULL
);
1410 if (reg_init
&& be32_to_cpu(*reg_init
) == 1) {
1412 * External switch connected to RGMII interface.
1413 * Unregister the switch device after initialization.
1415 dev_err(&pdev
->dev
, "RGMII mode, not exporting switch device.\n");
1416 unregister_switch(&esw
->swdev
);
1417 platform_set_drvdata(pdev
, NULL
);
1421 ret
= devm_request_irq(&pdev
->dev
, esw
->irq
, esw_interrupt
, 0, "esw",
1425 esw_w32(esw
, RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_ISR
);
1426 esw_w32(esw
, ~RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_IMR
);
1432 static int esw_remove(struct platform_device
*pdev
)
1434 struct rt305x_esw
*esw
= platform_get_drvdata(pdev
);
1437 esw_w32(esw
, ~0, RT305X_ESW_REG_IMR
);
1438 platform_set_drvdata(pdev
, NULL
);
1444 static const struct of_device_id ralink_esw_match
[] = {
1445 { .compatible
= "ralink,rt3050-esw" },
1448 MODULE_DEVICE_TABLE(of
, ralink_esw_match
);
1450 static struct platform_driver esw_driver
= {
1452 .remove
= esw_remove
,
1454 .name
= "rt3050-esw",
1455 .owner
= THIS_MODULE
,
1456 .of_match_table
= ralink_esw_match
,
1460 module_platform_driver(esw_driver
);
1462 MODULE_LICENSE("GPL");
1463 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1464 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1465 MODULE_VERSION(MTK_FE_DRV_VERSION
);