target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_irq.h>
  21
  22 #include <ralink_regs.h>
  23
  24 #include "mtk_eth_soc.h"
  25 #include "gsw_mt7620.h"
  26
  27 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  28 {
  29         iowrite32(val, gsw->base + reg);
  30 }
  31
  32 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  33 {
  34         return ioread32(gsw->base + reg);
  35 }
  36
  37 static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
  38 {
  39         struct fe_priv *priv = (struct fe_priv *)_priv;
  40         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  41         u32 reg, i;
  42
  43         reg = mt7530_mdio_r32(gsw, 0x700c);
  44         mt7530_mdio_w32(gsw, 0x700c, reg);
  45
  46         for (i = 0; i < 5; i++)
  47                 if (reg & BIT(i)) {
  48                         unsigned int link;
  49
  50                         link = mt7530_mdio_r32(gsw,
  51                                                0x3008 + (i * 0x100)) & 0x1;
  52
  53                         if (link != priv->link[i]) {
  54                                 priv->link[i] = link;
  55                                 if (link)
  56                                         netdev_info(priv->netdev,
  57                                                     "port %d link up\n", i);
  58                                 else
  59                                         netdev_info(priv->netdev,
  60                                                     "port %d link down\n", i);
  61                         }
  62                 }
  63
  64         mt7620_handle_carrier(priv);
  65
  66         return IRQ_HANDLED;
  67 }
  68
  69 static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
  70 {
  71         u32 i;
  72         u32 val;
  73
  74         /* wardware reset the switch */
  75         fe_reset(RST_CTRL_MCM);
  76         mdelay(10);
  77
  78         /* reduce RGMII2 PAD driving strength */
  79         rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
  80
  81         /* gpio mux - RGMII1=Normal mode */
  82         rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
  83
  84         /* set GMAC1 RGMII mode */
  85         rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
  86
  87         /* enable MDIO to control MT7530 */
  88         rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
  89
  90         /* turn off all PHYs */
  91         for (i = 0; i <= 4; i++) {
  92                 val = _mt7620_mii_read(gsw, i, 0x0);
  93                 val |= BIT(11);
  94                 _mt7620_mii_write(gsw, i, 0x0, val);
  95         }
  96
  97         /* reset the switch */
  98         mt7530_mdio_w32(gsw, 0x7000, 0x3);
  99         usleep_range(10, 20);
 100
 101         /* (GE1, Force 1000M/FD, FC OFF, MAX_RX_LENGTH 1536) */
 102         mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
 103         mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
 104
 105         /* (GE2, Link down) */
 106         mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
 107
 108         /* Set switch max RX frame length to 2k */
 109         mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
 110
 111         /* Enable Port 6, P5 as GMAC5, P5 disable */
 112         val = mt7530_mdio_r32(gsw, 0x7804);
 113         val &= ~BIT(8);
 114         val |= BIT(6) | BIT(13) | BIT(16);
 115         mt7530_mdio_w32(gsw, 0x7804, val);
 116
 117         val = rt_sysc_r32(0x10);
 118         val = (val >> 6) & 0x7;
 119         if (val >= 6) {
 120                 /* 25Mhz Xtal - do nothing */
 121         } else if (val >= 3) {
 122                 /* 40Mhz */
 123
 124                 /* disable MT7530 core clock */
 125                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 126                 _mt7620_mii_write(gsw, 0, 14, 0x410);
 127                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 128                 _mt7620_mii_write(gsw, 0, 14, 0x0);
 129
 130                 /* disable MT7530 PLL */
 131                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 132                 _mt7620_mii_write(gsw, 0, 14, 0x40d);
 133                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 134                 _mt7620_mii_write(gsw, 0, 14, 0x2020);
 135
 136                 /* for MT7530 core clock = 500Mhz */
 137                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 138                 _mt7620_mii_write(gsw, 0, 14, 0x40e);
 139                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 140                 _mt7620_mii_write(gsw, 0, 14, 0x119);
 141
 142                 /* enable MT7530 PLL */
 143                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 144                 _mt7620_mii_write(gsw, 0, 14, 0x40d);
 145                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 146                 _mt7620_mii_write(gsw, 0, 14, 0x2820);
 147
 148                 usleep_range(20, 40);
 149
 150                 /* enable MT7530 core clock */
 151                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 152                 _mt7620_mii_write(gsw, 0, 14, 0x410);
 153                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 154         } else {
 155                 /* 20Mhz Xtal - TODO */
 156         }
 157
 158         /* RGMII */
 159         _mt7620_mii_write(gsw, 0, 14, 0x1);
 160
 161         /* set MT7530 central align */
 162         val = mt7530_mdio_r32(gsw, 0x7830);
 163         val &= ~BIT(0);
 164         val |= BIT(1);
 165         mt7530_mdio_w32(gsw, 0x7830, val);
 166         val = mt7530_mdio_r32(gsw, 0x7a40);
 167         val &= ~BIT(30);
 168         mt7530_mdio_w32(gsw, 0x7a40, val);
 169         mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 170
 171         /* delay setting for 10/1000M */
 172         mt7530_mdio_w32(gsw, 0x7b00, 0x102);
 173         mt7530_mdio_w32(gsw, 0x7b04, 0x14);
 174
 175         /* lower Tx Driving*/
 176         mt7530_mdio_w32(gsw, 0x7a54, 0x44);
 177         mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
 178         mt7530_mdio_w32(gsw, 0x7a64, 0x44);
 179         mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
 180         mt7530_mdio_w32(gsw, 0x7a74, 0x44);
 181         mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
 182
 183         /* turn on all PHYs */
 184         for (i = 0; i <= 4; i++) {
 185                 val = _mt7620_mii_read(gsw, i, 0);
 186                 val &= ~BIT(11);
 187                 _mt7620_mii_write(gsw, i, 0, val);
 188         }
 189
 190         /* enable irq */
 191         mt7530_mdio_w32(gsw, 0x7008, 0x1f);
 192         val = mt7530_mdio_r32(gsw, 0x7808);
 193         val |= 3 << 16;
 194         mt7530_mdio_w32(gsw, 0x7808, val);
 195 }
 196
 197 static const struct of_device_id mediatek_gsw_match[] = {
 198         { .compatible = "mediatek,mt7621-gsw" },
 199         {},
 200 };
 201 MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
 202
 203 int mtk_gsw_init(struct fe_priv *priv)
 204 {
 205         struct device_node *np = priv->switch_np;
 206         struct platform_device *pdev = of_find_device_by_node(np);
 207         struct mt7620_gsw *gsw;
 208
 209         if (!pdev)
 210                 return -ENODEV;
 211
 212         if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
 213                 return -EINVAL;
 214
 215         gsw = platform_get_drvdata(pdev);
 216         priv->soc->swpriv = gsw;
 217
 218         if (gsw->irq) {
 219                 request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
 220                             "gsw", priv);
 221                 disable_irq(gsw->irq);
 222         }
 223
 224         mt7621_hw_init(gsw, np);
 225
 226         if (gsw->irq)
 227                 enable_irq(gsw->irq);
 228
 229         return 0;
 230 }
 231
 232 static int mt7621_gsw_probe(struct platform_device *pdev)
 233 {
 234         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 235         struct mt7620_gsw *gsw;
 236
 237         gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
 238         if (!gsw)
 239                 return -ENOMEM;
 240
 241         gsw->base = devm_ioremap_resource(&pdev->dev, res);
 242         if (IS_ERR(gsw->base))
 243                 return PTR_ERR(gsw->base);
 244
 245         gsw->dev = &pdev->dev;
 246         gsw->irq = platform_get_irq(pdev, 0);
 247
 248         platform_set_drvdata(pdev, gsw);
 249
 250         return 0;
 251 }
 252
 253 static int mt7621_gsw_remove(struct platform_device *pdev)
 254 {
 255         platform_set_drvdata(pdev, NULL);
 256
 257         return 0;
 258 }
 259
 260 static struct platform_driver gsw_driver = {
 261         .probe = mt7621_gsw_probe,
 262         .remove = mt7621_gsw_remove,
 263         .driver = {
 264                 .name = "mt7621-gsw",
 265                 .owner = THIS_MODULE,
 266                 .of_match_table = mediatek_gsw_match,
 267         },
 268 };
 269
 270 module_platform_driver(gsw_driver);
 271
 272 MODULE_LICENSE("GPL");
 273 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 274 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
 275 MODULE_VERSION(MTK_FE_DRV_VERSION);