target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h

   1 /*
   2  *  Ralink RT3662/RT3883 SoC register definitions
   3  *
   4  *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #ifndef _RT3883_REGS_H_
  12 #define _RT3883_REGS_H_
  13
  14 #include <linux/bitops.h>
  15
  16 #define RT3883_SDRAM_BASE       0x00000000
  17 #define RT3883_SYSC_BASE        0x10000000
  18 #define RT3883_TIMER_BASE       0x10000100
  19 #define RT3883_INTC_BASE        0x10000200
  20 #define RT3883_MEMC_BASE        0x10000300
  21 #define RT3883_UART0_BASE       0x10000500
  22 #define RT3883_PIO_BASE         0x10000600
  23 #define RT3883_FSCC_BASE        0x10000700
  24 #define RT3883_NANDC_BASE       0x10000810
  25 #define RT3883_I2C_BASE         0x10000900
  26 #define RT3883_I2S_BASE         0x10000a00
  27 #define RT3883_SPI_BASE         0x10000b00
  28 #define RT3883_UART1_BASE       0x10000c00
  29 #define RT3883_PCM_BASE         0x10002000
  30 #define RT3883_GDMA_BASE        0x10002800
  31 #define RT3883_CODEC1_BASE      0x10003000
  32 #define RT3883_CODEC2_BASE      0x10003800
  33 #define RT3883_FE_BASE          0x10100000
  34 #define RT3883_ROM_BASE         0x10118000
  35 #define RT3883_USBDEV_BASE      0x10112000
  36 #define RT3883_PCI_BASE         0x10140000
  37 #define RT3883_WLAN_BASE        0x10180000
  38 #define RT3883_USBHOST_BASE     0x101c0000
  39 #define RT3883_BOOT_BASE        0x1c000000
  40 #define RT3883_SRAM_BASE        0x1e000000
  41 #define RT3883_PCIMEM_BASE      0x20000000
  42
  43 #define RT3883_EHCI_BASE        (RT3883_USBHOST_BASE)
  44 #define RT3883_OHCI_BASE        (RT3883_USBHOST_BASE + 0x1000)
  45
  46 #define RT3883_SYSC_SIZE        0x100
  47 #define RT3883_TIMER_SIZE       0x100
  48 #define RT3883_INTC_SIZE        0x100
  49 #define RT3883_MEMC_SIZE        0x100
  50 #define RT3883_UART0_SIZE       0x100
  51 #define RT3883_UART1_SIZE       0x100
  52 #define RT3883_PIO_SIZE         0x100
  53 #define RT3883_FSCC_SIZE        0x100
  54 #define RT3883_NANDC_SIZE       0x0f0
  55 #define RT3883_I2C_SIZE         0x100
  56 #define RT3883_I2S_SIZE         0x100
  57 #define RT3883_SPI_SIZE         0x100
  58 #define RT3883_PCM_SIZE         0x800
  59 #define RT3883_GDMA_SIZE        0x800
  60 #define RT3883_CODEC1_SIZE      0x800
  61 #define RT3883_CODEC2_SIZE      0x800
  62 #define RT3883_FE_SIZE          0x10000
  63 #define RT3883_ROM_SIZE         0x4000
  64 #define RT3883_USBDEV_SIZE      0x4000
  65 #define RT3883_PCI_SIZE         0x40000
  66 #define RT3883_WLAN_SIZE        0x40000
  67 #define RT3883_USBHOST_SIZE     0x40000
  68 #define RT3883_BOOT_SIZE        (32 * 1024 * 1024)
  69 #define RT3883_SRAM_SIZE        (32 * 1024 * 1024)
  70
  71 /* SYSC registers */
  72 #define RT3883_SYSC_REG_CHIPID0_3       0x00    /* Chip ID 0 */
  73 #define RT3883_SYSC_REG_CHIPID4_7       0x04    /* Chip ID 1 */
  74 #define RT3883_SYSC_REG_REVID           0x0c    /* Chip Revision Identification */
  75 #define RT3883_SYSC_REG_SYSCFG0         0x10    /* System Configuration 0 */
  76 #define RT3883_SYSC_REG_SYSCFG1         0x14    /* System Configuration 1 */
  77 #define RT3883_SYSC_REG_CLKCFG0         0x2c    /* Clock Configuration 0 */
  78 #define RT3883_SYSC_REG_CLKCFG1         0x30    /* Clock Configuration 1 */
  79 #define RT3883_SYSC_REG_RSTCTRL         0x34    /* Reset Control*/
  80 #define RT3883_SYSC_REG_RSTSTAT         0x38    /* Reset Status*/
  81 #define RT3883_SYSC_REG_USB_PS          0x5c    /* USB Power saving control */
  82 #define RT3883_SYSC_REG_GPIO_MODE       0x60    /* GPIO Purpose Select */
  83 #define RT3883_SYSC_REG_PMU             0x88
  84 #define RT3883_SYSC_REG_PMU1            0x8c
  85
  86 #define RT3883_REVID_VER_ID_MASK        0x0f
  87 #define RT3883_REVID_VER_ID_SHIFT       8
  88 #define RT3883_REVID_ECO_ID_MASK        0x0f
  89
  90 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2   BIT(17)
  91 #define RT3883_SYSCFG0_CPUCLK_SHIFT     8
  92 #define RT3883_SYSCFG0_CPUCLK_MASK      0x3
  93 #define RT3883_SYSCFG0_CPUCLK_250       0x0
  94 #define RT3883_SYSCFG0_CPUCLK_384       0x1
  95 #define RT3883_SYSCFG0_CPUCLK_480       0x2
  96 #define RT3883_SYSCFG0_CPUCLK_500       0x3
  97
  98 #define RT3883_SYSCFG1_USB0_HOST_MODE   BIT(10)
  99 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
 100
 101 #define RT3883_CLKCFG1_UPHY1_CLK_EN     BIT(20)
 102 #define RT3883_CLKCFG1_UPHY0_CLK_EN     BIT(18)
 103
 104 #define RT3883_GPIO_MODE_I2C            BIT(0)
 105 #define RT3883_GPIO_MODE_SPI            BIT(1)
 106 #define RT3883_GPIO_MODE_UART0_SHIFT    2
 107 #define RT3883_GPIO_MODE_UART0_MASK     0x7
 108 #define RT3883_GPIO_MODE_UART0(x)       ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
 109 #define RT3883_GPIO_MODE_UARTF          0x0
 110 #define RT3883_GPIO_MODE_PCM_UARTF      0x1
 111 #define RT3883_GPIO_MODE_PCM_I2S        0x2
 112 #define RT3883_GPIO_MODE_I2S_UARTF      0x3
 113 #define RT3883_GPIO_MODE_PCM_GPIO       0x4
 114 #define RT3883_GPIO_MODE_GPIO_UARTF     0x5
 115 #define RT3883_GPIO_MODE_GPIO_I2S       0x6
 116 #define RT3883_GPIO_MODE_GPIO           0x7
 117 #define RT3883_GPIO_MODE_UART1          BIT(5)
 118 #define RT3883_GPIO_MODE_JTAG           BIT(6)
 119 #define RT3883_GPIO_MODE_MDIO           BIT(7)
 120 #define RT3883_GPIO_MODE_GE1            BIT(9)
 121 #define RT3883_GPIO_MODE_GE2            BIT(10)
 122 #define RT3883_GPIO_MODE_PCI_SHIFT      11
 123 #define RT3883_GPIO_MODE_PCI_MASK       0x7
 124 #define RT3883_GPIO_MODE_PCI(_x)        ((_x) << RT3883_GPIO_MODE_PCI_SHIFT)
 125 #define RT3883_GPIO_MODE_PCI_DEV        0
 126 #define RT3883_GPIO_MODE_PCI_HOST2      1
 127 #define RT3883_GPIO_MODE_PCI_HOST1      2
 128 #define RT3883_GPIO_MODE_PCI_FNC        3
 129 #define RT3883_GPIO_MODE_PCI_GPIO       7
 130 #define RT3883_GPIO_MODE_LNA_A_SHIFT    16
 131 #define RT3883_GPIO_MODE_LNA_A_MASK     0x3
 132 #define RT3883_GPIO_MODE_LNA_A(_x)      ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
 133 #define RT3883_GPIO_MODE_LNA_A_GPIO     0x3
 134 #define RT3883_GPIO_MODE_LNA_G_SHIFT    18
 135 #define RT3883_GPIO_MODE_LNA_G_MASK     0x3
 136 #define RT3883_GPIO_MODE_LNA_G(_x)      ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
 137 #define RT3883_GPIO_MODE_LNA_G_GPIO     0x3
 138
 139 #define RT3883_RSTCTRL_PCIE_PCI_PDM     BIT(27)
 140 #define RT3883_RSTCTRL_FLASH            BIT(26)
 141 #define RT3883_RSTCTRL_UDEV             BIT(25)
 142 #define RT3883_RSTCTRL_PCI              BIT(24)
 143 #define RT3883_RSTCTRL_PCIE             BIT(23)
 144 #define RT3883_RSTCTRL_UHST             BIT(22)
 145 #define RT3883_RSTCTRL_FE               BIT(21)
 146 #define RT3883_RSTCTRL_WLAN             BIT(20)
 147 #define RT3883_RSTCTRL_UART1            BIT(29)
 148 #define RT3883_RSTCTRL_SPI              BIT(18)
 149 #define RT3883_RSTCTRL_I2S              BIT(17)
 150 #define RT3883_RSTCTRL_I2C              BIT(16)
 151 #define RT3883_RSTCTRL_NAND             BIT(15)
 152 #define RT3883_RSTCTRL_DMA              BIT(14)
 153 #define RT3883_RSTCTRL_PIO              BIT(13)
 154 #define RT3883_RSTCTRL_UART             BIT(12)
 155 #define RT3883_RSTCTRL_PCM              BIT(11)
 156 #define RT3883_RSTCTRL_MC               BIT(10)
 157 #define RT3883_RSTCTRL_INTC             BIT(9)
 158 #define RT3883_RSTCTRL_TIMER            BIT(8)
 159 #define RT3883_RSTCTRL_SYS              BIT(0)
 160
 161 #define RT3883_INTC_INT_SYSCTL  BIT(0)
 162 #define RT3883_INTC_INT_TIMER0  BIT(1)
 163 #define RT3883_INTC_INT_TIMER1  BIT(2)
 164 #define RT3883_INTC_INT_IA      BIT(3)
 165 #define RT3883_INTC_INT_PCM     BIT(4)
 166 #define RT3883_INTC_INT_UART0   BIT(5)
 167 #define RT3883_INTC_INT_PIO     BIT(6)
 168 #define RT3883_INTC_INT_DMA     BIT(7)
 169 #define RT3883_INTC_INT_NAND    BIT(8)
 170 #define RT3883_INTC_INT_PERFC   BIT(9)
 171 #define RT3883_INTC_INT_I2S     BIT(10)
 172 #define RT3883_INTC_INT_UART1   BIT(12)
 173 #define RT3883_INTC_INT_UHST    BIT(18)
 174 #define RT3883_INTC_INT_UDEV    BIT(19)
 175
 176 /* FLASH/SRAM/Codec Controller registers */
 177 #define RT3883_FSCC_REG_FLASH_CFG0      0x00
 178 #define RT3883_FSCC_REG_FLASH_CFG1      0x04
 179 #define RT3883_FSCC_REG_CODEC_CFG0      0x40
 180 #define RT3883_FSCC_REG_CODEC_CFG1      0x44
 181
 182 #define RT3883_FLASH_CFG_WIDTH_SHIFT    26
 183 #define RT3883_FLASH_CFG_WIDTH_MASK     0x3
 184 #define RT3883_FLASH_CFG_WIDTH_8BIT     0x0
 185 #define RT3883_FLASH_CFG_WIDTH_16BIT    0x1
 186 #define RT3883_FLASH_CFG_WIDTH_32BIT    0x2
 187
 188
 189 /* UART registers */
 190 #define RT3883_UART_REG_RX      0
 191 #define RT3883_UART_REG_TX      1
 192 #define RT3883_UART_REG_IER     2
 193 #define RT3883_UART_REG_IIR     3
 194 #define RT3883_UART_REG_FCR     4
 195 #define RT3883_UART_REG_LCR     5
 196 #define RT3883_UART_REG_MCR     6
 197 #define RT3883_UART_REG_LSR     7
 198
 199 #endif /* _RT3883_REGS_H_ */