target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 /*
   2  *  Ralink RT288x SoC PCI register definitions
   3  *
   4  *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
   5  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/io.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/mach-ralink/rt288x.h>
  20 #include <asm/mach-ralink/rt288x_regs.h>
  21
  22 #define RT2880_PCI_SLOT1_BASE           0x20000000
  23
  24 #define RT2880_PCI_REG_PCICFG_ADDR      0x00
  25 #define RT2880_PCI_REG_PCIMSK_ADDR      0x0c
  26 #define RT2880_PCI_REG_BAR0SETUP_ADDR   0x10
  27 #define RT2880_PCI_REG_IMBASEBAR0_ADDR  0x18
  28 #define RT2880_PCI_REG_CONFIG_ADDR      0x20
  29 #define RT2880_PCI_REG_CONFIG_DATA      0x24
  30 #define RT2880_PCI_REG_MEMBASE          0x28
  31 #define RT2880_PCI_REG_IOBASE           0x2c
  32 #define RT2880_PCI_REG_ID               0x30
  33 #define RT2880_PCI_REG_CLASS            0x34
  34 #define RT2880_PCI_REG_SUBID            0x38
  35 #define RT2880_PCI_REG_ARBCTL           0x80
  36
  37 #define PCI_ACCESS_READ  0
  38 #define PCI_ACCESS_WRITE 1
  39
  40 void __iomem *rt2880_pci_base;
  41
  42 static u32 rt2880_pci_reg_read(u32 reg)
  43 {
  44         return readl(rt2880_pci_base + reg);
  45 }
  46
  47 static void rt2880_pci_reg_write(u32 val, u32 reg)
  48 {
  49         writel(val, rt2880_pci_base + reg);
  50 }
  51
  52 static void config_access(unsigned char access_type, struct pci_bus *bus,
  53                           unsigned int devfn, unsigned char where, u32 *data)
  54 {
  55         unsigned int slot = PCI_SLOT(devfn);
  56         unsigned int address;
  57         u8 func = PCI_FUNC(devfn);
  58
  59         address = (bus->number << 16) | (slot << 11) | (func << 8) |
  60                   (where & 0xfc) | 0x80000000;
  61
  62         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  63         if (access_type == PCI_ACCESS_WRITE)
  64                 rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
  65         else
  66                 *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  67 }
  68
  69 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  70                                   int where, int size, u32 *val)
  71 {
  72         u32 data = 0;
  73
  74         config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  75
  76         if (size == 1)
  77                 *val = (data >> ((where & 3) << 3)) & 0xff;
  78         else if (size == 2)
  79                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  80         else
  81                 *val = data;
  82
  83         return PCIBIOS_SUCCESSFUL;
  84 }
  85
  86 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  87                                    int where, int size, u32 val)
  88 {
  89         u32 data = 0;
  90
  91         if (size == 4) {
  92                 data = val;
  93         } else {
  94                 config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  95                 if (size == 1)
  96                         data = (data & ~(0xff << ((where & 3) << 3))) |
  97                                (val << ((where & 3) << 3));
  98                 else if (size == 2)
  99                         data = (data & ~(0xffff << ((where & 3) << 3))) |
 100                                (val << ((where & 3) << 3));
 101         }
 102
 103         config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
 104
 105         return PCIBIOS_SUCCESSFUL;
 106 }
 107
 108 static struct pci_ops rt2880_pci_ops = {
 109         .read   = rt2880_pci_config_read,
 110         .write  = rt2880_pci_config_write,
 111 };
 112
 113 static struct resource rt2880_pci_io_resource = {
 114         .name   = "PCI MEM space",
 115         .start  = 0x20000000,
 116         .end    = 0x2FFFFFFF,
 117         .flags  = IORESOURCE_MEM,
 118 };
 119
 120 static struct resource rt2880_pci_mem_resource = {
 121         .name   = "PCI IO space",
 122         .start  = 0x00460000,
 123         .end    = 0x0046FFFF,
 124         .flags  = IORESOURCE_IO,
 125 };
 126
 127 static struct pci_controller rt2880_pci_controller = {
 128         .pci_ops        = &rt2880_pci_ops,
 129         .mem_resource   = &rt2880_pci_io_resource,
 130         .io_resource    = &rt2880_pci_mem_resource,
 131 };
 132
 133 static inline void read_config(unsigned long bus, unsigned long dev,
 134                                unsigned long func, unsigned long reg,
 135                                unsigned long *val)
 136 {
 137         unsigned long address;
 138
 139         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 140                   0x80000000;
 141         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 142         *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 143 }
 144
 145 static inline void write_config(unsigned long bus, unsigned long dev,
 146                                 unsigned long func, unsigned long reg,
 147                                 unsigned long val)
 148 {
 149         unsigned long address;
 150
 151         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 152                   0x80000000;
 153         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 154         rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
 155 }
 156
 157 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 158 {
 159         u16 cmd;
 160         unsigned long val;
 161         int irq = -1;
 162
 163         if (dev->bus->number != 0)
 164                 return 0;
 165
 166         switch (PCI_SLOT(dev->devfn)) {
 167         case 0x00:
 168                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 169                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 170                 break;
 171         case 0x11:
 172                 irq = RT288X_CPU_IRQ_PCI;
 173                 break;
 174         default:
 175                 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 176                        __FILE__, __func__, __LINE__);
 177                 BUG();
 178                 break;
 179         }
 180
 181         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 182         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 183         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 184         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 185                PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 186                PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 187         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 188         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 189                               dev->irq);
 190         return irq;
 191 }
 192
 193 static int __init rt2880_pci_init(void)
 194 {
 195         unsigned long val = 0;
 196         int i;
 197
 198         rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
 199
 200         rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
 201         for(i = 0; i < 0xfffff; i++) {}
 202
 203         rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
 204         rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 205         rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE);
 206         rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE);
 207         rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
 208         rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
 209         rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 210         rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 211         rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
 212         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 213         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 214
 215         register_pci_controller(&rt2880_pci_controller);
 216         return 0;
 217 }
 218
 219 int pcibios_plat_dev_init(struct pci_dev *dev)
 220 {
 221         return 0;
 222 }
 223
 224 struct pci_fixup pcibios_fixups[] = {
 225         {0}
 226 };
 227
 228 arch_initcall(rt2880_pci_init);