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ralink: move ethernet driver to files/
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3052.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31
32 #include <asm/mach-ralink/ralink_regs.h>
33
34 #include "ralink_soc_eth.h"
35
36 #include <linux/ioport.h>
37 #include <linux/switch.h>
38 #include <linux/mii.h>
39
40 #include <ralink_regs.h>
41 #include <asm/mach-ralink/rt305x.h>
42 #include <asm/mach-ralink/rt305x_esw_platform.h>
43
44 /*
45 * HW limitations for this switch:
46 * - No large frame support (PKT_MAX_LEN at most 1536)
47 * - Can't have untagged vlan and tagged vlan on one port at the same time,
48 * though this might be possible using the undocumented PPE.
49 */
50
51 #define RT305X_ESW_REG_ISR 0x00
52 #define RT305X_ESW_REG_IMR 0x04
53 #define RT305X_ESW_REG_FCT0 0x08
54 #define RT305X_ESW_REG_PFC1 0x14
55 #define RT305X_ESW_REG_ATS 0x24
56 #define RT305X_ESW_REG_ATS0 0x28
57 #define RT305X_ESW_REG_ATS1 0x2c
58 #define RT305X_ESW_REG_ATS2 0x30
59 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
60 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
61 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
62 #define RT305X_ESW_REG_POA 0x80
63 #define RT305X_ESW_REG_FPA 0x84
64 #define RT305X_ESW_REG_SOCPC 0x8c
65 #define RT305X_ESW_REG_POC0 0x90
66 #define RT305X_ESW_REG_POC1 0x94
67 #define RT305X_ESW_REG_POC2 0x98
68 #define RT305X_ESW_REG_SGC 0x9c
69 #define RT305X_ESW_REG_STRT 0xa0
70 #define RT305X_ESW_REG_PCR0 0xc0
71 #define RT305X_ESW_REG_PCR1 0xc4
72 #define RT305X_ESW_REG_FPA2 0xc8
73 #define RT305X_ESW_REG_FCT2 0xcc
74 #define RT305X_ESW_REG_SGC2 0xe4
75 #define RT305X_ESW_REG_P0LED 0xa4
76 #define RT305X_ESW_REG_P1LED 0xa8
77 #define RT305X_ESW_REG_P2LED 0xac
78 #define RT305X_ESW_REG_P3LED 0xb0
79 #define RT305X_ESW_REG_P4LED 0xb4
80 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
81 #define RT305X_ESW_REG_P1PC 0xec
82 #define RT305X_ESW_REG_P2PC 0xf0
83 #define RT305X_ESW_REG_P3PC 0xf4
84 #define RT305X_ESW_REG_P4PC 0xf8
85 #define RT305X_ESW_REG_P5PC 0xfc
86
87 #define RT305X_ESW_LED_LINK 0
88 #define RT305X_ESW_LED_100M 1
89 #define RT305X_ESW_LED_DUPLEX 2
90 #define RT305X_ESW_LED_ACTIVITY 3
91 #define RT305X_ESW_LED_COLLISION 4
92 #define RT305X_ESW_LED_LINKACT 5
93 #define RT305X_ESW_LED_DUPLCOLL 6
94 #define RT305X_ESW_LED_10MACT 7
95 #define RT305X_ESW_LED_100MACT 8
96 /* Additional led states not in datasheet: */
97 #define RT305X_ESW_LED_BLINK 10
98 #define RT305X_ESW_LED_ON 12
99
100 #define RT305X_ESW_LINK_S 25
101 #define RT305X_ESW_DUPLEX_S 9
102 #define RT305X_ESW_SPD_S 0
103
104 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
105 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
106 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
107
108 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
109
110 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
111 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
112
113 #define RT305X_ESW_PVIDC_PVID_M 0xfff
114 #define RT305X_ESW_PVIDC_PVID_S 12
115
116 #define RT305X_ESW_VLANI_VID_M 0xfff
117 #define RT305X_ESW_VLANI_VID_S 12
118
119 #define RT305X_ESW_VMSC_MSC_M 0xff
120 #define RT305X_ESW_VMSC_MSC_S 8
121
122 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
123 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
124 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
125 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
126
127 #define RT305X_ESW_POC0_EN_BP_S 0
128 #define RT305X_ESW_POC0_EN_FC_S 8
129 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
130 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
131 #define RT305X_ESW_POC0_DIS_PORT_S 23
132
133 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
134 #define RT305X_ESW_POC2_UNTAG_EN_S 0
135 #define RT305X_ESW_POC2_ENAGING_S 8
136 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
137
138 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
139 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
140 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
141 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
142
143 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
144 #define RT305X_ESW_PFC1_EN_VLAN_S 16
145 #define RT305X_ESW_PFC1_EN_TOS_S 24
146
147 #define RT305X_ESW_VLAN_NONE 0xfff
148
149 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
150 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
151
152 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
153 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
154
155 #define RT305X_ESW_POA_LINK_MASK 0x1f
156 #define RT305X_ESW_POA_LINK_SHIFT 25
157
158 #define RT305X_ESW_PORT_ST_CHG BIT(26)
159 #define RT305X_ESW_PORT0 0
160 #define RT305X_ESW_PORT1 1
161 #define RT305X_ESW_PORT2 2
162 #define RT305X_ESW_PORT3 3
163 #define RT305X_ESW_PORT4 4
164 #define RT305X_ESW_PORT5 5
165 #define RT305X_ESW_PORT6 6
166
167 #define RT305X_ESW_PORTS_NONE 0
168
169 #define RT305X_ESW_PMAP_LLLLLL 0x3f
170 #define RT305X_ESW_PMAP_LLLLWL 0x2f
171 #define RT305X_ESW_PMAP_WLLLLL 0x3e
172
173 #define RT305X_ESW_PORTS_INTERNAL \
174 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
175 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
176 BIT(RT305X_ESW_PORT4))
177
178 #define RT305X_ESW_PORTS_NOCPU \
179 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
180
181 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
182
183 #define RT305X_ESW_PORTS_ALL \
184 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
185
186 #define RT305X_ESW_NUM_VLANS 16
187 #define RT305X_ESW_NUM_VIDS 4096
188 #define RT305X_ESW_NUM_PORTS 7
189 #define RT305X_ESW_NUM_LANWAN 6
190 #define RT305X_ESW_NUM_LEDS 5
191
192 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
193 #define RT5350_EWS_REG_LED_POLARITY 0x168
194 #define RT5350_RESET_EPHY BIT(24)
195 #define SYSC_REG_RESET_CTRL 0x34
196
197 enum {
198 /* Global attributes. */
199 RT305X_ESW_ATTR_ENABLE_VLAN,
200 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
201 RT305X_ESW_ATTR_BC_STATUS,
202 RT305X_ESW_ATTR_LED_FREQ,
203 /* Port attributes. */
204 RT305X_ESW_ATTR_PORT_DISABLE,
205 RT305X_ESW_ATTR_PORT_DOUBLETAG,
206 RT305X_ESW_ATTR_PORT_UNTAG,
207 RT305X_ESW_ATTR_PORT_LED,
208 RT305X_ESW_ATTR_PORT_LAN,
209 RT305X_ESW_ATTR_PORT_RECV_BAD,
210 RT305X_ESW_ATTR_PORT_RECV_GOOD,
211 RT5350_ESW_ATTR_PORT_TR_BAD,
212 RT5350_ESW_ATTR_PORT_TR_GOOD,
213 };
214
215 struct esw_port {
216 bool disable;
217 bool doubletag;
218 bool untag;
219 u8 led;
220 u16 pvid;
221 };
222
223 struct esw_vlan {
224 u8 ports;
225 u16 vid;
226 };
227
228 struct rt305x_esw {
229 struct device *dev;
230 void __iomem *base;
231 int irq;
232 const struct rt305x_esw_platform_data *pdata;
233 /* Protects against concurrent register rmw operations. */
234 spinlock_t reg_rw_lock;
235
236 unsigned char port_map;
237 unsigned int reg_initval_fct2;
238 unsigned int reg_initval_fpa2;
239 unsigned int reg_led_polarity;
240
241
242 struct switch_dev swdev;
243 bool global_vlan_enable;
244 bool alt_vlan_disable;
245 int bc_storm_protect;
246 int led_frequency;
247 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
248 struct esw_port ports[RT305X_ESW_NUM_PORTS];
249
250 };
251
252 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
253 {
254 __raw_writel(val, esw->base + reg);
255 }
256
257 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
258 {
259 return __raw_readl(esw->base + reg);
260 }
261
262 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
263 unsigned long val)
264 {
265 unsigned long t;
266
267 t = __raw_readl(esw->base + reg) & ~mask;
268 __raw_writel(t | val, esw->base + reg);
269 }
270
271 static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
272 unsigned long val)
273 {
274 unsigned long flags;
275
276 spin_lock_irqsave(&esw->reg_rw_lock, flags);
277 esw_rmw_raw(esw, reg, mask, val);
278 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
279 }
280
281 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
282 u32 write_data)
283 {
284 unsigned long t_start = jiffies;
285 int ret = 0;
286
287 while (1) {
288 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
289 RT305X_ESW_PCR1_WT_DONE))
290 break;
291 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
292 ret = 1;
293 goto out;
294 }
295 }
296
297 write_data &= 0xffff;
298 esw_w32(esw,
299 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
300 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
301 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
302 RT305X_ESW_REG_PCR0);
303
304 t_start = jiffies;
305 while (1) {
306 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
307 RT305X_ESW_PCR1_WT_DONE)
308 break;
309
310 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
311 ret = 1;
312 break;
313 }
314 }
315 out:
316 if (ret)
317 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
318 return ret;
319 }
320
321 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
322 {
323 unsigned s;
324 unsigned val;
325
326 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
327 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
328 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
329
330 return val;
331 }
332
333 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
334 {
335 unsigned s;
336
337 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
338 esw_rmw(esw,
339 RT305X_ESW_REG_VLANI(vlan / 2),
340 RT305X_ESW_VLANI_VID_M << s,
341 (vid & RT305X_ESW_VLANI_VID_M) << s);
342 }
343
344 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
345 {
346 unsigned s, val;
347
348 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
349 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
350 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
351 }
352
353 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
354 {
355 unsigned s;
356
357 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
358 esw_rmw(esw,
359 RT305X_ESW_REG_PVIDC(port / 2),
360 RT305X_ESW_PVIDC_PVID_M << s,
361 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
362 }
363
364 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
365 {
366 unsigned s, val;
367
368 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
369 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
370 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
371
372 return val;
373 }
374
375 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
376 {
377 unsigned s;
378
379 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
380 esw_rmw(esw,
381 RT305X_ESW_REG_VMSC(vlan / 4),
382 RT305X_ESW_VMSC_MSC_M << s,
383 (msc & RT305X_ESW_VMSC_MSC_M) << s);
384 }
385
386 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
387 {
388 unsigned reg;
389 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
390 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
391 RT305X_ESW_POC0_DIS_PORT_M;
392 }
393
394 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
395 {
396 unsigned old_mask;
397 unsigned enable_mask;
398 unsigned changed;
399 int i;
400
401 old_mask = esw_get_port_disable(esw);
402 changed = old_mask ^ disable_mask;
403 enable_mask = old_mask & disable_mask;
404
405 /* enable before writing to MII */
406 esw_rmw(esw, RT305X_ESW_REG_POC0,
407 (RT305X_ESW_POC0_DIS_PORT_M <<
408 RT305X_ESW_POC0_DIS_PORT_S),
409 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
410
411 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
412 if (!(changed & (1 << i)))
413 continue;
414 if (disable_mask & (1 << i)) {
415 /* disable */
416 rt305x_mii_write(esw, i, MII_BMCR,
417 BMCR_PDOWN);
418 } else {
419 /* enable */
420 rt305x_mii_write(esw, i, MII_BMCR,
421 BMCR_FULLDPLX |
422 BMCR_ANENABLE |
423 BMCR_ANRESTART |
424 BMCR_SPEED100);
425 }
426 }
427
428 /* disable after writing to MII */
429 esw_rmw(esw, RT305X_ESW_REG_POC0,
430 (RT305X_ESW_POC0_DIS_PORT_M <<
431 RT305X_ESW_POC0_DIS_PORT_S),
432 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
433 }
434
435 static void esw_set_gsc(struct rt305x_esw *esw)
436 {
437 esw_rmw(esw, RT305X_ESW_REG_SGC,
438 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
439 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
440 esw_rmw(esw, RT305X_ESW_REG_SGC,
441 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
442 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
443 }
444
445 static int esw_apply_config(struct switch_dev *dev);
446
447 static void esw_hw_init(struct rt305x_esw *esw)
448 {
449 int i;
450 u8 port_disable = 0;
451 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
452
453 /* vodoo from original driver */
454 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
455 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
456 /* Port priority 1 for all ports, vlan enabled. */
457 esw_w32(esw, 0x00005555 |
458 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
459 RT305X_ESW_REG_PFC1);
460
461 /* Enable Back Pressure, and Flow Control */
462 esw_w32(esw,
463 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
464 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
465 RT305X_ESW_REG_POC0);
466
467 /* Enable Aging, and VLAN TAG removal */
468 esw_w32(esw,
469 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
470 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
471 RT305X_ESW_REG_POC2);
472
473 if (esw->reg_initval_fct2)
474 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
475 else
476 esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
477
478 /*
479 * 300s aging timer, max packet len 1536, broadcast storm prevention
480 * disabled, disable collision abort, mac xor48 hash, 10 packet back
481 * pressure jam, GMII disable was_transmit, back pressure disabled,
482 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
483 * ports.
484 */
485 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
486
487 /* Setup SoC Port control register */
488 esw_w32(esw,
489 (RT305X_ESW_SOCPC_CRC_PADDING |
490 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
491 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
492 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
493 RT305X_ESW_REG_SOCPC);
494
495 if (esw->reg_initval_fpa2)
496 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
497 else
498 esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
499 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
500
501 /* Force Link/Activity on ports */
502 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
503 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
504 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
505 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
506 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
507
508 /* Copy disabled port configuration from bootloader setup */
509 port_disable = esw_get_port_disable(esw);
510 for (i = 0; i < 6; i++)
511 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
512
513 if (soc_is_rt3352()) {
514 /* reset EPHY */
515 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
516 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
517 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
518
519 rt305x_mii_write(esw, 0, 31, 0x8000);
520 for (i = 0; i < 5; i++) {
521 if (esw->ports[i].disable) {
522 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
523 } else {
524 rt305x_mii_write(esw, i, MII_BMCR,
525 BMCR_FULLDPLX |
526 BMCR_ANENABLE |
527 BMCR_SPEED100);
528 }
529 /* TX10 waveform coefficient LSB=0 disable PHY */
530 rt305x_mii_write(esw, i, 26, 0x1601);
531 /* TX100/TX10 AD/DA current bias */
532 rt305x_mii_write(esw, i, 29, 0x7016);
533 /* TX100 slew rate control */
534 rt305x_mii_write(esw, i, 30, 0x0038);
535 }
536
537 /* select global register */
538 rt305x_mii_write(esw, 0, 31, 0x0);
539 /* enlarge agcsel threshold 3 and threshold 2 */
540 rt305x_mii_write(esw, 0, 1, 0x4a40);
541 /* enlarge agcsel threshold 5 and threshold 4 */
542 rt305x_mii_write(esw, 0, 2, 0x6254);
543 /* enlarge agcsel threshold */
544 rt305x_mii_write(esw, 0, 3, 0xa17f);
545 rt305x_mii_write(esw, 0,12, 0x7eaa);
546 /* longer TP_IDL tail length */
547 rt305x_mii_write(esw, 0, 14, 0x65);
548 /* increased squelch pulse count threshold. */
549 rt305x_mii_write(esw, 0, 16, 0x0684);
550 /* set TX10 signal amplitude threshold to minimum */
551 rt305x_mii_write(esw, 0, 17, 0x0fe0);
552 /* set squelch amplitude to higher threshold */
553 rt305x_mii_write(esw, 0, 18, 0x40ba);
554 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
555 rt305x_mii_write(esw, 0, 22, 0x253f);
556 /* set PLL/Receive bias current are calibrated */
557 rt305x_mii_write(esw, 0, 27, 0x2fda);
558 /* change PLL/Receive bias current to internal(RT3350) */
559 rt305x_mii_write(esw, 0, 28, 0xc410);
560 /* change PLL bias current to internal(RT3052_MP3) */
561 rt305x_mii_write(esw, 0, 29, 0x598b);
562 /* select local register */
563 rt305x_mii_write(esw, 0, 31, 0x8000);
564 } else if (soc_is_rt5350()) {
565 /* reset EPHY */
566 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
567 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
568 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
569
570 /* set the led polarity */
571 esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
572
573 /* local registers */
574 rt305x_mii_write(esw, 0, 31, 0x8000);
575 for (i = 0; i < 5; i++) {
576 if (esw->ports[i].disable) {
577 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
578 } else {
579 rt305x_mii_write(esw, i, MII_BMCR,
580 BMCR_FULLDPLX |
581 BMCR_ANENABLE |
582 BMCR_SPEED100);
583 }
584 /* TX10 waveform coefficient LSB=0 disable PHY */
585 rt305x_mii_write(esw, i, 26, 0x1601);
586 /* TX100/TX10 AD/DA current bias */
587 rt305x_mii_write(esw, i, 29, 0x7015);
588 /* TX100 slew rate control */
589 rt305x_mii_write(esw, i, 30, 0x0038);
590 }
591
592 /* global registers */
593 rt305x_mii_write(esw, 0, 31, 0x0);
594 /* enlarge agcsel threshold 3 and threshold 2 */
595 rt305x_mii_write(esw, 0, 1, 0x4a40);
596 /* enlarge agcsel threshold 5 and threshold 4 */
597 rt305x_mii_write(esw, 0, 2, 0x6254);
598 /* enlarge agcsel threshold 6 */
599 rt305x_mii_write(esw, 0, 3, 0xa17f);
600 rt305x_mii_write(esw, 0, 12, 0x7eaa);
601 /* longer TP_IDL tail length */
602 rt305x_mii_write(esw, 0, 14, 0x65);
603 /* increased squelch pulse count threshold. */
604 rt305x_mii_write(esw, 0, 16, 0x0684);
605 /* set TX10 signal amplitude threshold to minimum */
606 rt305x_mii_write(esw, 0, 17, 0x0fe0);
607 /* set squelch amplitude to higher threshold */
608 rt305x_mii_write(esw, 0, 18, 0x40ba);
609 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
610 rt305x_mii_write(esw, 0, 22, 0x253f);
611 /* set PLL/Receive bias current are calibrated */
612 rt305x_mii_write(esw, 0, 27, 0x2fda);
613 /* change PLL/Receive bias current to internal(RT3350) */
614 rt305x_mii_write(esw, 0, 28, 0xc410);
615 /* change PLL bias current to internal(RT3052_MP3) */
616 rt305x_mii_write(esw, 0, 29, 0x598b);
617 /* select local register */
618 rt305x_mii_write(esw, 0, 31, 0x8000);
619 } else {
620 rt305x_mii_write(esw, 0, 31, 0x8000);
621 for (i = 0; i < 5; i++) {
622 if (esw->ports[i].disable) {
623 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
624 } else {
625 rt305x_mii_write(esw, i, MII_BMCR,
626 BMCR_FULLDPLX |
627 BMCR_ANENABLE |
628 BMCR_SPEED100);
629 }
630 /* TX10 waveform coefficient */
631 rt305x_mii_write(esw, i, 26, 0x1601);
632 /* TX100/TX10 AD/DA current bias */
633 rt305x_mii_write(esw, i, 29, 0x7058);
634 /* TX100 slew rate control */
635 rt305x_mii_write(esw, i, 30, 0x0018);
636 }
637
638 /* PHY IOT */
639 /* select global register */
640 rt305x_mii_write(esw, 0, 31, 0x0);
641 /* tune TP_IDL tail and head waveform */
642 rt305x_mii_write(esw, 0, 22, 0x052f);
643 /* set TX10 signal amplitude threshold to minimum */
644 rt305x_mii_write(esw, 0, 17, 0x0fe0);
645 /* set squelch amplitude to higher threshold */
646 rt305x_mii_write(esw, 0, 18, 0x40ba);
647 /* longer TP_IDL tail length */
648 rt305x_mii_write(esw, 0, 14, 0x65);
649 /* select local register */
650 rt305x_mii_write(esw, 0, 31, 0x8000);
651 }
652
653 if (esw->port_map)
654 port_map = esw->port_map;
655 else
656 port_map = RT305X_ESW_PMAP_LLLLLL;
657
658 /*
659 * Unused HW feature, but still nice to be consistent here...
660 * This is also exported to userspace ('lan' attribute) so it's
661 * conveniently usable to decide which ports go into the wan vlan by
662 * default.
663 */
664 esw_rmw(esw, RT305X_ESW_REG_SGC2,
665 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
666 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
667
668 /* make the switch leds blink */
669 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
670 esw->ports[i].led = 0x05;
671
672 /* Apply the empty config. */
673 esw_apply_config(&esw->swdev);
674
675 /* Only unmask the port change interrupt */
676 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
677 }
678
679 static irqreturn_t esw_interrupt(int irq, void *_esw)
680 {
681 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
682 u32 status;
683
684 status = esw_r32(esw, RT305X_ESW_REG_ISR);
685 if (status & RT305X_ESW_PORT_ST_CHG) {
686 u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
687 link >>= RT305X_ESW_POA_LINK_SHIFT;
688 link &= RT305X_ESW_POA_LINK_MASK;
689 dev_info(esw->dev, "link changed 0x%02X\n", link);
690 }
691 esw_w32(esw, status, RT305X_ESW_REG_ISR);
692
693 return IRQ_HANDLED;
694 }
695
696 static int esw_apply_config(struct switch_dev *dev)
697 {
698 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
699 int i;
700 u8 disable = 0;
701 u8 doubletag = 0;
702 u8 en_vlan = 0;
703 u8 untag = 0;
704
705 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
706 u32 vid, vmsc;
707 if (esw->global_vlan_enable) {
708 vid = esw->vlans[i].vid;
709 vmsc = esw->vlans[i].ports;
710 } else {
711 vid = RT305X_ESW_VLAN_NONE;
712 vmsc = RT305X_ESW_PORTS_NONE;
713 }
714 esw_set_vlan_id(esw, i, vid);
715 esw_set_vmsc(esw, i, vmsc);
716 }
717
718 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
719 u32 pvid;
720 disable |= esw->ports[i].disable << i;
721 if (esw->global_vlan_enable) {
722 doubletag |= esw->ports[i].doubletag << i;
723 en_vlan |= 1 << i;
724 untag |= esw->ports[i].untag << i;
725 pvid = esw->ports[i].pvid;
726 } else {
727 int x = esw->alt_vlan_disable ? 0 : 1;
728 doubletag |= x << i;
729 en_vlan |= x << i;
730 untag |= x << i;
731 pvid = 0;
732 }
733 esw_set_pvid(esw, i, pvid);
734 if (i < RT305X_ESW_NUM_LEDS)
735 esw_w32(esw, esw->ports[i].led,
736 RT305X_ESW_REG_P0LED + 4*i);
737 }
738
739 esw_set_gsc(esw);
740 esw_set_port_disable(esw, disable);
741 esw_rmw(esw, RT305X_ESW_REG_SGC2,
742 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
743 RT305X_ESW_SGC2_DOUBLE_TAG_S),
744 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
745 esw_rmw(esw, RT305X_ESW_REG_PFC1,
746 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
747 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
748 esw_rmw(esw, RT305X_ESW_REG_POC2,
749 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
750 untag << RT305X_ESW_POC2_UNTAG_EN_S);
751
752 if (!esw->global_vlan_enable) {
753 /*
754 * Still need to put all ports into vlan 0 or they'll be
755 * isolated.
756 * NOTE: vlan 0 is special, no vlan tag is prepended
757 */
758 esw_set_vlan_id(esw, 0, 0);
759 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
760 }
761
762 return 0;
763 }
764
765 static int esw_reset_switch(struct switch_dev *dev)
766 {
767 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
768
769 esw->global_vlan_enable = 0;
770 memset(esw->ports, 0, sizeof(esw->ports));
771 memset(esw->vlans, 0, sizeof(esw->vlans));
772 esw_hw_init(esw);
773
774 return 0;
775 }
776
777 static int esw_get_vlan_enable(struct switch_dev *dev,
778 const struct switch_attr *attr,
779 struct switch_val *val)
780 {
781 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
782
783 val->value.i = esw->global_vlan_enable;
784
785 return 0;
786 }
787
788 static int esw_set_vlan_enable(struct switch_dev *dev,
789 const struct switch_attr *attr,
790 struct switch_val *val)
791 {
792 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
793
794 esw->global_vlan_enable = val->value.i != 0;
795
796 return 0;
797 }
798
799 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
800 const struct switch_attr *attr,
801 struct switch_val *val)
802 {
803 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
804
805 val->value.i = esw->alt_vlan_disable;
806
807 return 0;
808 }
809
810 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
811 const struct switch_attr *attr,
812 struct switch_val *val)
813 {
814 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
815
816 esw->alt_vlan_disable = val->value.i != 0;
817
818 return 0;
819 }
820
821 static int
822 rt305x_esw_set_bc_status(struct switch_dev *dev,
823 const struct switch_attr *attr,
824 struct switch_val *val)
825 {
826 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
827
828 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
829
830 return 0;
831 }
832
833 static int
834 rt305x_esw_get_bc_status(struct switch_dev *dev,
835 const struct switch_attr *attr,
836 struct switch_val *val)
837 {
838 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
839
840 val->value.i = esw->bc_storm_protect;
841
842 return 0;
843 }
844
845 static int
846 rt305x_esw_set_led_freq(struct switch_dev *dev,
847 const struct switch_attr *attr,
848 struct switch_val *val)
849 {
850 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
851
852 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
853
854 return 0;
855 }
856
857 static int
858 rt305x_esw_get_led_freq(struct switch_dev *dev,
859 const struct switch_attr *attr,
860 struct switch_val *val)
861 {
862 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
863
864 val->value.i = esw->led_frequency;
865
866 return 0;
867 }
868
869 static int esw_get_port_link(struct switch_dev *dev,
870 int port,
871 struct switch_port_link *link)
872 {
873 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
874 u32 speed, poa;
875
876 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
877 return -EINVAL;
878
879 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
880
881 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
882 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
883 if (port < RT305X_ESW_NUM_LEDS) {
884 speed = (poa >> RT305X_ESW_SPD_S) & 1;
885 } else {
886 if (port == RT305X_ESW_NUM_PORTS - 1)
887 poa >>= 1;
888 speed = (poa >> RT305X_ESW_SPD_S) & 3;
889 }
890 switch (speed) {
891 case 0:
892 link->speed = SWITCH_PORT_SPEED_10;
893 break;
894 case 1:
895 link->speed = SWITCH_PORT_SPEED_100;
896 break;
897 case 2:
898 case 3: /* forced gige speed can be 2 or 3 */
899 link->speed = SWITCH_PORT_SPEED_1000;
900 break;
901 default:
902 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
903 break;
904 }
905
906 return 0;
907 }
908
909 static int esw_get_port_bool(struct switch_dev *dev,
910 const struct switch_attr *attr,
911 struct switch_val *val)
912 {
913 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
914 int idx = val->port_vlan;
915 u32 x, reg, shift;
916
917 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
918 return -EINVAL;
919
920 switch (attr->id) {
921 case RT305X_ESW_ATTR_PORT_DISABLE:
922 reg = RT305X_ESW_REG_POC0;
923 shift = RT305X_ESW_POC0_DIS_PORT_S;
924 break;
925 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
926 reg = RT305X_ESW_REG_SGC2;
927 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
928 break;
929 case RT305X_ESW_ATTR_PORT_UNTAG:
930 reg = RT305X_ESW_REG_POC2;
931 shift = RT305X_ESW_POC2_UNTAG_EN_S;
932 break;
933 case RT305X_ESW_ATTR_PORT_LAN:
934 reg = RT305X_ESW_REG_SGC2;
935 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
936 if (idx >= RT305X_ESW_NUM_LANWAN)
937 return -EINVAL;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 x = esw_r32(esw, reg);
944 val->value.i = (x >> (idx + shift)) & 1;
945
946 return 0;
947 }
948
949 static int esw_set_port_bool(struct switch_dev *dev,
950 const struct switch_attr *attr,
951 struct switch_val *val)
952 {
953 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
954 int idx = val->port_vlan;
955
956 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
957 val->value.i < 0 || val->value.i > 1)
958 return -EINVAL;
959
960 switch (attr->id) {
961 case RT305X_ESW_ATTR_PORT_DISABLE:
962 esw->ports[idx].disable = val->value.i;
963 break;
964 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
965 esw->ports[idx].doubletag = val->value.i;
966 break;
967 case RT305X_ESW_ATTR_PORT_UNTAG:
968 esw->ports[idx].untag = val->value.i;
969 break;
970 default:
971 return -EINVAL;
972 }
973
974 return 0;
975 }
976
977 static int esw_get_port_recv_badgood(struct switch_dev *dev,
978 const struct switch_attr *attr,
979 struct switch_val *val)
980 {
981 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
982 int idx = val->port_vlan;
983 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
984 u32 reg;
985
986 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
987 return -EINVAL;
988 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
989 val->value.i = (reg >> shift) & 0xffff;
990
991 return 0;
992 }
993
994 static int
995 esw_get_port_tr_badgood(struct switch_dev *dev,
996 const struct switch_attr *attr,
997 struct switch_val *val)
998 {
999 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1000
1001 int idx = val->port_vlan;
1002 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1003 u32 reg;
1004
1005 if (!soc_is_rt5350())
1006 return -EINVAL;
1007
1008 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1009 return -EINVAL;
1010
1011 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1012 val->value.i = (reg >> shift) & 0xffff;
1013
1014 return 0;
1015 }
1016
1017 static int esw_get_port_led(struct switch_dev *dev,
1018 const struct switch_attr *attr,
1019 struct switch_val *val)
1020 {
1021 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1022 int idx = val->port_vlan;
1023
1024 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1025 idx >= RT305X_ESW_NUM_LEDS)
1026 return -EINVAL;
1027
1028 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1029
1030 return 0;
1031 }
1032
1033 static int esw_set_port_led(struct switch_dev *dev,
1034 const struct switch_attr *attr,
1035 struct switch_val *val)
1036 {
1037 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1038 int idx = val->port_vlan;
1039
1040 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1041 return -EINVAL;
1042
1043 esw->ports[idx].led = val->value.i;
1044
1045 return 0;
1046 }
1047
1048 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1049 {
1050 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1051
1052 if (port >= RT305X_ESW_NUM_PORTS)
1053 return -EINVAL;
1054
1055 *val = esw_get_pvid(esw, port);
1056
1057 return 0;
1058 }
1059
1060 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1061 {
1062 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1063
1064 if (port >= RT305X_ESW_NUM_PORTS)
1065 return -EINVAL;
1066
1067 esw->ports[port].pvid = val;
1068
1069 return 0;
1070 }
1071
1072 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1073 {
1074 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1075 u32 vmsc, poc2;
1076 int vlan_idx = -1;
1077 int i;
1078
1079 val->len = 0;
1080
1081 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1082 return -EINVAL;
1083
1084 /* valid vlan? */
1085 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1086 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1087 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1088 vlan_idx = i;
1089 break;
1090 }
1091 }
1092
1093 if (vlan_idx == -1)
1094 return -EINVAL;
1095
1096 vmsc = esw_get_vmsc(esw, vlan_idx);
1097 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1098
1099 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1100 struct switch_port *p;
1101 int port_mask = 1 << i;
1102
1103 if (!(vmsc & port_mask))
1104 continue;
1105
1106 p = &val->value.ports[val->len++];
1107 p->id = i;
1108 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1109 p->flags = 0;
1110 else
1111 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1112 }
1113
1114 return 0;
1115 }
1116
1117 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1118 {
1119 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1120 int ports;
1121 int vlan_idx = -1;
1122 int i;
1123
1124 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1125 val->len > RT305X_ESW_NUM_PORTS)
1126 return -EINVAL;
1127
1128 /* one of the already defined vlans? */
1129 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1130 if (esw->vlans[i].vid == val->port_vlan &&
1131 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1132 vlan_idx = i;
1133 break;
1134 }
1135 }
1136
1137 /* select a free slot */
1138 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1139 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1140 vlan_idx = i;
1141 }
1142
1143 /* bail if all slots are in use */
1144 if (vlan_idx == -1)
1145 return -EINVAL;
1146
1147 ports = RT305X_ESW_PORTS_NONE;
1148 for (i = 0; i < val->len; i++) {
1149 struct switch_port *p = &val->value.ports[i];
1150 int port_mask = 1 << p->id;
1151 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1152
1153 if (p->id >= RT305X_ESW_NUM_PORTS)
1154 return -EINVAL;
1155
1156 ports |= port_mask;
1157 esw->ports[p->id].untag = untagged;
1158 }
1159 esw->vlans[vlan_idx].ports = ports;
1160 if (ports == RT305X_ESW_PORTS_NONE)
1161 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1162 else
1163 esw->vlans[vlan_idx].vid = val->port_vlan;
1164
1165 return 0;
1166 }
1167
1168 static const struct switch_attr esw_global[] = {
1169 {
1170 .type = SWITCH_TYPE_INT,
1171 .name = "enable_vlan",
1172 .description = "VLAN mode (1:enabled)",
1173 .max = 1,
1174 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1175 .get = esw_get_vlan_enable,
1176 .set = esw_set_vlan_enable,
1177 },
1178 {
1179 .type = SWITCH_TYPE_INT,
1180 .name = "alternate_vlan_disable",
1181 .description = "Use en_vlan instead of doubletag to disable"
1182 " VLAN mode",
1183 .max = 1,
1184 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1185 .get = esw_get_alt_vlan_disable,
1186 .set = esw_set_alt_vlan_disable,
1187 },
1188 {
1189 .type = SWITCH_TYPE_INT,
1190 .name = "bc_storm_protect",
1191 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1192 .max = 3,
1193 .id = RT305X_ESW_ATTR_BC_STATUS,
1194 .get = rt305x_esw_get_bc_status,
1195 .set = rt305x_esw_set_bc_status,
1196 },
1197 {
1198 .type = SWITCH_TYPE_INT,
1199 .name = "led_frequency",
1200 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1201 .max = 3,
1202 .id = RT305X_ESW_ATTR_LED_FREQ,
1203 .get = rt305x_esw_get_led_freq,
1204 .set = rt305x_esw_set_led_freq,
1205 }
1206 };
1207
1208 static const struct switch_attr esw_port[] = {
1209 {
1210 .type = SWITCH_TYPE_INT,
1211 .name = "disable",
1212 .description = "Port state (1:disabled)",
1213 .max = 1,
1214 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1215 .get = esw_get_port_bool,
1216 .set = esw_set_port_bool,
1217 },
1218 {
1219 .type = SWITCH_TYPE_INT,
1220 .name = "doubletag",
1221 .description = "Double tagging for incoming vlan packets "
1222 "(1:enabled)",
1223 .max = 1,
1224 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1225 .get = esw_get_port_bool,
1226 .set = esw_set_port_bool,
1227 },
1228 {
1229 .type = SWITCH_TYPE_INT,
1230 .name = "untag",
1231 .description = "Untag (1:strip outgoing vlan tag)",
1232 .max = 1,
1233 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1234 .get = esw_get_port_bool,
1235 .set = esw_set_port_bool,
1236 },
1237 {
1238 .type = SWITCH_TYPE_INT,
1239 .name = "led",
1240 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1241 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1242 " 8:100mact, 10:blink, 11:off, 12:on)",
1243 .max = 15,
1244 .id = RT305X_ESW_ATTR_PORT_LED,
1245 .get = esw_get_port_led,
1246 .set = esw_set_port_led,
1247 },
1248 {
1249 .type = SWITCH_TYPE_INT,
1250 .name = "lan",
1251 .description = "HW port group (0:wan, 1:lan)",
1252 .max = 1,
1253 .id = RT305X_ESW_ATTR_PORT_LAN,
1254 .get = esw_get_port_bool,
1255 },
1256 {
1257 .type = SWITCH_TYPE_INT,
1258 .name = "recv_bad",
1259 .description = "Receive bad packet counter",
1260 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1261 .get = esw_get_port_recv_badgood,
1262 },
1263 {
1264 .type = SWITCH_TYPE_INT,
1265 .name = "recv_good",
1266 .description = "Receive good packet counter",
1267 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1268 .get = esw_get_port_recv_badgood,
1269 },
1270 {
1271 .type = SWITCH_TYPE_INT,
1272 .name = "tr_bad",
1273
1274 .description = "Transmit bad packet counter. rt5350 only",
1275 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1276 .get = esw_get_port_tr_badgood,
1277 },
1278 {
1279 .type = SWITCH_TYPE_INT,
1280 .name = "tr_good",
1281
1282 .description = "Transmit good packet counter. rt5350 only",
1283 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1284 .get = esw_get_port_tr_badgood,
1285 },
1286 };
1287
1288 static const struct switch_attr esw_vlan[] = {
1289 };
1290
1291 static const struct switch_dev_ops esw_ops = {
1292 .attr_global = {
1293 .attr = esw_global,
1294 .n_attr = ARRAY_SIZE(esw_global),
1295 },
1296 .attr_port = {
1297 .attr = esw_port,
1298 .n_attr = ARRAY_SIZE(esw_port),
1299 },
1300 .attr_vlan = {
1301 .attr = esw_vlan,
1302 .n_attr = ARRAY_SIZE(esw_vlan),
1303 },
1304 .get_vlan_ports = esw_get_vlan_ports,
1305 .set_vlan_ports = esw_set_vlan_ports,
1306 .get_port_pvid = esw_get_port_pvid,
1307 .set_port_pvid = esw_set_port_pvid,
1308 .get_port_link = esw_get_port_link,
1309 .apply_config = esw_apply_config,
1310 .reset_switch = esw_reset_switch,
1311 };
1312
1313 static struct rt305x_esw_platform_data rt3050_esw_data = {
1314 /* All ports are LAN ports. */
1315 .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1316 .reg_initval_fct2 = 0x00d6500c,
1317 /*
1318 * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1319 * turbo mii off, rgmi 3.3v off
1320 * port5: disabled
1321 * port6: enabled, gige, full-duplex, rx/tx-flow-control
1322 */
1323 .reg_initval_fpa2 = 0x3f502b28,
1324 };
1325
1326 static const struct of_device_id ralink_esw_match[] = {
1327 { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1328 {},
1329 };
1330 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1331
1332 static int esw_probe(struct platform_device *pdev)
1333 {
1334 struct device_node *np = pdev->dev.of_node;
1335 const struct rt305x_esw_platform_data *pdata;
1336 const __be32 *port_map, *reg_init;
1337 struct rt305x_esw *esw;
1338 struct switch_dev *swdev;
1339 struct resource *res, *irq;
1340 int err;
1341
1342 pdata = pdev->dev.platform_data;
1343 if (!pdata) {
1344 const struct of_device_id *match;
1345 match = of_match_device(ralink_esw_match, &pdev->dev);
1346 if (match)
1347 pdata = (struct rt305x_esw_platform_data *) match->data;
1348 }
1349 if (!pdata)
1350 return -EINVAL;
1351
1352 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1353 if (!res) {
1354 dev_err(&pdev->dev, "no memory resource found\n");
1355 return -ENOMEM;
1356 }
1357
1358 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1359 if (!irq) {
1360 dev_err(&pdev->dev, "no irq resource found\n");
1361 return -ENOMEM;
1362 }
1363
1364 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1365 if (!esw) {
1366 dev_err(&pdev->dev, "no memory for private data\n");
1367 return -ENOMEM;
1368 }
1369
1370 esw->dev = &pdev->dev;
1371 esw->irq = irq->start;
1372 esw->base = ioremap(res->start, resource_size(res));
1373 if (!esw->base) {
1374 dev_err(&pdev->dev, "ioremap failed\n");
1375 err = -ENOMEM;
1376 goto free_esw;
1377 }
1378
1379 port_map = of_get_property(np, "ralink,portmap", NULL);
1380 if (port_map)
1381 esw->port_map = be32_to_cpu(*port_map);
1382
1383 reg_init = of_get_property(np, "ralink,fct2", NULL);
1384 if (reg_init)
1385 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1386
1387 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1388 if (reg_init)
1389 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1390
1391 reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1392 if (reg_init)
1393 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1394
1395 swdev = &esw->swdev;
1396 swdev->of_node = pdev->dev.of_node;
1397 swdev->name = "rt305x-esw";
1398 swdev->alias = "rt305x";
1399 swdev->cpu_port = RT305X_ESW_PORT6;
1400 swdev->ports = RT305X_ESW_NUM_PORTS;
1401 swdev->vlans = RT305X_ESW_NUM_VIDS;
1402 swdev->ops = &esw_ops;
1403
1404 err = register_switch(swdev, NULL);
1405 if (err < 0) {
1406 dev_err(&pdev->dev, "register_switch failed\n");
1407 goto unmap_base;
1408 }
1409
1410 platform_set_drvdata(pdev, esw);
1411
1412 esw->pdata = pdata;
1413 spin_lock_init(&esw->reg_rw_lock);
1414
1415 esw_hw_init(esw);
1416
1417 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1418 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1419 request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1420
1421 return 0;
1422
1423 unmap_base:
1424 iounmap(esw->base);
1425 free_esw:
1426 kfree(esw);
1427 return err;
1428 }
1429
1430 static int esw_remove(struct platform_device *pdev)
1431 {
1432 struct rt305x_esw *esw;
1433
1434 esw = platform_get_drvdata(pdev);
1435 if (esw) {
1436 unregister_switch(&esw->swdev);
1437 platform_set_drvdata(pdev, NULL);
1438 iounmap(esw->base);
1439 kfree(esw);
1440 }
1441
1442 return 0;
1443 }
1444
1445 static struct platform_driver esw_driver = {
1446 .probe = esw_probe,
1447 .remove = esw_remove,
1448 .driver = {
1449 .name = "rt305x-esw",
1450 .owner = THIS_MODULE,
1451 .of_match_table = ralink_esw_match,
1452 },
1453 };
1454
1455 int __init rtesw_init(void)
1456 {
1457 return platform_driver_register(&esw_driver);
1458 }
1459
1460 void rtesw_exit(void)
1461 {
1462 platform_driver_unregister(&esw_driver);
1463 }
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