ralink: mt7628 does not actually need this fix for the ethernet driver
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / soc_rt305x.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19
20 #include <asm/mach-ralink/ralink_regs.h>
21 #ifdef CONFIG_SOC_MT7620
22 static inline int soc_is_rt3352(void)
23 {
24 return 0;
25 }
26
27 static inline int soc_is_rt3052(void)
28 {
29 return 0;
30 }
31 #else
32 #include <asm/mach-ralink/rt305x.h>
33 #endif
34
35 #include "ralink_soc_eth.h"
36 #include "mdio_rt2880.h"
37
38 #define RT305X_RESET_FE BIT(21)
39 #define RT305X_RESET_ESW BIT(23)
40 #define SYSC_REG_RESET_CTRL 0x034
41
42 static const u32 rt5350_reg_table[FE_REG_COUNT] = {
43 [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
44 [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
45 [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
46 [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
47 [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
48 [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
49 [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
50 [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
51 [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
52 [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
53 [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
54 [FE_REG_FE_DMA_VID_BASE] = 0,
55 };
56
57 static void rt305x_init_data(struct fe_soc_data *data,
58 struct net_device *netdev)
59 {
60 struct fe_priv *priv = netdev_priv(netdev);
61
62 priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG;
63 netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
64 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
65 }
66
67 static int rt3050_fwd_config(struct fe_priv *priv)
68 {
69 int ret;
70
71 if (soc_is_rt3052()) {
72 ret = fe_set_clock_cycle(priv);
73 if (ret)
74 return ret;
75 }
76
77 fe_fwd_config(priv);
78 if (!soc_is_rt3352())
79 fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
80 fe_csum_config(priv);
81
82 return 0;
83 }
84
85 static void rt305x_fe_reset(void)
86 {
87 rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
88 rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
89 }
90
91 static void rt5350_init_data(struct fe_soc_data *data,
92 struct net_device *netdev)
93 {
94 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
95 }
96
97 static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
98 {
99 unsigned long flags;
100
101 spin_lock_irqsave(&priv->page_lock, flags);
102 fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
103 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
104 RT5350_SDM_MAC_ADRL);
105 spin_unlock_irqrestore(&priv->page_lock, flags);
106 }
107
108 static void rt5350_rxcsum_config(bool enable)
109 {
110 if (enable)
111 fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
112 RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
113 RT5350_SDM_CFG);
114 else
115 fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
116 RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
117 RT5350_SDM_CFG);
118 }
119
120 static int rt5350_fwd_config(struct fe_priv *priv)
121 {
122 struct net_device *dev = priv_netdev(priv);
123
124 rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
125
126 return 0;
127 }
128
129 static void rt5350_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
130 {
131 priv->tx_dma[idx].txd4 = 0;
132 }
133
134 static void rt5350_fe_reset(void)
135 {
136 rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
137 rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
138 }
139
140 static struct fe_soc_data rt3050_data = {
141 .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
142 .init_data = rt305x_init_data,
143 .reset_fe = rt305x_fe_reset,
144 .fwd_config = rt3050_fwd_config,
145 .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
146 .checksum_bit = RX_DMA_L4VALID,
147 .tx_udf_bit = TX_DMA_UDF,
148 .rx_dly_int = FE_RX_DLY_INT,
149 .tx_dly_int = FE_TX_DLY_INT,
150 };
151
152 static struct fe_soc_data rt5350_data = {
153 .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
154 .init_data = rt5350_init_data,
155 .reg_table = rt5350_reg_table,
156 .reset_fe = rt5350_fe_reset,
157 .set_mac = rt5350_set_mac,
158 .fwd_config = rt5350_fwd_config,
159 .tx_dma = rt5350_tx_dma,
160 .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
161 .checksum_bit = RX_DMA_L4VALID,
162 .tx_udf_bit = TX_DMA_UDF,
163 .rx_dly_int = RT5350_RX_DLY_INT,
164 .tx_dly_int = RT5350_TX_DLY_INT,
165 };
166
167 const struct of_device_id of_fe_match[] = {
168 { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
169 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
170 {},
171 };
172
173 MODULE_DEVICE_TABLE(of, of_fe_match);