target/linux/ramips/files/drivers/net/ramips_esw.c

   1 #include <linux/ioport.h>
   2
   3 #include <rt305x_regs.h>
   4 #include <rt305x_esw_platform.h>
   5
   6 #define RT305X_ESW_REG_FCT0             0x08
   7 #define RT305X_ESW_REG_PFC1             0x14
   8 #define RT305X_ESW_REG_PVIDC(_n)        (0x48 + 4 * (_n))
   9 #define RT305X_ESW_REG_VLANI(_n)        (0x50 + 4 * (_n))
  10 #define RT305X_ESW_REG_VMSC(_n)         (0x70 + 4 * (_n))
  11 #define RT305X_ESW_REG_FPA              0x84
  12 #define RT305X_ESW_REG_SOCPC            0x8c
  13 #define RT305X_ESW_REG_POC1             0x90
  14 #define RT305X_ESW_REG_POC2             0x94
  15 #define RT305X_ESW_REG_POC3             0x98
  16 #define RT305X_ESW_REG_SGC              0x9c
  17 #define RT305X_ESW_REG_PCR0             0xc0
  18 #define RT305X_ESW_REG_PCR1             0xc4
  19 #define RT305X_ESW_REG_FPA2             0xc8
  20 #define RT305X_ESW_REG_FCT2             0xcc
  21 #define RT305X_ESW_REG_SGC2             0xe4
  22
  23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S  16
  24 #define RT305X_ESW_PCR0_WT_PHY_CMD      BIT(13)
  25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S   8
  26
  27 #define RT305X_ESW_PCR1_WT_DONE         BIT(0)
  28
  29 #define RT305X_ESW_PHY_TIMEOUT          (5 * HZ)
  30
  31 #define RT305X_ESW_VLANI_VID_M          0xfff
  32 #define RT305X_ESW_VLANI_VID_S          12
  33
  34 struct rt305x_esw {
  35         void __iomem *base;
  36         struct rt305x_esw_platform_data *pdata;
  37         spinlock_t reg_rw_lock;
  38 };
  39
  40 static inline void
  41 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
  42 {
  43         __raw_writel(val, esw->base + reg);
  44 }
  45
  46 static inline u32
  47 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
  48 {
  49         return __raw_readl(esw->base + reg);
  50 }
  51
  52 static inline void
  53 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
  54                    unsigned long val)
  55 {
  56         unsigned long t;
  57
  58         t = __raw_readl(esw->base + reg) & ~mask;
  59         __raw_writel(t | val, esw->base + reg);
  60 }
  61
  62 static void
  63 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
  64                unsigned long val)
  65 {
  66         unsigned long flags;
  67
  68         spin_lock_irqsave(&esw->reg_rw_lock, flags);
  69         rt305x_esw_rmw_raw(esw, reg, mask, val);
  70         spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
  71 }
  72
  73 static u32
  74 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
  75                  u32 write_data)
  76 {
  77         unsigned long t_start = jiffies;
  78         int ret = 0;
  79
  80         while (1) {
  81                 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
  82                       RT305X_ESW_PCR1_WT_DONE))
  83                         break;
  84                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
  85                         ret = 1;
  86                         goto out;
  87                 }
  88         }
  89
  90         write_data &= 0xffff;
  91         rt305x_esw_wr(esw,
  92                       (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
  93                       (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
  94                       (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
  95                       RT305X_ESW_REG_PCR0);
  96
  97         t_start = jiffies;
  98         while (1) {
  99                 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 100                     RT305X_ESW_PCR1_WT_DONE)
 101                         break;
 102
 103                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 104                         ret = 1;
 105                         break;
 106                 }
 107         }
 108 out:
 109         if (ret)
 110                 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 111         return ret;
 112 }
 113
 114 static void
 115 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 116 {
 117         unsigned s;
 118
 119         s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 120         rt305x_esw_rmw(esw,
 121                        RT305X_ESW_REG_VLANI(vlan / 2),
 122                        RT305X_ESW_VLANI_VID_M << s,
 123                        (vid & RT305X_ESW_VLANI_VID_M) << s);
 124 }
 125
 126 static void
 127 rt305x_esw_hw_init(struct rt305x_esw *esw)
 128 {
 129         int i;
 130
 131         /* vodoo from original driver */
 132         rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 133         rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 134         rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
 135         rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
 136         rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
 137         rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
 138         rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 139         rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
 140         rt305x_esw_wr(esw, 0x00001002, RT305X_ESW_REG_PVIDC(2));
 141         rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
 142         rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
 143
 144         rt305x_mii_write(esw, 0, 31, 0x8000);
 145         for (i = 0; i < 5; i++) {
 146                 /* TX10 waveform coefficient */
 147                 rt305x_mii_write(esw, i, 0, 0x3100);
 148                 /* TX10 waveform coefficient */
 149                 rt305x_mii_write(esw, i, 26, 0x1601);
 150                 /* TX100/TX10 AD/DA current bias */
 151                 rt305x_mii_write(esw, i, 29, 0x7058);
 152                 /* TX100 slew rate control */
 153                 rt305x_mii_write(esw, i, 30, 0x0018);
 154         }
 155
 156         /* PHY IOT */
 157         /* select global register */
 158         rt305x_mii_write(esw, 0, 31, 0x0);
 159         /* tune TP_IDL tail and head waveform */
 160         rt305x_mii_write(esw, 0, 22, 0x052f);
 161         /* set TX10 signal amplitude threshold to minimum */
 162         rt305x_mii_write(esw, 0, 17, 0x0fe0);
 163         /* set squelch amplitude to higher threshold */
 164         rt305x_mii_write(esw, 0, 18, 0x40ba);
 165         /* longer TP_IDL tail length */
 166         rt305x_mii_write(esw, 0, 14, 0x65);
 167         /* select local register */
 168         rt305x_mii_write(esw, 0, 31, 0x8000);
 169
 170         /* set default vlan */
 171         rt305x_esw_set_vlan_id(esw, 0, 1);
 172         rt305x_esw_set_vlan_id(esw, 1, 2);
 173         rt305x_esw_wr(esw, 0x504f, RT305X_ESW_REG_VMSC(0));
 174 }
 175
 176 static int
 177 rt305x_esw_probe(struct platform_device *pdev)
 178 {
 179         struct rt305x_esw_platform_data *pdata;
 180         struct rt305x_esw *esw;
 181         struct resource *res;
 182         int err;
 183
 184         pdata = pdev->dev.platform_data;
 185         if (!pdata)
 186                 return -EINVAL;
 187
 188         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 189         if (!res) {
 190                 dev_err(&pdev->dev, "no memory resource found\n");
 191                 return -ENOMEM;
 192         }
 193
 194         esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
 195         if (!esw) {
 196                 dev_err(&pdev->dev, "no memory for private data\n");
 197                 return -ENOMEM;
 198         }
 199
 200         esw->base = ioremap(res->start, resource_size(res));
 201         if (!esw->base) {
 202                 dev_err(&pdev->dev, "ioremap failed\n");
 203                 err = -ENOMEM;
 204                 goto free_esw;
 205         }
 206
 207         platform_set_drvdata(pdev, esw);
 208
 209         esw->pdata = pdata;
 210         spin_lock_init(&esw->reg_rw_lock);
 211         rt305x_esw_hw_init(esw);
 212
 213         return 0;
 214
 215 free_esw:
 216         kfree(esw);
 217         return err;
 218 }
 219
 220 static int
 221 rt305x_esw_remove(struct platform_device *pdev)
 222 {
 223         struct rt305x_esw *esw;
 224
 225         esw = platform_get_drvdata(pdev);
 226         if (esw) {
 227                 platform_set_drvdata(pdev, NULL);
 228                 iounmap(esw->base);
 229                 kfree(esw);
 230         }
 231
 232         return 0;
 233 }
 234
 235 static struct platform_driver rt305x_esw_driver = {
 236         .probe = rt305x_esw_probe,
 237         .remove = rt305x_esw_remove,
 238         .driver = {
 239                 .name = "rt305x-esw",
 240                 .owner = THIS_MODULE,
 241         },
 242 };
 243
 244 static int __init
 245 rt305x_esw_init(void)
 246 {
 247         return platform_driver_register(&rt305x_esw_driver);
 248 }
 249
 250 static void __exit
 251 rt305x_esw_exit(void)
 252 {
 253         platform_driver_unregister(&rt305x_esw_driver);
 254 }